JPH0616261B2 - Display controller - Google Patents

Description

The present invention relates to a display controller used in a terminal of an electronic computer, a video game, or the like.

[Prior art]

In recent years, CRTs have been controlled under the control of a CPU (central processing unit).
(CRT) Various display controllers have been developed for displaying moving images and still images on the screen of a display device. FIG. 1 is a block diagram showing the configuration of a color display device using this type of display controller. In FIG. 1, 2 is a CPU, 3 is a ROM (read only memory) in which programs used in the CPU 2 are stored, and data. A memory composed of a RAM (random access memory) for storage, 4 is a VRAM (video R)
AM) and 5 are CRT display devices. In this case, VRA
M4 includes a still image pattern table in which a plurality of still image patterns (dot patterns) are stored, a still image position table in which the positions at which the still image patterns should be displayed are stored, and the color of each still image pattern is a color code (4 (Bit) still image color table, a moving image pattern table that stores a plurality of moving image patterns, a moving image display that stores the X and Y coordinates of the position where the moving image pattern should be displayed and the color (color code) of the moving image pattern Each table is provided, and writing of each table is CP
Performed by U2. Then, the color display controller 1 outputs V based on the display command from the CPU 2.
A moving image pattern, a still image pattern, a color code, etc. in the RAM 4 are successively output, and RGB is output based on the continuously output data.
A (red, green, blue) color signal is created and output to the CRT display device 5 together with a synchronization signal. As a result, the moving image pattern and the still image pattern are displayed in color on the CRT screen. Further, the moving of the moving image pattern is performed by changing the X and Y coordinates of the moving image display table in the VRAM 4,
It is performed by rewriting by the program of the CPU 2.

By the way, in the conventional display controller 1, an interrupt signal to the CPU 2 is generated at the time point when the entire scanning of one screen is completed. Therefore, rewriting of the VRAM 4 during image display or display Processing such as rewriting of registers in the controller 1 could be performed only during the vertical blanking period.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and an object thereof is to be able to generate an interrupt signal at the time when horizontal scanning of a screen is completed. Therefore, even when the CPU rewrites VRAM during the horizontal blanking period. It is to provide a display controller capable of performing processing.

[Characteristics of the Invention]

The present invention is directed to a horizontal counter that counts dot clock pulses corresponding to each dot displayed on the screen of a display device and outputs a horizontal pulse, a vertical counter that counts horizontal pulses, and a scan output from a central processing unit. A register that stores the line number, the register output is compared with the vertical counter count output, and a match circuit that outputs a match signal when the two match, and a predetermined value when the horizontal counter count output reaches a predetermined value It is characterized by comprising a decoder for outputting a detection signal and an interrupt signal output circuit for outputting an interrupt signal to the central processing unit based on the coincidence signal and the predetermined value detection signal.

[Embodiment] FIG. 2 is a block diagram showing a configuration of a color display device by dot display using a display controller 7 according to an embodiment of the present invention. In this figure, the timing signal generating circuit 8 generates a basic clock pulse by a crystal oscillator provided inside,
The dot clock pulse DCP and the synchronization signal SYNC are generated based on this basic clock pulse. And
The dot clock pulse DCP is output to the clock terminal CK of the horizontal counter 9, and the synchronization signal SYNC is output to the CRT display device 5. Where dot clock pulse D
CP is a clock pulse corresponding to each dot displayed on the CRT display screen, in other words, a clock pulse output in synchronization with the display timing of each dot sequentially displayed by horizontal scanning of the screen. The timing signal generating circuit 8 also generates various timing signals necessary for processing the image data and outputs them to the image data processing circuit 10.

The horizontal counter 9 is a 341-ary up counter, which is initially reset at the start of screen display, and outputs a horizontal pulse HP to the clock terminal CK of the vertical counter 11 every time the dot clock pulse DCP counts 341 pulses. The count output of the horizontal counter 9 indicates which dot from the left of the screen the electron beam of the CRT display device 5 scans. That is,
For example, when the count output is "0", the scanning of the electron beam is at the leftmost end of the screen, and when it is "100", the electron beam is scanning the 101st dot position from the left of the screen.
It should be noted that in this embodiment, one horizontal line of the screen has 256 lines.
It is designed to display dots. Therefore, an apparent horizontal blanking period is provided when the count output of the horizontal counter 9 is between "256" and "340".

The vertical counter 11 is a 262-ary up counter,
Initial reset is performed at the start of screen display. The count output of the vertical counter 11 is the CRT display device 5.
Shows which line the electron beam of is scanning from the top of the screen. Further, in this embodiment, the number of lines is 192, and therefore, the vertical count output between "192" and "261" is an apparent vertical blanking period.

Next, the VRAM 4 has the same configuration as that shown in FIG. 1, and is internally provided with a still picture pattern table, a still picture position table, a still picture color table, a moving picture pattern table, and a moving picture display table. This VRAM4
The data to be written in each table is output from the CPU 2 and supplied to the image data processing circuit 10 via the interface circuit 12. The image data processing circuit 10 sequentially writes each supplied data into each table of the VRAM 4. Next, after the writing in the VRAM 4 is completed, the CPU 2
When the display command is output from the image data processing circuit 10, the image data processing circuit 10 continuously outputs each data in the VRAM 4 and determines which color dot display should be performed at each dot position on the CRT screen based on the continuously output data. Detect and level counter 9
A color code (4 bits) is sequentially output from the terminal TG in accordance with the scanning position of the electron beam indicated by each count output of the vertical counter 11 and is supplied to the color palette 13.

The color palette 13 is a kind of code conversion circuit, and
The bit color code is converted into 9-bit color data and output. This color palette 13 is, for example, # 0.
The data in the latch corresponding to the supplied color code is output as color data. The 16 latches # 9 to # 15 (each 9 bits) and the decoder for decoding the color code are provided. Then, the upper 3 bits of the output color data are the green color data GD,
The middle 3 bits are output as red color data RD and the lower 3 bits are output as blue color data BD to a DAC (digital / analog converter) 14. DAC
Reference numeral 14 converts the color data GD, RD, BD into a green color signal GV, a red color signal RV, and a blue color signal BV (all are analog signals), and outputs them to the CRT display device 5. Note that FIG. 3 shows an example of the correspondence relationship among the color code, the color data, and the display color. The data written in the latch in the color palette 13 is the CPU
2 through the interface circuit 12.

Next, the interrupt processing circuit 16 will be described. The interrupt processing circuit 16 is a circuit for generating an interrupt signal IR for the CPU 2, and a register 17 in which a line number (scanning line number) supplied from the CPU 2 via the interface circuit 12 is written, and in this register 17. Line number and the count output of the vertical counter 11 are compared, and the coincidence circuit 18 which outputs a coincidence signal D (“1” signal) when both coincide with each other and the count output of the horizontal counter 9 are “25”.
6 ", a decoder 19 that outputs a predetermined value detection signal (" 1 "signal), and an AND gate (interrupt signal output circuit)
20 and 20. When the CPU 2 writes, for example, the line number “20” in the register 17,
When the count output of the vertical counter 11 reaches “20”, that is, when the scanning of the 21st line from the top of the screen is started, the match circuit 18 outputs the match signal D (“1” signal). As a result, the AND gate 20 is opened. Next, when the scanning of the 21st line is completed, the count output of the horizontal counter 9 becomes "25".
6 ", a predetermined value detection signal (" 1 "signal) is output from the decoder 19, the" 1 "signal passes through the AND gate 20 and is output as an interrupt signal IR, and is output to the CPU 2 via the interface circuit 12. Supplied.

As described above, in the embodiment shown in FIG. 2, the interrupt signal IR to the CPU 2 can be generated at the time when the horizontal scanning of the screen is completed. As a result, the CPU 2 rewrites the VRAM 4 in the horizontal blanking period, Processing such as rewriting of the latch in the color palette 13 can be performed. Further, according to the above-described embodiment, it is possible to determine which line at which the scanning of the interrupt signal IR is generated at the end of scanning.
Since it can be designated by PU2, the following processing is possible. For example, if the line number of the center line of the screen is set in the register 17 and each latch in the color palette 13 is rewritten when the interrupt signal IR based on the line number is generated, the upper half of the screen is displayed. It is possible to completely change the color and the display color of the lower half. Further, for example, when the line number of the next line is set in the register 17 each time the horizontal scanning is completed, the interrupt signal IR is generated every time the horizontal scanning of one line is completed. If each latch in the color palette 13 is rewritten each time the interrupt signal IR is generated, 512 colors (corresponding to the bit number 9 of the latch) can be displayed for each line, and , The entire screen can be displayed in 512 colors.

〔The invention's effect〕

As described above, according to the present invention, the horizontal counter that counts the dot clock pulse corresponding to each dot displayed on the screen of the display device and outputs the horizontal pulse, the vertical counter that counts the horizontal pulse, The register that stores the scanning line number output from the central processing unit is compared with the output of the register and the count output of the vertical counter, and the match circuit that outputs a match signal when both match and the count output of the horizontal counter are Since the decoder for outputting the predetermined value detection signal when the predetermined value is reached and the interrupt signal output circuit for outputting the interrupt signal to the central processing unit based on the coincidence signal and the predetermined value detection signal are provided, the CPU
Can perform each processing in the horizontal blanking period, and can change the screen display more variably than before.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a display device using a display controller, FIG. 2 is a block diagram showing a configuration of a display device using a display controller 7 according to an embodiment of the present invention, and FIG. 3 is a color diagram. It is a figure which shows the correspondence of a code, color data, and a display color. 2 ... Central processing unit (CPU), 7 ... Display controller, 9 ... Horizontal counter, 11 ... Vertical counter, 17 ... Register, 18 ... Matching circuit, 19 ... Decoder, 20 ... AND gate ( Interrupt signal output circuit),
IR: Interrupt signal, D: Match signal.

Front page continuation (72) Inventor Takaju Ishii Minami-Aoyama 5-11-5 Tokyo Minato-ku 5-11-5 Stock Company ASCII (72) Inventor Ryozo Yamashita Minami-Aoyama 5-11 Minami-Aoyama Tokyo Stock Company Ascii (72) Inventor Takatoshi Okumura 10-1 Nakazawa-machi, Hamamatsu-shi, Shizuoka, Japan Musical Instruments Manufacturing Co., Ltd. 56) References JP-A-56-14291 (JP, A) JP-A-56-140433 (JP, A) Actual opening Sho-56-74738 (JP, U) Actual opening Sho-57-56893 (JP, U)

Claims (1)

[Claims] 1. A display controller for displaying an image on a display device of a raster scan system under the control of a central processing unit, counting dot clock pulses corresponding to each dot displayed on the screen of the display device. A horizontal counter that outputs a horizontal pulse, a vertical counter that counts the horizontal pulse, a register that stores a scanning line number that is output from the central processing unit, and an output of the register and a count output of the vertical counter are compared. Then, a match circuit that outputs a match signal when both match, a decoder that outputs a predetermined value detection signal when the count output of the horizontal counter reaches a predetermined value, and a match signal and the predetermined value detection signal And an interrupt signal output circuit for outputting an interrupt signal to the central processing unit based on the above. Display controller.