JPH0616293B2 - Image processing device - Google Patents

Description

The present invention relates to an image processing apparatus suitable for use in processing video data.

One of the digital memory devices, which can input a plurality of data at the same time or output a plurality of data at the same time (referred to as array memory), is used for processing such as filtering of video data. The conventional array memory has a drawback that it cannot be efficiently processed according to the window (for example, one unit required for filtering) of the image data to be processed because the array structure is fixed. When different processing such as a one-dimensional digital filter and a two-dimensional digital filter is simulated by one video image processing device,
The flexibility of the video image processing apparatus can be improved if the array structure according to the object can be taken.

Furthermore, since the conventional array memory has a structure in which the data in the memory cannot be moved within this memory, the contents of the array memory can be changed even when updating one data or shifting each other. All had to be replaced, and there was a drawback that the efficiency of data transfer was poor.

The present invention solves the problems of the conventional array memory. It is an object of the present invention to realize an image processing apparatus that can change the form of an array according to the data processing to be performed and can replace the data in the array.

An embodiment in which the present invention is applied to a video image processing apparatus will be described below with reference to the drawings.

FIG. 1 shows the overall construction of an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an I / O control unit,
The analog video signals input from the ITV2 and VTR3 are quantized by 8 bits at a sampling period of 70 nsec and transferred to the memory unit 5. Also, the processed data is transferred from the memory unit 5 to the I / O control unit 1
Sent to the D / A converter of the
It is supplied to the VTR 3 and the monitor receiver 4. The analog input / output signals are composite signals or component signals (YU
V, YIQ, RGB).

The memory unit 5 is normally composed of several banks and is for storing input data, output data, and temporary data. One bank is (76
It is composed of 8 × 256) pixels and corresponds to one field of a video signal. The memory unit 5 can be freely expanded in bank units.

Further, 7 is n array memories M ₁ , M ₂ , ... M.
_An array memory group consisting of _n-1 and Mn is shown. In order to control the data transfer between the memory unit 5 and the array memory group 7 and the internal data transfer of each of the array memories M _{1 to} Mn, a delay calculation unit 6 which calculates a predetermined address and generates a control signal. Is provided. The delay operation unit 6 also has a sophisticated operation function in order to enable complicated position conversion.

Reference numeral 8 indicates a product-sum operation unit. The Yunitsuto 8 consists of a control Units - _C 1 to Cn array memory _M 1 n pieces of product sum coupled with each of ~Mn processor _P 1 to PN and for each of the product-sum processor _P 1 to PN. Decentralized control can be performed by providing dedicated control units C _{1 to} Cn for each of the product-sum processors P _{1 to} Pn. The output data from each of the product-sum processors P _{1 to} Pn of the product-sum operation unit 8 is written in the memory unit 5.

Reference numeral 9 indicates a main control unit for managing the entire video image processing apparatus.

The main control unit 9 allows the product-sum processors P ₁ -P _{1 of} the delay operation unit 6 and the product-sum operation unit 8 to be processed.
Initialization of Pn is performed, and the microprograms and coefficient tables necessary for these are supplied from the main control unit 9.

This microprogram is for the whole video image processing device,
The delay operation unit 6 and the product-sum operation unit 8 can be divided into those for controlling the product-sum processors P _{1 to} Pn, but they have the following four operating modes as a whole.

(a) External mode: This is a mode in which a micro program and a coefficient table are transferred from the main control unit 9 to the control units C _{1 to} Cn of the delay calculation unit 6 and the integration calculation unit 8.

(b) Internal mode: This is a mode in which the control units C _{1 to} Cn of the main control unit 9, the delay calculation unit 6, and the integration calculation unit 8 control themselves by the micro programs.

(c) Debug mode: This is a mode for debugging each microprogram.

(d) Interrupt mode: This mode puts everything under the control of the main control unit 9 so as to switch from the internal mode to the external mode.

FIG. 2 shows the interconnection network between the memory unit 5, the array memory group 7 and the sum-of-products processors P ₁ -Pn.

In principle, necessary data is read from the memory unit 5 once per pixel and input to the input side data bus 10 every 70 nsec. The input side data bus 10 supplies input data to the array memories M _{1 to} Mn of the array memory group 4 in parallel.

For the array memories M _{1 to} Mn, the product sum processor P ₁ to
Input data required by Pn is taken in, and each of the product-sum processors P _{1 to} Pn performs a predetermined arithmetic process using this input data.

The data processed by the product sum processors P _{1 to} Pn is 70
The data is sequentially output to the output-side data bus 11 every n seconds and written to the memory unit 5 from this bus 11. In FIG. 2, array memories M _{1 to} Mn and product-sum processors P _{1 to} Pn shown in a ring shape are shown.
Is considered to be rotating in the clockwise direction indicated by the arrow. The time required for this one rotation becomes (70 × n) nsec, and the product-sum processors P _{1 to} Pn finish the processing within the time of this one rotation and output the processed data to the output side data bus 1
Output to 1.

The delay operation unit 6 controls the memory unit 5, the array memory group 7, the input side data bus 10 and the output side data bus 11 to perform the above-mentioned operation.

The mutual connection network shown in FIG. 2 can prevent memory contention.

Further, each array memory M _{1 to} M of the array memory group 7 is
Since each n can freely change its array structure, it can take an optimum array structure according to the processing purpose, which contributes to speeding up of processing and efficiency of data transfer.

As an example, FIG. 3 shows an array memory in which various registers can be formed by connecting a plurality of registers through tristate gates and controlling the tristates by the delay operation unit 6.

In FIG. 3, R _i represents a parallel-input parallel-output 8-bit shift register, and each output control terminal is at a low level so that an output can be generated. Shift registers R ₃₁ , R ₃₂ , R ₃₃ , R ₃₄ and R ₃₅ are connected in parallel to the input side data bus 10. By controlling the supply of the shift pulses T ₁ , T ₂ , T ₃ , T ₄ , T _{5 to} each of the shift registers R _{31 to} R _35, the input data is taken into only the desired shift register, and the shift data is shifted. Input data is output synchronously from a plurality of registers. Further, the shift pulse T ₆ is commonly supplied to each of the shift registers R _{1 to} R ₂₇ .

5 shift registers R ₁ for shift register R ₃₁
~ R ₅ are connected in cascade, and the shift register R ₅ is connected to the shift register R ₆ via the tri-state G ₁ .
A shift register R ₃₂ is connected to the shift register R ₆ via a tristate G ₂ . Also, between the shift registers R ₇ and R ₈ , between R ₃₂ and R ₈ , between R ₉ and R ₁₀ , and between R ₃₂ and R ₁₀ , tristates G ₃ , G
₄ , G ₅ and G ₆ are inserted respectively. Similarly, between shift registers R ₁₀ and R ₁₁ , between R ₃₃ and R ₁₁ , R ₁₄ and R
₁₅ during, between R ₃₃ and R _15, tri-state _G 7 between R ₃₂ and _{R 15, G 8, G 9} , G 10, G 11 are inserted respectively. Furthermore, similarly, between shift registers R ₁₅ and R ₁₆ ,
Between R ₃₄ and R ₁₆ , between R ₁₈ and R ₁₉ , between R ₃₃ and R ₁₉ , between R ₂₀ and R ₂₁ , between R ₃₅ and R ₂₁ , R ₂₁ and R
₂₂ during the tristate G ₁₂ between R ₃₄ and R _22,
G ₁₃ , G ₁₄ , G ₁₅ , G ₁₆ , G ₁₇ , G ₁₈ , and G ₁₉ are inserted, respectively.

The outputs of the shift registers R _{1 to} R ₂₇ are supplied to corresponding ones of the product-sum processors P _{1 to} Pn via tristates (not shown). Shift register R ₁
To R ₂₇ , R _{31 to} R ₃₅ , shift pulses and output control signals, and tristates G _{1 to} G
_The control signal for each of ₁₉ is generated in the delay calculation unit 6.

The array memory shown in FIG. 3 can have the array structure shown in each of FIGS. 4A to 4E. First, the shift clock T ₁ is supplied to the shift register R ₃₁ to take in the input data, and the tristates G ₁ , G ₃ , G
_By setting the control signals for ₅ , G ₇ , G ₉ , G ₁₂ , G ₁₄ , G ₁₆ , and G ₁₈ to low levels, making them active, and setting the other tristates to high impedance, FIG. As shown in A, an array structure is formed in which all the shift registers R ₁ to R ₂₇ are cascade-connected. As an example, this array structure is used when simulating a one-dimensional digital filter.

Further, the input data are sequentially fetched into the shift registers R ₃₁ and R ₃₂ , and the input data are output in synchronization with each other, and the tristates G ₁ , G ₃ , G ₅ , G ₇ , G ₁₁ , G ₁₁ ,
By setting G ₁₂ , G ₁₄ , G ₁₆ , and G ₁₈ to the active state and the other tristates to the high impedance state, as shown in FIG. 4B, the shift register R ₁
An array structure is formed having a first row of 14 shift registers from R to R ₁₄ and a second row of 13 shift registers from R ₁₅ to R ₂₇ .

In addition, input data is taken into each of the shift registers R ₃₁ , R ₃₂ , and R ₃₃ , and tristates G ₁ , G ₃ , G ₆ , and G are stored.
_By setting ₇ , G ₉ , G ₁₂ , G ₁₅ , G ₁₆ , G ₁₈ in the active state and the other tristates in the high impedance state, as shown in FIG. 4C, an array of (3 × 9) array is formed. The structure is realized.

In addition, input data is taken into each of the shift registers R ₃₁ , R ₃₂ , R ₃₃ , and R ₃₄ , and tristates G ₁ , G ₄ , and G are stored.
_By setting ₅ , G ₇ , G ₁₀ , G ₁₂ , G ₁₄ , G ₁₆ , and G ₁₉ in the active state and the other tristates in the high impedance state, as shown in FIG.
From the row to the 3rd row is composed of 7 shift registers,
An array structure is realized in which the fourth row is composed of 6 shift registers.

Further, the input data is taken into each of the shift registers R ₃₁ , R ₃₂ , R ₃₃ , R ₃₄ , and R ₃₅ , and tristates G ₂ , G ₃ , G ₅ , G ₈ , G ₉ , G ₁₃ , G are tristated. ₁₄ , G ₁₇ ,
With G ₁₈ in the active state, as shown in FIG. 4E, an array structure in which the first to fourth rows are composed of five shift registers and the fifth row is composed of seven shift registers is provided. Will be realized.

The above-mentioned array structures of FIGS. 4B, 4C, 4D, and 4E are applied when performing simulation of a two-dimensional digital filter, for example. That is, the video image processing apparatus according to this embodiment includes a digital filter, a special effect device such as image conversion, a color encoder,
Various simulations such as color decoder and fast Fourier transform can be performed.

As can be understood from the above description of the embodiment, according to the present invention, the structure of the array can be changed by the external control signal, and the data can be shifted within the array. Therefore, there is an advantage that the data in the array can be updated only with a slight data replacement.
According to the present invention, the speed of data processing can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall construction of an embodiment of the present invention, FIG. 2 is a schematic diagram used for explaining an interconnection network in an embodiment of the present invention, and FIGS. 3 and 4 are FIG. 3 is a block diagram of an example of a specific configuration of an array memory in one embodiment of the present invention and a schematic diagram used for explaining the operation thereof. 1 ... I / O control unit, 5 ... Memory unit, 6 ... Delay operation unit, 7 ... Array memory group, 8 ... Multiply-accumulate operation unit, 9 ... Main control unit.

Claims (1)

[Claims] 1. A memory for storing image signals, and a plurality of array memories to which signals from the memories are respectively inputted.
Image processing including a plurality of arithmetic units for performing signal processing on signals supplied from each of the plurality of array memories, and control means for controlling the memories, the array memories and the arithmetic units based on a signal processing program. In the apparatus, each of the plurality of array memories is provided in parallel with respect to a signal from the memory, and a plurality of selecting means for selecting and outputting a signal from the memory and a plurality of cascaded ( In each of the plurality of (n) memory element groups and the plurality of (n) memory element groups connected to the respective outputs of the plurality of selecting means, A memory device connecting / disconnecting means for connecting / disconnecting a predetermined memory device, and a memo for connecting / disconnecting a predetermined memory device of different memory device groups among the plurality of memory device groups. An element group connecting / disconnecting means, and the control means controls the plurality of selecting means, the memory element connecting / disconnecting means, and the memory element group connecting / disconnecting means to use the memory elements of m × n. The array memory has M rows and N columns (where M and N are integers and M × N ≦
The image processing apparatus is characterized in that a predetermined array structure of (m × n) is set.