JPH0616295B2 - Image processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and in particular to a facsimile,
Used in scanners, etc., for example, when scanning a binary image in which characters and halftone dots are mixed, separating the image areas in order to improve the quality of both images, and performing processing suitable for each image. The present invention relates to an image processing device that generates pattern determination area data.

2. Description of the Related Art In recent years, due to the demand for high-speed, high-performance image processing technology, multi-value halftone processing, pseudo-halftone processing, binarization processing, compression processing,
Image processing such as image quality improvement processing has been realized by hardware.

Most of these image processes are performed by determining a pattern of image correlation between a pixel of interest centered on the pixel of interest, that is, a pixel of interest in a so-called scanning window and peripheral pixels.

Therefore, there is a demand for a means for storing the result of determining the pattern in the scanning window while sequentially updating it as the scanning window moves.

For example, when processing character / halftone dot areas under different image processing conditions, it is necessary to sequentially select the data from each image processing circuit in pixel units according to the pattern determination area data.

Since a halftone dot is an image isolated from the surrounding image like a dot, it must be a halftone dot area including the surroundings of the point, and a means for that is required.

In that case, unless the result of the determination according to the movement of the scanning window is spread on the surface, the area around the point does not become a halftone dot area.

Since a circuit having such a function has not been proposed in the past, it was not possible to realize area separation of a binary image in which characters / dots are mixed.

Problems to be Solved by the Invention The present invention has been made in view of the above-mentioned demands of the related art. Therefore, an object of the present invention is to set pattern judgment area data by inputting pattern judgment data. It is to provide a new image processing device.

Means for Solving the Problems In order to achieve the above object, an image processing apparatus according to the present invention includes first to third OR gates, an output of the first OR gate, and an input of the second OR gate. And a first connected between the output of the second OR gate and the input of the third OR gate
And a second one-pixel delay circuit, fourth to sixth OR gates, an output of the fourth OR gate, an input of the fifth OR gate, an output of the fifth OR gate, and an output of the sixth OR gate. Third and fourth one-pixel delay circuits connected between the input, the seventh to ninth OR gates, the output of the seventh OR gate, the input of the eighth OR gate, and the eighth OR. A fifth connected between the output of the gate and the input of the ninth OR gate
And a sixth 1-pixel delay circuit, connected between the output of the third OR gate and the output of the fourth OR gate, and between the output of the sixth OR gate and the input of the seventh OR gate. The first to ninth OR gates are black in the middle and data around the middle pixel of the white pixel pattern is "1".
It is characterized in that pattern determination data for each pixel whose data for the pixel in the center other than the above pattern is "0" is simultaneously input, and an output signal is taken out from the output of the ninth OR gate.

Examples Hereinafter, the present invention will be described in detail with reference to the accompanying drawings with reference to the drawings.

Here, for convenience of description, as an example of pattern determination, a case of determining a black pixel surrounded by white pixels will be described, and the scanning window size will be described as 3 × 3.

FIGS. 1 (a) to 1 (c) are diagrams for explaining a process of setting a pattern determination area from pattern determination data.

FIG. 1 (a) is pattern determination data (for example, halftone dot detection data obtained by scanning image data in advance), FIG. 1 (b) is original image data of black pixels surrounded by white pixels, and FIG. FIG. 7C is a diagram showing the pattern determination area in FIG. In FIG. 1 (b), the scanning window moves one pixel at a time in the main scanning direction, and when all the main scanning pixels move, returns to the main scanning start position, moves one pixel in the sub scanning direction, and moves in the main scanning direction. 1
It shall be repeated to move pixel by pixel.

Here, the condition of black pixels surrounded by white pixels is the pattern determination standard. The pattern is determined in accordance with the movement of the scanning window, and when the condition of black pixels surrounded by white pixels is satisfied, it is expressed as black, and when it is not satisfied, it is expressed as white.
, Which indicates the pattern determination area.

FIG. 2 is a block diagram showing an embodiment of the present invention.

Referring to FIG. 2, the pattern judgment data applied to the input terminal T1 is OR gates 1A, 1B, 1C, 1D, 1
E, 1F, 1G, 1H, 1I. Here, regarding the logic of the pattern determination data, "1" is set when the above condition is satisfied, and "0" is set when the above condition is not satisfied.

When the pattern is judged in accordance with the movement of the scanning window and the above conditions are satisfied, the output of each OR gate becomes "1" and the pattern judgment area data for 3 × 3 pixels of the scanning window is refined and output terminal T2. Is output to. The pattern determination area data includes 1-pixel delay elements 2A, 2B, 2C, 2D, 2
E, 2F and 1 scan line delay elements 3A, 3B, 3C, 3
Stored by D and updated in the scan window as it moves.

One scanning line delay element is composed of two per scanning line, and writing and reading operations are alternately performed to simplify address control associated with data delay in each one-pixel delay element stage and enable high-speed operation. Becomes

The address counter 5A designates a read address, and the address counter 5B designates a write address. The address counter 5A uses a 1-scan line processing valid signal VAR input from a terminal T3 and a 1-pixel clock CK1 input from a terminal T4. Operate.

The 1/2 frequency divider circuit 6 supplies a signal R / W designating a write or read mode to the selectors 4A, 4B, 4C, 4D and the write signal generation circuits 7A, 7B.

The write signal generation circuits 7A and 7B generate write signals WE1 and WE2 by the CK1, the pixel clock CK2 which is twice the CK1 input from the terminal T5, and the signal R / W.

The 1-pixel delay elements 2G, 2H are 1-pixel delay elements 2A, 2B, 2C, 2D, 2 for storing pattern determination area data.
The delay difference between the write address and the read address due to the data delay at E and 2F is matched.

In the above description, the scanning window size is 3 × 3, but the size is not limited to this example.

EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to set pattern determination area data by inputting pattern determination data.

[Brief description of drawings]

1 (a) to 1 (c) are views for explaining the process of setting a pattern judgment area from pattern judgment data, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1
I ... OR gate, 2A, 2B, 2C, 2D, 2E, 2
F, 2G, 2H ... 1 pixel delay element, 3A, 3B, 3
C, 3D ... 1 scanning line delay element, 4A, 4B, 4C, 4
D: selector, 5A: read address counter,
5B ... write address counter, 6 ... 1/2 frequency divider circuit, 7A, 7B ... write signal generating circuit

Claims (1)

[Claims] 1. First to third OR gates (1A, 1B, 1)
C) and the first and second 1's connected between the output of the first OR gate and the input of the second OR gate and between the output of the second OR gate and the input of the gate of the third OR. The pixel delay circuit (2A, 2B) and the fourth to sixth OR gates (1
D, 1E, 1F), the output of the fourth OR gate, the input of the fifth OR gate, the output of the fifth OR gate, and the sixth
3rd and 4th 1 connected between the input of the OR gate of
Pixel delay circuit (2C, 2D), seventh to ninth OR gates (1G, 1H, 1I), output of seventh OR gate, input of eighth OR gate, and output of eighth OR gate The fifth and sixth 1-pixel delay circuits (2E, 2F) connected between the input and the input of the ninth OR gate, and the third OR
A first line delay means connected between the output of the gate and the output of the fourth OR gate and between the output of the sixth OR gate and the input of the seventh OR gate; Each of the OR gates 9 has a data of "1" for the pixel in the center of the pattern of black pixels in the center and a white pixel around it, and a data of "0" for the pixel in the center other than the above pattern. An image processing apparatus, wherein pattern judgment data is inputted at the same time, and an output signal is taken out from an output of the ninth OR gate.