JPH061635B2 - Sense amplifier circuit - Google Patents

Description

The present invention relates to a sense amplifier circuit suitable for a memory circuit composed of MISFETs (insulated gate field effect transistors).

[Prior art]

In a dynamic memory circuit using MISFET,
As a so-called sense amplifier circuit for amplifying a minute potential difference read from a memory cell, a circuit based on a flip-flop circuit is usually used. An example of such a circuit is shown in FIG. 3 (for example, Nikkei Electronics January 8, 1979, pages 110 to 133).

In FIG. 3, the MISFET 3 is in the cutoff state due to the potentials applied to the clock terminal 19 and the clock terminal 20 immediately before the amplification operation.
4 and 5 are conductive. Therefore, the input terminals 15 and 16
Is being applied to. The potentials are output terminals 17 and 18 respectively.
The stray capacitances present at the output terminals 17 and 18 that are transmitted to are charged to the input potential.

At the time of amplification, first, the potential of the clock terminal 20 is changed to shut off the MISFETs 4 and 5. Next, the potential of the clock terminal 19 is changed to make the MISFET 3 conductive. As a result, the MISFETs 1 and 2 form a flip-flop circuit, and the output terminals 17 and 1
Of the eight, the terminal closer to the potential VSS of the power supply 21 immediately before the amplification operation is discharged to the potential VSS, and the potential of the other output terminal hardly changes, and as a result, it is applied to the input terminals 15 and 16. The potential difference that has been present is amplified and obtained at the output terminals 17 and 18.

[Problems of conventional technology]

In the above amplification operation, since the output terminals 17 and 18 are charged in the floating capacitance, the potential cannot change rapidly and it takes some time. Therefore, when the potential of the connection point 22 is suddenly changed, both MISFETs 1 and 2 become conductive, and correct amplification operation cannot be expected.

In order to explain this in detail, it is assumed that the potential applied to the input terminal 15 is closer to VSS than the potential applied to the input terminal 16. MISF in this state
When ET4 and 5 are cut off, MISFET3 is made conductive, and the potential of the connection point 22 is gradually brought close to VSS, first M
ISFET1 becomes conductive. As a result, even if the potential of the output terminal 17 approaches VSS and the potential of the connection point 22 approaches VSS, the MISFET 2 is kept in the cutoff state. In this way, only the potential of the output terminal 17 eventually reaches VSS. However, if the potential of the connection point 22 changes too rapidly and the change in the potential of the output terminal 17 cannot catch up, the gate-source voltage of the MISFET 2 also becomes MI.
The voltage becomes equal to or higher than the threshold voltage of SFET2 and the SFET2 becomes conductive. Then, the potential of the output terminal 18 also changes toward VSS. Therefore, correct amplification operation cannot be expected.

As described above, in order for the circuit shown in FIG. 3 to operate properly, the voltage waveform applied to the clock terminal 19 must be adjusted so that the potential at the connection point 22 changes sufficiently slowly. The larger the stray capacitance, the slower the change of the output terminals 17 and 18, and therefore the potential of the connection point 22 must be changed slowly.

Generally, it is desired that the time required for amplification is short, and for that purpose, it is necessary to reduce the stray capacitance of the output terminals 17 and 18.

However, in the holding state after amplification, the output terminal 17
If the stray capacitances of 18 and 18 are too small, even if a slight amount of current noise is applied to this terminal, the potential changes greatly and, as a result, the stored contents are destroyed.

As described above, in the circuit conventionally used, the stray capacitance of the output terminal must be reduced in order to speed up the amplification operation, but if it is too small, the resistance to noise in the held state becomes weak. There is a problem in that it cannot be made too small, and therefore a sufficiently high speed cannot be achieved.

[Object of the Invention]

In view of this point, an object of the present invention is to provide a sense amplifier circuit that does not reduce the resistance to noise in the holding state even if the amplification operation is speeded up.

[Structure of Invention]

The sense amplifier circuit of the present invention comprises a first two-terminal load element having one end connected to a first power supply and the other end connected to a first output terminal, and one electrode connected to the first output terminal. A first MISFET having a gate electrode connected to a second output terminal and the other electrode connected to a first connection point; one end connected to the first power supply and the other end connected to the second output terminal Done second
And a second MISFE in which one electrode is connected to the second output terminal, a gate electrode is connected to the first output terminal, and the other electrode is connected to the first connection point.
T, a third MISFET in which one electrode is connected to the first connection point, a gate electrode is connected to the first clock terminal, and the other electrode is connected to a second power supply; and one electrode is a first
A gate electrode connected to a second clock terminal and the other electrode connected to the first output terminal
MISFET and a fifth MISFE having one electrode connected to the second input terminal, the gate electrode connected to the second clock terminal, and the other electrode connected to the second output terminal.
T, a sixth MISFET having one electrode connected to the first output terminal, a gate electrode connected to the second connection point, and the other electrode connected to the first connection point, and one electrode A seventh MISFET connected to the second output terminal, a gate electrode connected to a third connection point, and the other electrode connected to the first connection point; and one electrode connected to the second connection point. An eighth MISFET having a gate electrode connected to a third clock terminal and the other electrode connected to the second power supply (or the first connection point), and one electrode connected to the third connection point And the gate electrode is connected to the third clock terminal and the other electrode is connected to the second power source (or the first connection point).
And a MISFET connected to each other, and a first electrode having one electrode connected to the second output terminal, a gate electrode connected to a fourth clock terminal, and the other electrode connected to the second connection point.
0 MISFET and an eleventh MI1 having one electrode connected to the first output terminal, a gate electrode connected to the fourth clock terminal, and the other electrode connected to the third connection point.
It is composed of SFET.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In this example, the drain and gate electrodes are connected to the first power supply (power supply potential VDD) 25, and the source electrodes are connected to the first output terminal 17, which is a first two-terminal load element MISF.
ET11, the drain electrode is connected to the output terminal 17, the gate electrode is connected to the second output terminal 18, and the source electrode is the first.
Of the first MISFET 1 connected to the connection point 22 and the second MISFET as a second two-terminal load element in which the drain and gate electrodes are connected to the power supply 25 and the source electrode is connected to the output terminal 18.
SFET 12, a second MISFET 2 having a drain electrode connected to the output terminal 18, a gate electrode connected to the output terminal 17 and a source electrode connected to the connection point 22, and a drain electrode connected to the connection point 22 and a gate electrode being the first Connected to the clock terminal 19 of the source electrode of the second power supply (power supply potential VS
S) 21 connected to the third MISFET3, and a fourth MISFET4 having a drain electrode connected to the first input terminal 15 and a gate electrode connected to the second clock terminal 2 and a source electrode connected to the output terminal 17. A fifth MI in which the drain electrode is connected to the second input terminal 16, the gate electrode is connected to the clock terminal 20, and the source electrode is connected to the output terminal 18.
SFET5, a sixth MISFET6 having a drain electrode connected to the output terminal 17, a gate electrode connected to the second connection point 23, and a source electrode connected to the connection point 22, and a drain electrode connected to the output terminal 18 and a gate electrode To the third connection point 2
No. 7 and the source electrode is connected to the connection point 22
ISFET7, the drain electrode is connected to the connection point 23, the gate electrode is connected to the third clock terminal 26, the source electrode is connected to the power supply 21, and the drain electrode is connected to the connection point 24 and the gate electrode is connected. The ninth MISFET 9 connected to the clock terminal 26 and the source electrode connected to the second power supply 21, the drain electrode connected to the output terminal 18, the gate electrode connected to the fourth clock terminal 27, and the source electrode connected to the connection point 23. Tenth MISFET connected to
13, the drain electrode is connected to the output terminal 17, the gate electrode is connected to the clock terminal 27, and the source electrode is connected to the connection point 24.
And an eleventh MISFET 14 connected to.
Here, the MISFETs 1 to 9 and 11 to 14 are N-channel type.

Next, the operation of this embodiment will be described with reference to the time chart of each clock shown in FIG. Each MISFET
Conducts when the potential of the clock is 1 level, and shuts off when the potential of the clock is 0 level.

In FIG. 1, MISFETs 1, 2, 3, 4, and 5 have the same functions as those of the conventional circuit shown in FIG. Immediately before starting amplification, the MIS is generated by the clock 1 and the clock 2 applied to the clock terminals 19 and 20.
FET3 is cut off and MISFETs 4 and 5 are conducted. Further, the clock 3 applied to the clock terminal 26
Causes MISFETs 8 and 9 to conduct and clock terminal 27
The MISFETs 13 and 14 are cut off by the clock 4 applied to, and as a result, the MISFETs 6 and 7 are cut off. The MISFETs 11 and 12 function as load elements having two terminals.

During the amplifying operation, the potential of the clock terminal 20 is changed to shut off the MISFETs 4 and 5. After that, the potential of the clock terminal 19 is changed to make the MISFET 3 conductive. Then, the potential difference initially present at the output terminals 17 and 18 is amplified in the same manner as in the case of the circuit of FIG. However, one of the potentials after amplification may be almost VSS, but the other potential may not be VDD due to the action of the load element 11 or 12. Enhancement type MIS as shown in FIG.
When FETs are used, if the threshold voltage of the MISFETs 11 and 12 is VT, the other potential is VDD-VT.

After the amplification is completed, the potentials of the clock terminals 26 and 27 are changed by the clock 3 and the clock 4, the MISFETs 8 and 9 are cut off, and the MISFETs 13 and 14 are made conductive. For the sake of explanation, if the potentials of the output terminals 17 and 18 are VSS and VDD-VT, respectively, after completion of amplification, MISFE will be assumed.
Although T7 is still in the cutoff state, a current flows into the connection point 23 through the MISFET 13 and, after a sufficient time has passed, the potential of the connection point 23 is the same as VDD-VT of the output terminal 18.
Therefore, the MISFET 6 becomes conductive. Output terminal 17
If the potentials of 18 and 18 are opposite to each other, MISFET 7 is turned on while MISFET 6 remains in the cutoff state. MISF
ET6 and 7 are transistors with a large gate area,
Due to its gate capacitance, the stray capacitances at nodes 23 and 24 are quite large. Therefore, in this state, even if the potentials of the output terminals 17 and 18 change due to noise, the circuit states do not change due to the action of the MISFETs 6 and 7, and the potentials of the output terminals 17 and 18 immediately return to their original values.

That is, the circuit of FIG. 1 is concerned only with the stray capacitances of the output terminals 17 and 18 during the amplification operation, and high speed operation can be obtained by reducing the stray capacitance. On the other hand, in the holding state, large stray capacitances at the connection points 23 and 24 have an effect, and thus are strong against noise.

Although the source electrodes of the MISFETs 8 and 9 are connected to the electrode 21 in this embodiment, even if they are connected to the connection point 22, the same effect can be obtained.

Although the above description has been made for the N-channel type MISFET, the same applies to the case of using the P-channel type MISFET.

[Effects of the Invention] As described above, according to the present invention, since it has the above-mentioned means, it is possible to obtain a sense amplifier circuit that achieves both high-speed operation and noise resistance, and it is possible to obtain a MIS such as a dynamic memory.
It has a great effect in an integrated circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a time chart of its clock, and FIG. 3 is a circuit diagram showing a conventional example. 1-9, 11-14 ... N-channel type MISFET, 1
5, 16 ... Input terminal, 17, 18 ... Output terminal, 19,
20,26,27 …… Clock terminal, 20,21 …… Power supply, 22〜
24 ... Connection point.

Claims (1)

[Claims] 1. A first two-terminal load element having one end connected to a first power supply and the other end connected to a first output terminal, and one electrode connected to the first output terminal and a gate electrode connected to the first output terminal. A first electrode connected to the second output terminal and the other electrode connected to the first connection point
MISFET, a second two-terminal load element having one end connected to the first power supply and the other end connected to the second output terminal, and one electrode connected to the second output terminal and a gate electrode Is connected to the first output terminal and the other electrode is connected to the first output terminal.
And a second MISFET connected to the connection point of the third and a third electrode having one electrode connected to the first connection point, the gate electrode connected to the first clock terminal, and the other electrode connected to the second power supply.
And a fourth MISFET in which one electrode is connected to the first input terminal, the gate electrode is connected to the second clock terminal, and the other electrode is connected to the first output terminal.
And one electrode is connected to the second input terminal, the gate electrode is connected to the second clock terminal, and the other electrode is connected to the second electrode.
A fifth MISFT connected to an output terminal of the first and a first electrode connected to the first output terminal, a gate electrode connected to a second connection point, and the other electrode connected to the first connection point. 6, and a seventh MISFET having one electrode connected to the second output terminal, the gate electrode connected to a third connection point, and the other electrode connected to the first connection point,
An eighth MISFE in which one electrode is connected to the second connection point, the gate electrode is connected to the third clock terminal, and the other electrode is connected to the second power supply (or the first connection point).
T, one electrode connected to the third connection point, the gate electrode connected to the third clock terminal, and the other electrode connected to the second power supply (or the first connection point) MISFET 9 and a tenth MISFET having one electrode connected to the second output terminal, the gate electrode connected to the fourth clock terminal, and the other electrode connected to the second connection point.
And an eleventh MISFET having one electrode connected to the first output terminal, the gate electrode connected to the fourth clock terminal, and the other electrode connected to the third connection point. And sense amplifier circuit.