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JPH0616537B2 - Method for manufacturing semiconductor substrate - Google Patents
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JPH0616537B2 - Method for manufacturing semiconductor substrate - Google Patents

Method for manufacturing semiconductor substrate

Info

Publication number
JPH0616537B2
JPH0616537B2 JP58203808A JP20380883A JPH0616537B2 JP H0616537 B2 JPH0616537 B2 JP H0616537B2 JP 58203808 A JP58203808 A JP 58203808A JP 20380883 A JP20380883 A JP 20380883A JP H0616537 B2 JPH0616537 B2 JP H0616537B2
Authority
JP
Japan
Prior art keywords
substrate
single crystal
silicon single
layer
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58203808A
Other languages
Japanese (ja)
Other versions
JPS6095936A (en
Inventor
山本  和彦
真三郎 岩渕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP58203808A priority Critical patent/JPH0616537B2/en
Publication of JPS6095936A publication Critical patent/JPS6095936A/en
Publication of JPH0616537B2 publication Critical patent/JPH0616537B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment

Landscapes

  • Recrystallisation Techniques (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体基体特にSOI(Silicon on Insulato
r)基体の製造方法に関する。
Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor substrate, particularly SOI (Silicon on Insulato).
r) relates to a method of manufacturing a substrate.

〔発明の技術的背景〕[Technical background of the invention]

周知の如く、半導体素子の製造に際しては例えばSOS
(Silicon on Sapphine)基体が用いられている。かか
るSOS基体は、通常サフアイア基板(ウエハ)の表面
を十分平滑処理した後、該基板表面に気相成長により薄
い単結晶シリコン層を形成することによつて製造され
る。
As is well known, when manufacturing a semiconductor device, for example, SOS is used.
(Silicon on Sapphine) substrate is used. Such an SOS substrate is usually manufactured by sufficiently smoothing the surface of a sapphire substrate (wafer) and then forming a thin single crystal silicon layer on the substrate surface by vapor phase growth.

〔背景技術の問題点〕[Problems of background technology]

しかしながら、従来技術によれば、単結晶シリコン層の
結晶性に問題が生じ、結晶欠陥の発生や電気的特性の劣
化を招く。これは、気相成長過程の初期においてはウエ
ハの結晶構造の影響を受け、本来の結晶構造をとりにく
いことに起因する。つまり、結晶構造の完全さが得られ
るまでには、数百Å程度の膜厚を必要とする。このた
め、単結晶シリコン層の上層には完全結晶層が形成され
るが、下層の不完全結晶層の影響を受け完全結晶層に結
晶欠陥を生じやすく、不完全結晶層ではリーク電流が増
大する等の電気的特性が劣化し半導体基板に素子を形成
した場合、素子の高速化、高密度化の妨げとなつてい
る。
However, according to the conventional technique, a problem occurs in the crystallinity of the single crystal silicon layer, which causes the generation of crystal defects and the deterioration of electrical characteristics. This is because the crystal structure of the wafer is affected in the initial stage of the vapor phase growth process, and it is difficult to take the original crystal structure. In other words, a film thickness of several hundred Å is required until the complete crystal structure is obtained. Therefore, a complete crystal layer is formed in the upper layer of the single crystal silicon layer, but crystal defects are likely to occur in the complete crystal layer due to the influence of the incomplete crystal layer in the lower layer, and the leak current increases in the incomplete crystal layer. When the elements are formed on the semiconductor substrate due to deterioration in electrical characteristics such as the above, it is an obstacle to speeding up and increasing the density of the element.

〔発明の目的〕[Object of the Invention]

本発明は上記事情に鑑みてなされたもので、結晶欠陥の
発生や電気的特性の劣化を阻止し、素子の高速化、高密
度化が可能な半導体基体の製造方法を提供することを目
的とするものである。
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor substrate capable of preventing the occurrence of crystal defects and the deterioration of electrical characteristics, and increasing the speed and density of elements. To do.

〔発明の概要〕[Outline of Invention]

本発明は、表面が十分平滑に形成された半導体層と表面
が平滑に形成された絶縁性基板を、平滑表面が相接する
ように重ねた後、熱圧着することによつて前述した目的
を達成することを図つたものである。即ち、表面が研磨
により十分に平滑に形成された半導体層と、表面が研磨
により十分に平滑に形成された絶縁性基板とを別々の工
程で作成した後、両者を熱圧着して一体化して従来の如
く成長初期に半導体基板の結晶構造に左右される不完全
結晶層の発生を回避し、完全結晶状態の半導体層を有す
る半導体基体を形成するものである。
The present invention has the above-mentioned object by stacking a semiconductor layer having a sufficiently smooth surface and an insulating substrate having a smooth surface so that the smooth surfaces are in contact with each other and then thermocompression bonding. It aims to achieve it. That is, a semiconductor layer whose surface is sufficiently smoothed by polishing and an insulating substrate whose surface is sufficiently smoothed by polishing are prepared in separate steps and then thermocompression-bonded to integrate them. As in the prior art, generation of an incomplete crystal layer that depends on the crystal structure of the semiconductor substrate is avoided at the initial stage of growth, and a semiconductor substrate having a semiconductor layer in a completely crystalline state is formed.

〔発明の実施例〕Example of Invention

以下、本発明の一実施例を第1図(a)〜(c)を参照して説
明する。
An embodiment of the present invention will be described below with reference to FIGS. 1 (a) to 1 (c).

まず、半導体基板としての例えば砒素を高濃度にドープ
した比抵抗0.002 cmのシリコン単結晶基板1の表面をミ
ラー研磨した。つづいて、この基板1上に一般的な気相
成長技術により半導体層としての厚さ0.5μmのシリコ
ン単結晶層2を成長させた(第1(a)図示)。次いで、
上記と同様に表面がミラー研磨された絶縁性基板として
のSiO基板3を用意し、この基板3の表面上に前記
基板1を該基板1の単結晶層2がSiO基板3の表面
と接するように重ねた。しかる後、1×10−4torrの
真空中で950℃、500g/cm3の条件で1時間熱圧
着を行なつた(第1図(b)図示)。更に、降温を行なつ
た後、不純物濃度によりエツチング速度に選択性のある
フツ硝酸系エツチング液を用い、前記シリコン単結晶基
板1を除去して半導体基体を製造した。なお、上記エツ
チング液には、HF:HNO:CHCOOH−1:
3:8を用い、このときのエツチング速度はシリコン単
結晶基板1で2.3μm/min、シリコン単結晶層2で
ほぼ零であつた(第1図(c)図示)。
First, the surface of a silicon single crystal substrate 1 having a specific resistance of 0.002 cm, which is highly doped with arsenic as a semiconductor substrate, is mirror-polished. Subsequently, a 0.5 μm thick silicon single crystal layer 2 as a semiconductor layer was grown on this substrate 1 by a general vapor phase growth technique (first (a) shown). Then
In the same manner as above, a SiO 2 substrate 3 as an insulating substrate whose surface is mirror-polished is prepared, and the substrate 1 is provided on the surface of the substrate 1 with the single crystal layer 2 of the substrate 1 being the surface of the SiO 2 substrate 3. Layered to touch. Then, thermocompression bonding was performed for 1 hour at 950 ° C. and 500 g / cm 3 in a vacuum of 1 × 10 −4 torr (shown in FIG. 1 (b)). Further, after the temperature was lowered, the silicon single crystal substrate 1 was removed using a fluorine-nitric acid-based etching solution having an etching rate selectivity depending on the impurity concentration to manufacture a semiconductor substrate. Note that the etching solution, HF: HNO 3: CH 3 COOH-1:
3: 8 was used, and the etching speed at this time was 2.3 μm / min in the silicon single crystal substrate 1 and almost zero in the silicon single crystal layer 2 (shown in FIG. 1 (c)).

しかして、本発明によれば、シリコン単結晶層2を有す
るシリコン単結晶基板1とSiO基板3とを別々の工
程で作製した後、これらを熱圧着しシリコン単結晶基板
1を選択的にエツチングするため、従来と比べ結晶性が
完全なシリコン単結晶層2を得ることができる。
Therefore, according to the present invention, after the silicon single crystal substrate 1 having the silicon single crystal layer 2 and the SiO 2 substrate 3 are produced in separate steps, they are thermocompression bonded to selectively produce the silicon single crystal substrate 1. Since etching is performed, the silicon single crystal layer 2 having more complete crystallinity than that of the conventional one can be obtained.

従つて、従来問題となつていた結晶欠陥や電気特性の劣
化を阻止し、素子の高速化、高密度化が可能となる。な
お、上記実施例において、シリコン単結晶層2とSiO
基板3との熱圧着前後のラツピングした断面を顕微鏡
で撮影したところ、第2図(a),(b)に示す模式図が得ら
れた。ここで、同図(a)は熱圧着前の状態を、同図(b)は
熱圧着後の状態を夫々示す。同図(a),(b)より、熱圧着
前はシリコン単結晶層2とSiO基板3に境界面4が
存在したが、熱圧着後はこの境界面4が完全に消失して
いることが確認できる。これは、SiOは粘弾性体と
しての性質を持ち、高温では粘性流動が顕著に生じるた
めである。また、サフアイア基板上に厚さ0.3μmのシ
リコン単結晶層を設けたSOS基体を、従来の気相成長
法と本発明法により作製し、一定距離を隔てて設けた拡
散電極間のリーク電流を測定したところ、電流値は本発
明によるものが2桁の減少を示した。これにより、本発
明法が従来の場合と比べて優れていることが確認でき
る。
Therefore, it is possible to prevent the crystal defects and the deterioration of electric characteristics, which have been problems in the past, and to increase the speed and density of the device. In the above embodiment, the silicon single crystal layer 2 and SiO
When the lapped sections before and after thermocompression bonding with the two substrates 3 were photographed with a microscope, the schematic diagrams shown in FIGS. 2 (a) and 2 (b) were obtained. Here, (a) of the figure shows the state before thermocompression bonding, and (b) of the figure shows the state after thermocompression bonding. From FIGS. 2A and 2B, the boundary surface 4 was present between the silicon single crystal layer 2 and the SiO 2 substrate 3 before the thermocompression bonding, but this boundary surface 4 disappeared completely after the thermocompression bonding. Can be confirmed. This is because SiO 2 has a property as a viscoelastic body and viscous flow remarkably occurs at a high temperature. Further, an SOS substrate having a silicon single crystal layer having a thickness of 0.3 μm provided on a sapphire substrate was manufactured by the conventional vapor phase growth method and the method of the present invention, and leakage current between diffusion electrodes provided at a constant distance was measured. When measured, the current value according to the present invention showed a two-digit decrease. From this, it can be confirmed that the method of the present invention is superior to the conventional method.

なお、上記実施例では、シリコン単結晶層が形成された
シリコン単結晶基板とSiO基板とを熱圧着したが、
シリコン単結晶層が厚い場合にはシリコン単結晶のみを
SiO基板に熱圧着してもよい。また、上記実施例で
は、シリコン単結晶板を用いたが、これに限定されるも
のではない。
In the above example, the silicon single crystal substrate having the silicon single crystal layer formed thereon and the SiO 2 substrate were thermocompression bonded,
When the silicon single crystal layer is thick, only the silicon single crystal may be thermocompression bonded to the SiO 2 substrate. Further, although the silicon single crystal plate is used in the above-mentioned embodiment, the present invention is not limited to this.

〔発明の効果〕〔The invention's effect〕

以上詳述した如く本発明によれば、結晶性の完全な半導
体層を絶縁基板とは別個に用意した後、両者を一体形成
することによつて、半導体層の結晶欠陥の発生や電気的
特性の劣化を阻止し、素子の高速化、高密度が可能な半
導体基体を製造する方法を提供できるものである。
As described above in detail, according to the present invention, the crystalline semiconductor layer is prepared separately from the insulating substrate, and then the both are integrally formed. It is possible to provide a method of manufacturing a semiconductor substrate capable of preventing deterioration of the device, increasing the device speed, and increasing the density.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)〜(c)は本発明の一実施例に係る半導体基体の
製造方法を工程順に示す断面図、第2図(a)はシリコン
単結晶層とSiO基板との熱圧着前のラツピングした
断面を顕微鏡で撮影した状態を示す模式図、同図(b)は
シリコン単結晶層とSiO基板との熱圧着後のラツピ
ングした断面を顕微鏡で撮影した状態を示す模式図であ
る。 1……シリコン単結晶基板(半導体基板)、2……シリ
コン単結晶層(半導体層)、3……SiO基板(絶縁
性基板)、4……境界面。
1 (a) to 1 (c) are sectional views showing a method of manufacturing a semiconductor substrate according to an embodiment of the present invention in the order of steps, and FIG. 2 (a) is thermocompression bonding of a silicon single crystal layer and a SiO 2 substrate. The schematic diagram showing the state of the previous lapped cross section taken by a microscope, and FIG. 6B is the schematic diagram showing the state of the lapped cross section after thermocompression bonding of the silicon single crystal layer and the SiO 2 substrate taken with the microscope. is there. 1 ... Silicon single crystal substrate (semiconductor substrate), 2 ... Silicon single crystal layer (semiconductor layer), 3 ... SiO 2 substrate (insulating substrate), 4 ... Boundary surface.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭51−18475(JP,A) 特公 昭37−114(JP,B1) 特公 昭49−26455(JP,B1) 第44回応用物理学会予稿集 1983.9. 25 P.614(講演番号26a−D−9) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-51-18475 (JP, A) JP-B 37-114 (JP, B1) JP-B 49-26455 (JP, B1) 44th Applied Physics Academic Proceedings 1983. September 25 P. 614 (lecture number 26a-D-9)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】表面が十分平滑に形成されたSi半導体層
と表面が十分平滑に形成されたSiO層を前記平滑表
面で接合し、温度950℃以上で熱圧着により前記Si
半導体層表面と前記SiO層表面の接合した境界面を
消失せしめる工程を具備することを特徴とする半導体基
体の製造方法。
1. A Si semiconductor layer having a sufficiently smooth surface and a SiO 2 layer having a sufficiently smooth surface are joined on the smooth surface, and the Si is formed by thermocompression bonding at a temperature of 950 ° C. or higher.
A method for manufacturing a semiconductor substrate, comprising a step of eliminating a boundary surface where the surface of the semiconductor layer and the surface of the SiO 2 layer are joined.
JP58203808A 1983-10-31 1983-10-31 Method for manufacturing semiconductor substrate Expired - Lifetime JPH0616537B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58203808A JPH0616537B2 (en) 1983-10-31 1983-10-31 Method for manufacturing semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58203808A JPH0616537B2 (en) 1983-10-31 1983-10-31 Method for manufacturing semiconductor substrate

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP5005671A Division JPH0770694B2 (en) 1993-01-18 1993-01-18 Semiconductor substrate

Publications (2)

Publication Number Publication Date
JPS6095936A JPS6095936A (en) 1985-05-29
JPH0616537B2 true JPH0616537B2 (en) 1994-03-02

Family

ID=16480064

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58203808A Expired - Lifetime JPH0616537B2 (en) 1983-10-31 1983-10-31 Method for manufacturing semiconductor substrate

Country Status (1)

Country Link
JP (1) JPH0616537B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8501773A (en) * 1985-06-20 1987-01-16 Philips Nv METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES
JPH0770694B2 (en) * 1993-01-18 1995-07-31 株式会社東芝 Semiconductor substrate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3902979A (en) * 1974-06-24 1975-09-02 Westinghouse Electric Corp Insulator substrate with a thin mono-crystalline semiconductive layer and method of fabrication

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
第44回応用物理学会予稿集1983.9.25P.614(講演番号26a−D−9)

Also Published As

Publication number Publication date
JPS6095936A (en) 1985-05-29

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