JPH0616548B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device suitable for enhancing radiation resistance and high integration.

[Conventional technology]

A conventional SOI (Silicon on Insulator) type semiconductor device having the structure shown in FIG. 2 has been proposed.

That is, for example, on the p-type single crystal semiconductor substrate 1, p
A source having a single crystal semiconductor region 2 formed as a channel region having a n-type on the buried insulating layer 5 for element isolation, having an n-type, and having a higher impurity concentration than the single crystal semiconductor region 2. Single crystal semiconductor regions 3 and 4 serving as regions and drain regions are juxtaposed and connected to single crystal semiconductor region 2, and are formed on single crystal semiconductor substrate 1 with embedded insulator layer 5 interposed therebetween.

Further, the gate 6 is formed on the single crystal semiconductor region 2 with the gate insulating layer 7 interposed therebetween. Further, a source electrode 8, a drain electrode 9 and a gate electrode 10 are attached to the single crystal semiconductor regions 3 and 4 and a gate 6, respectively, and a substrate electrode 11 is attached to the single crystal semiconductor substrate 1. 5'is an insulating layer for element isolation.

The above is a configuration example of a semiconductor device conventionally proposed,
SOI n-channel metal-insulator-semiconductor (hereinafter MIS
Called) Transistor. In FIG. 2, if n-type and p-type, which indicate the conductivity type of a semiconductor, are exchanged, S
It goes without saying that it will be an OI type p-channel MIS transistor.

In the conventional SOI type MIS transistor having such a structure, the n-channel MIS transistor and the p-channel MIS transistor are made of a single crystal because they are completely electrically separated from other semiconductor elements by the insulating layers 5 and 5 '. The parasitic thyristor is not formed even if it is mixedly mounted on the semiconductor substrate 1, and there is an advantage that malfunction (latch-up) due to the parasitic thyristor effect does not occur even if radiation is performed. However, when the insulator layers 5 and 5 ′ such as silicon oxide (hereinafter referred to as SiO ₂ ) are irradiated with radiation, holes among the electrons and holes generated in the insulator layers are isolated. In the n-channel MIS transistor, the insulator layer is positively charged because it is trapped in the source layer.
There is a problem that the leak current between the drains increases. Hereinafter, this problem will be described in detail with reference to FIG.

3A is a cross-sectional view of the SOI n-channel MIS transistor, and FIG. 3B is a plan view thereof. Since the element isolation buried insulator 5 and the element isolation insulator layer 5'are positively charged by the irradiation of electrons, electrons are induced in the p-type channel region and the n-type inversion layer 12 is formed. Is shown.

Since a current flows through the n-type inversion layer 12 to the n-type source 3 and the drain 4, in the normally-off n-channel MIS transistor, the source
The leak current between the drains increases. For example, gate 6
Width / length = 100 μm / 5 μm, impurity concentration of p-type channel region˜1 × 10 ¹⁷ cm ⁻³ , thickness of isolation SiO ₂ layers 5 and 5 ′ ˜0.2 μm and 1 μm structural constant When the channel MOS transistor is irradiated with 1 × 10 ⁵ rad of ⁶⁰ Co, the leakage current between the source and the drain increases several thousand to several ten thousand times.

In the SOI p-channel MIS transistor, since the channel region is n-type, the inversion layer is not formed even when the isolation insulator layer is positively charged by the irradiation of radiation, but the storage layer is formed. Therefore, the p-channel MIS transistor does not increase the leak current as in the n-channel MIS transistor.

As is apparent from the above description, the conventional S shown in FIG.
In the OI type element, an inversion layer, that is, a channel is formed due to the irradiation of radiation, so that there is a problem that the normally off type is changed to the normally on type.

On the other hand, the conventional embodiment shown in FIG. 4 was developed aiming at high integration of an n-channel MIS transistor, and a polycrystalline semiconductor containing a high concentration of p-type impurities around the n-channel MIS transistor. A layer 13 is provided in contact with the single crystal semiconductor substrate 1 and a p-type impurity is diffused from the polycrystalline semiconductor layer 13 into the single crystal semiconductor substrate 1 at a high concentration to form a p-type channel stopper region 14. There are features. In this embodiment, even if the insulating layer 5'for element isolation is positively charged by irradiation with radiation, the insulating layer 5'for element isolation is formed.
Since electrons are induced in the single crystal semiconductor substrate 1 and the polycrystalline semiconductor layer 13 immediately below, no n-type inversion layer is formed in the p-type channel region 2.

However, p-channel MIS is used to reduce power consumption.
A CMOS is formed by mounting a transistor on the single crystal semiconductor substrate 1 together.
With the structure, since both the n-channel and p-channel MIS transistors have insulators and are not separated from the single crystal semiconductor substrate 1, there is a problem that a parasitic thyristor is formed and latch-up occurs due to radiation irradiation.

Further, in the n-channel MIS transistor shown in FIG. 4, since the element isolation insulator layer 7'is in direct contact with the channel region 2, even if the insulator layer 7'is positively charged by radiation irradiation, In order to prevent the formation of an n-type inversion layer in the region 2, the thickness of the insulating layer 7'is, for example, several hundred Å in order to suppress the number of electron-hole pairs generated in the insulating layer 7 '. However, the source potential of the p-channel MIS transistor is set to the single crystal semiconductor substrate 1.
Since it is always higher than the potential of the polycrystalline semiconductor layer 13 in contact with the parasitic semiconductor layer 13, the polycrystalline semiconductor layer 13 surrounding the p-channel MIS transistor serves as a gate and the element isolation insulator layer 7'of the transistor serves as a gate insulator. The gate of the MIS transistor is always negatively biased, and the threshold voltage of the parasitic MIS transistor is increased negatively to increase the p
In order to make the channel MIS transistor a normally-off type, it is necessary to increase the thickness of the element isolation insulator layer 7'of the p-channel MIS transistor to, for example, several thousand Å. That is, since the required thickness of the element isolation insulator layer 7'is significantly different between the n-channel MIS transistor and the p-channel MIS transistor, if the insulator is formed in the same step, the n-channel MIS transistor and the p-channel MIS transistor are formed. There is a problem that the MIS transistor and the MIS transistor cannot be mounted together.

[Problems to be solved by the invention]

In the conventional CMOS integrated circuit, as described in detail above, radiation causes an n-type inversion layer to occur in the p-type channel region of the n-channel field effect transistor, resulting in leakage between the n-type source and drain. There is a problem that the current increases or a parasitic thyristor is formed to cause latch-up.

The present invention solves such problems and provides a semiconductor device having excellent radiation resistance and low power consumption.

[Means and Actions for Solving Problems]

In order to solve the above problems, the first configuration of the present invention is an integrated circuit in which an n-channel field effect transistor and a p-channel field effect transistor are provided on a semiconductor substrate, and a side surface of the n-channel field effect transistor. A non-insulating layer in contact with the semiconductor substrate is provided via the insulating layer, and the non-insulating layer is not provided on the side surface of the p-channel field effect transistor at least in a range where the field effect is large. .

A second structure of the present invention is the integrated circuit having the above structure, further comprising an n-channel field effect transistor and a p-channel field effect transistor.
An insulating layer is provided on the bottom surface of each active region of the channel field effect transistor via a semi-insulating layer.

That is, the non-insulating layer and the semi-insulating layer have an electrolytic shielding effect, and electron induction due to holes trapped in the element isolation insulating layer by irradiation with radiation is It occurs in semiconductor substrates, and also in the semi-insulating layer. Therefore, the lines of electric force generated from the holes in the insulating layer for element isolation do not enter the p-type channel region, and the n-type inversion layer is not formed. Therefore, it is possible to prevent the phenomenon that the element isolation insulator layer is positively charged by the irradiation of radiation and the leak current increases between the source and the drain of the n-channel field effect transistor to deteriorate the characteristics.

Further, in the second configuration of the present invention, n channels,
Since the p-channel field effect transistor is separated by the insulating layer provided on the bottom surface, it is possible to prevent a parasitic thyristor from being formed due to irradiation of radiation and latch-up.

When a parasitic p-channel field effect transistor is formed by the non-insulating layer and the p-channel field effect transistor, the parasitic p-channel field effect transistor can be turned off by using the side surface of the p-channel field effect transistor. Since it is necessary to increase the distance from the non-insulator layer, p
The non-insulator layer is not provided on the side surface of the channel field effect transistor at least in the range where the field effect is large.

〔Example〕

FIGS. 1 (a) to 1 (c) are views showing the structure of a semiconductor device according to an embodiment of the present invention, which is a case where a CMOS inverter configuration is performed. 1A is a sectional view, FIG. 1B is a plan view of the CMOS inverter cut along the AA ′ plane shown in FIG. 1A, and FIG. 1C is a BB ′ plane shown in FIG. It is sectional drawing when a CMOS inverter is cut.

In the figure, 1 is a single crystal semiconductor substrate, 2 is a channel region, 3 is a source region, 4 is a drain-in region, 5 is a buried insulating layer for element isolation, 5'is an insulating layer for element isolation, 6 is a gate, Reference numeral 7 is a gate insulator layer, 7'is an element isolation insulator layer, 8 and 8'is a source electrode, 9 is a drain electrode, 10 is a gate electrode, 11 is a substrate electrode, and 15 is a semi-insulating layer for electric field shielding. A mixture layer of silicon and silicon oxide, 16 is a non-insulating layer for electric field shielding, for example, a polycrystalline silicon semiconductor layer. As shown in FIGS. 1B and 1C, the electric field shielding non-insulating layer 16 is provided only on the side surface of the channel region 2 of the n-channel MIS transistor and is in contact with the single crystal semiconductor substrate 1. .

When operating the CMOS inverter of FIG. 1, a positive voltage is applied to the source electrode 8'and the source electrode 8 is grounded. At this time, since the base electrode 11 is also grounded, the electric potential of the electric field shielding non-insulating layer 16 becomes the same as the electric potential of the source region 3 of the n-channel MIS transistor. Therefore, the non-insulator layer 16 for shielding the electric field is used as the gate, and the insulator layer 7'for element isolation is used.
The parasitic n-channel MIS transistor having the gate insulator as the gate insulator is always in the off state because the gate bias is always 0V. On the other hand, when a plurality of the CMOS inverters are mounted together, the parasitic p-channel MIS transistor is also formed by the non-insulator layer 16 for electric field shielding and the p-channel MIS transistor. Source 3 of parasitic p-channel MIS transistor
On the other hand, the electric field shielding non-insulating layer 16 is always biased negatively. Therefore, in order to turn off the parasitic p-channel MIS transistor, the side surface of the p-channel MIS transistor is separated from the non-insulating layer 16 and the parasitic It is necessary to sufficiently increase the threshold value of the p-channel MIS transistor in the negative direction.

When the CMOS inverter shown in FIG. 1 is irradiated with radiation,
The gate insulator layer 7 and the element isolation insulator layers 5, 5'and 7'are positively charged. This is because, of the electron-hole pairs generated in the insulating layer by radiation as described above, only holes are trapped in the insulating layer. Gate insulator layer 7
Is positively charged, the threshold voltage of the MIS transistor fluctuates in the negative direction, and the element isolation insulating layers 5, 5'and 7 '
Is positively charged, an n-type inversion layer is easily formed in the channel region of the n-channel MIS transistor, and as a result, a leak current is generated between the source and the drain even when the gate applied voltage of the parasitic MIS transistor is 0V. Occurs. However, the above problem does not occur in the n-channel MIS transistor having the structure shown in FIG. The SOI n-channel MIS transistor will be described in detail below.

Since the electric field shielding semi-insulating layer 15 exists between the element isolation embedded insulator layer 5 and the channel region 2, it is caused by holes trapped in the element isolation embedded insulator layer 5. The induced electrons are generated in the electric field shielding semi-insulating layer 15. Therefore, the lines of electric force emitted from the holes in the element isolation insulator layer 5 are terminated by the induced electrons in the electric field shielding semi-insulator layer 15,
It does not enter the channel region 2. Further, since the induction of electrons due to the holes trapped in the element isolation insulator layer 5'occurs in the electric field shielding non-insulator layer 16 and the single crystal semiconductor substrate 1, the element isolation insulator layer 5 ' The electric lines of force generated from the holes of the above do not enter the channel region 2.

As is clear from the above description, the phenomenon that the element isolation insulator layers 5 and 5 ′ are positively charged by the irradiation of radiation and the characteristics of the n-channel MIS transistor are deteriorated are as follows. It is suppressed by the non-insulating layer 16.

On the other hand, the gate insulator layer 7 and the element isolation insulator layer 7 '
Is in contact with the channel region 2, so that electrons are induced in the channel region 2 when the insulator layers 7 and 7'are positively charged by irradiation of radiation. However, the charge amount of the insulator layers 7 and 7 ', that is, the number of holes trapped in the insulator layer depends on the thickness of the insulator layer, and the thinner the insulator layer is, the more positive holes are captured. Fewer holes.

This is shown in FIG. 5 as an example. Figure 5 shows MO
Γ-ray from ⁶⁰ Co is 1.5 × 10 ⁶ rad using S capacitor
The dependence of the flat band voltage fluctuation upon irradiation on the gate oxide film thickness is shown. The gate oxidation conditions are steam oxidation at 850 ° C and dry oxygen oxidation at 900 ° C. Although the variation in the flat band voltage varies depending on the gate oxidation conditions, the variation in the flat band voltage becomes smaller as the gate oxide film thickness is made thinner. Since the variation of the flat band voltage corresponds to the number of holes trapped in the gate oxide film, the thinner the gate oxide film, the smaller the number of holes trapped in the gate oxide film. You can see from Figure 5.

Therefore, regarding the induction of electrons in the channel region 2 due to the positive charge of the insulating layers 7 and 7'in FIG. 1, the number of electrons can be reduced by decreasing the thickness of the insulating layers 7 and 7 '. Can be kept small. Therefore, by setting the structure constant so that the number of induced electrons is smaller than the number of holes, which are the majority carriers of the p-type channel region 2, the characteristic deterioration of the n-channel MIS transistor can be suppressed.

As is apparent from the above description, in the n-channel MIS transistor having the structure shown in FIG. 1, the gate insulating layer 7 and the element isolation insulating layers 5, 5'and 7'are positively charged by irradiation with radiation. However, there is no characteristic deterioration such as leakage between the source and drain.

Since the p-channel MIS transistor having the structure shown in FIG. 1 does not have the electric field shielding non-insulating layer 16, when the element isolating insulating layers 5'and 7'are irradiated with radiation and thus are charged directly. , Electrons are induced in the channel region 2. However, since the dielectric type of the channel region 2 is n-type, a storage layer is formed, and source-drain leakage due to the formation of the inversion layer in the n-channel MIS transistor does not occur. Further, the effect on the channel region 2 due to the positive charge of the element isolation buried insulator layer 5 is suppressed by the electric field shielding semi-insulator layer 15 as in the case of the n-channel MIS transistor.

As is clear from the above description, in the embodiment shown in FIG. 1, since both the n-channel MIS transistor and the p-channel MIS transistor are separated by the insulator, latch-up does not occur even when receiving radiation, Further, the effect of the separation insulator capturing holes and positively charging to form the n-type inversion layer in the p-type channel region is suppressed by the electric field shielding layer. The concept of providing the electric field shielding layer for enhancing the radiation resistance of the present invention is also effective for enhancing the radiation resistance of the pn junction field effect transistor (JFET) and the Schottky junction field effect transistor (MESFET). Needless to say.

Next, one embodiment of the method of manufacturing the device of the present invention is shown in FIG.
It shows in (h).

(A) p-type single crystal semiconductor substrate 1, for example, specific resistance 1000 Ωcm
Oxygen ions, for example, are implanted into the single crystal silicon substrate at a temperature of 150 KeV until the dose reaches 1.8 × 10 ¹⁸ cm ^-2 , and then at a predetermined temperature, for example, 1150 ° C.
Then, the element isolation buried insulating layer 5 and the electric field shielding semi-insulating layer 15 are simultaneously formed by thermal annealing for a predetermined time, for example, for 2 hours. Next, after a single crystal semiconductor layer having a predetermined thickness, for example, 4000 Å, for example, a single crystal silicon layer is epitaxially grown on the single crystal semiconductor existing on the electric field shielding semi-insulating layer 15, the single crystal semiconductor is formed. An n-type or p-type impurity is added to the layer by a method such as an ion implantation method to form an n-type or p-type channel region 2 having a desired impurity concentration.

(B) After covering the surface of the channel region 2 with a protective film such as a silicon oxide film, a non-oxidizing mask material 17 such as a nitride film (Si
₃ N ₄ ) is used to process and form the channel region 2 having anisotropic etching characteristics, for example, by the reactive ion etching method. At this time, the side surface of the channel region 2 is processed so as to be as vertical as possible with respect to the single crystal semiconductor substrate 1, and in the field portion other than the channel region 2, the semi-insulating layer 15 for electric field shielding and The element isolation embedded insulator layer 5 is also etched and processed until the single crystal semiconductor substrate 1 is exposed. After that, the insulator layer 7 ', for example, a silicon oxide film is formed by a method such as oxidation to a predetermined thickness, for example, a thickness of 1000Å.

(C) After removing the insulating layer 7'formed on the side surface and the field portion of the channel region 2 by etching, a thin insulating material such as a silicon oxide film having a thickness of 200 Å is used as an insulating layer 7'for element isolation. Is newly formed by a method such as oxidation. As a result, the surface of the newly formed insulating layer 7'for element isolation is separated from the end of the mask material 17 by a distance l (Fig. 6 (c)).
(Indicated in Figure 3) only inside. For example, in the above example, l = 340Å.

Next, only the insulator layer 7'formed in the field portion is etched by using anisotropic etching method such as reactive ion etching method. At this time, the surface of the element isolation insulator layer 7 ′ formed on the side surface of the channel region 2 is located inside by 1 from the end of the mask material 17, and therefore is not etched. This means that the element isolation insulator layer 7'existing on the side surface of the channel region 2 is not damaged during reactive ion etching, and traps holes generated by radiation irradiation. It is effective in reducing the That is, the element isolation insulator layer 7'existing on the side surface of the channel region 2 is not damaged, and only the element isolation insulator layer 7'in the field portion can be selectively etched (d) For example, A non-insulating layer 16 for shielding an electric field, for example, a polycrystalline silicon layer is deposited by the low pressure CVD method. At this time, since the single crystal semiconductor substrate 1 is exposed, the substrate 1 and the non-insulating layer 16 are in direct contact with each other. The film thickness of the non-insulator layer 16 is larger than l shown in FIG. 6 (c).

(E) Anisotropic etching method, for example, reactive ion etching method, is used to etch the non-insulating layer 16 for electric field shielding over the entire surface of the sample in the state of (d), and only the side surface of the channel region 2 is self-etched. After leaving the non-insulating layer 16 by the matching method, the mask material 17 is removed. Since the thickness of the non-insulator layer 16 for electric field shielding is larger than l shown in FIG. 6 (c), the non-insulator layer 16 is formed as the single crystal semiconductor substrate 1 even if the etching is excessively performed. The contact area is secured. That is, it is characterized in that the non-insulator layer 16 for electric field shielding which is in contact with the single crystal semiconductor substrate 1 is left only on the side surface of the channel region by the self-alignment method.

(F) to (h) In order to provide the non-insulator layer 16 for electric field shielding only on the side surface of the channel region 2 of the n-channel MIS transistor, as shown in the plan view of FIG.
18 For example, a resist is provided. A sectional view taken along the line AA 'is shown in (g). After that, the non-insulator layer 16 for shielding electric field other than that covered by the mask 18 is etched by using an isotropic etching method, for example, a plasma etching method, and the mask 18 is removed. (H) is after removing the mask 18,
It is sectional drawing cut | disconnected by the BB 'surface shown to (g). An electric field shielding non-insulating layer 16 is formed only on the side surface of the channel region 2 of the n-channel MIS transistor with an element isolation insulating layer 7 ′ interposed therebetween.

(I) The field portion other than the channel region 2 is filled with an element isolation insulator layer 5 ', for example, a SiO ₂ layer. This filling is performed by a known method, for example, a low pressure CVD method, to deposit a SiO ₂ layer above the height h (shown in FIG. 6 (i)) of the channel region 2 to flatten the deposition surface, and then to form a non-insulator for electric field shielding. This can be achieved by etching the SiO ₂ layer until the layer 16 is exposed.

Next, after forming the gate insulator layer 7, for example, a polycrystalline silicon layer 6 is formed as a gate. Next, using the gate 6 as a mask, an n-type impurity is added to the p-type channel region 2 and a p-type impurity is added to the n-type channel region 2 by a method such as an ion implantation method to form the source region 3 and The drain region 4 is formed.

(J) After making contact holes in the insulating layer using a mask material such as resist, electrodes 8, 8 ', 9, 10, 11 are formed to complete the CMOS inverter.

As described above, the characteristics of the above-described manufacturing method are that the insulating layer 7 ′ for element isolation that is not damaged by etching is formed on the side surface of the channel region 2 by utilizing the anisotropic etching method. The non-insulating layer 16 for electric field shielding which is in contact with the semiconductor substrate 1 is formed only on the side surface of the channel region of the n-channel MIS transistor.

〔The invention's effect〕

As described above, according to the semiconductor device of the present invention, it is possible to realize a CMOS configuration with less characteristic deterioration due to radiation irradiation and low power consumption. The effects of the present invention are summarized below.

(A) A non-insulating layer for electric field shielding, which is in contact with the semiconductor substrate, is provided on the side surface of the n-channel field effect transistor via the insulating layer, or the active regions of the n-channel field effect transistor and the p-channel field effect transistor are further provided. By providing the insulating layer on the bottom surface via the semi-insulating layer, the inversion layer is not formed in the p-type channel region even when the insulating layer for element isolation is irradiated with radiation and is positively charged,
It is possible to prevent a leak current between the source and the drain due to radiation irradiation.

(B) By separating the transistor from the single crystal semiconductor substrate with an insulating layer, even if a CMOS structure is adopted, no malfunction (latch-up) due to a parasitic thyristor occurs.

(C) Since the element isolation insulator layer can be formed on the side surface of the channel region by the self-alignment method without being damaged during processing, it is possible to suppress the charge amount of the insulator caused by radiation irradiation. it can.

(D) If, for example, silicon is used as the material of the single crystal semiconductor substrate, the buried insulator layer for element isolation and the semi-insulator for electric field shielding located thereabove only by ion implantation of oxygen into the semiconductor substrate and subsequent thermal annealing. The layers can be formed simultaneously.

[Brief description of drawings]

1 (a) is a sectional view of an embodiment of the device of the present invention, FIG. 1 (b) is a sectional view taken along the line AA 'of FIG. 1 (a), and FIG. 1 (c).
Is a sectional view taken along the line BB 'in FIG. 1 (a), FIG. 2, FIG. 3 (a), (b), and FIG. 4 are views showing a conventional semiconductor device, and FIG. 5 is a MOS capacitor. FIG. 6A is a diagram showing a specific example of the relationship between the fluctuation value of the flood band voltage and the gate oxide film thickness when γ-rays are irradiated, and FIGS. 6A to 6J show an example of the manufacturing process of the semiconductor device of the present invention. FIG. 1 ... Single crystal semiconductor substrate, 2 ... Channel region 3 ... Source region, 4 ... Drain region 5 ... Element isolation buried insulator layer 5 ', 7' ... Element isolation insulator layer 6 ... ... gate, 7 ... gate insulator layer 8,8 '... source electrode, 9 ... drain electrode 10 ... gate electrode, 11 ... substrate electrode 12 ... n type inversion layer 13 ... polycrystalline silicon semiconductor layer 14 …… Channel stopper region 15 …… Semi-insulating layer for electric field shielding 16 …… Non-insulating layer for electric field shielding 17, 18 …… Mask

Claims (2)

[Claims] 1. In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor provided on a semiconductor substrate, a non-insulating layer in contact with the semiconductor substrate is an insulating layer on a side surface of the n-channel field effect transistor. The semiconductor device is characterized in that the non-insulating layer is not provided on the side surface of the p-channel field effect transistor at least in a range where the field effect is large. 2. In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor provided on a semiconductor substrate, a non-insulating layer in contact with the semiconductor substrate is an insulating layer on a side surface of the n-channel field effect transistor. And the non-insulating layer is not provided on the side surface of the p-channel field effect transistor at least in a range where the field effect is large, and the n-channel field effect transistor and the p-channel field effect transistor are A semiconductor device, wherein an insulating layer is provided on the bottom surface of each active region via a semi-insulating layer.