JPH0616582B2 - Reset circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a reset circuit that detects a voltage drop such as a momentary power interruption and resets a logic circuit system.

[Conventional technology]

In a control system composed of various logic circuits including a microprocessor, when the power supply voltage drops below a certain value, the operation of the microprocessor is no longer guaranteed and so-called runaway occurs.

In order to prevent this, a reset circuit that detects a drop in the power supply voltage and resets the control system is often used.

FIG. 3 is a circuit diagram of a conventional example of this type of reset circuit.

The voltage comparator COMP ₁ has hysteresis, and a voltage obtained by dividing the power supply voltage Vcc applied to the power supply voltage terminal T ₁ by the resistors R ₁ and R ₂ is input to the inverting terminal to supply the power applied to the terminal T _1. The reference voltage V _REF that does not depend on the voltage Vcc is input from the terminal T ₃ to the non-inverting terminal.

Voltage comparison circuit COMP ₁ and voltage comparison circuit CO described later
The reason why MP ₂ has hysteresis is to prevent malfunction of the entire reset circuit due to noise voltage mixed in the non-inverting terminal or the inverting terminal when the reset circuit is mounted in the control system (device). Dead band width)
It is not large, and it is assumed here that both voltage comparators COMP ₁ and COMP ₂ have no hysteresis for simplification of description. The power supply voltage Vcc applied to the terminal T ₁ drops, and the voltage V _INN of the inverting terminal of the voltage comparator COMP ₁ = (Vcc ×
When R ₂ ) / (R ₁ + R ₂ ) becomes lower than the reference voltage V _REF , the output of the voltage comparator COMP ₁ becomes almost equal to the power supply voltage Vcc, and the N-channel MOS transistor M ₁ is turned on. Since the electric charge charged in the capacitor C ₁ by the constant current source I _SI is instantaneously discharged by turning on the transistor M ₁ , the inverting terminal of the voltage comparator COMP ₂ becomes 0 [V]. Voltage comparator non-inverting terminal of COMP ₂ are the reference voltage input by the discharging of the capacitor C ₁ since it is connected to the terminal T ₃ voltage comparator COMP ₂ inverting terminal the reference becomes lower than the voltage V _REF when the voltage comparator COMP ₂ The output becomes almost equal to the power supply voltage Vcc, the first N-channel MOS transistor M ₂ turns on, and the resistance R ₃ connected between the drain power supply terminals T _{1 of} the first N-channel MOS transistor M ₂ The reset output terminal T ₂ outputs almost 0 [V], that is, the “L” level. This output is the RESET output, which resets the control system logic circuit such as the microprocessor.

Next, the operation of the reset circuit of FIG. 3 will be described with reference to the graphs of FIGS.

4 and 5 show the power supply voltage Vcc applied to the terminal T ₁ .
After There increased in number to the specified voltage VN from 0 [V], there is a time T _I to be less guaranteed operating voltage V _TH of the microprocessor or the like control system LSI, lowering the 0 V return again to the specified voltage N _N Power supply voltage Vcc and reset output of terminal T ₂ when
The relationship between RESET, the power supply voltage Vcc, and the power supply V _T4 of the terminal T ₄ is shown.

When the power supply voltage Vcc fluctuates in this way, if the power supply voltage Vcc at the time t _{0 at which} the voltage comparison circuits COMP ₁ and COMP ₂ start to operate normally is V _REF , the voltage comparator COMP ₁
Since the voltage applied to the inverting terminal of the voltage comparator is always lower than the voltage applied to the terminal T ₃ , the output of the voltage comparator COMP ₁ is almost the power supply voltage Vcc, and the power supply voltage Vcc is the threshold of the N-channel MOS transistor M ₁ . If it is higher than the hold voltage _T , the N-channel MOS transistor M ₁ is turned on,
Since the electric charge of the capacitor C ₁ has been discharged, the voltage V _T4 at the terminal T ₄ is 0 [V] as shown in FIG. Power supply voltage Vcc
_{Exceeds the} guaranteed operating voltage V _TH at time t ₁ , the voltage comparator COMP
_Since the output of ₁ is inverted and the N-channel MOS transistor M ₁ is turned off, the constant current source I _SI starts charging the capacitor C ₁ . The output RESET of the terminal T ₂ before the voltage comparator COMP ₁ is inverted is 0 [V] as shown in FIG. 4 because the first N-channel MOS transistor M _{2 is} on. When the charging of the capacitor C ₁ is started and the voltage V _T4 of the terminal T ₄ exceeds the reference voltage V _REF at time t ₂ , the voltage comparator CO
Since the output of MP ₂ is inverted and the first N-channel MOS transistor M ₂ is turned off, the output RESET of the terminal T ₂ becomes almost Vcc and the reset is released.

Therefore, the time t _d from when the power supply voltage Vcc exceeds the guaranteed operation voltage V _TH to when the reset is released is t _d = C ₁
It is represented by × V _REF / I _SI .

Next, when the power supply voltage Vcc drops momentarily and becomes equal to or lower than the guaranteed operation voltage V _{TH at} time t ₃ , the output of the voltage comparator COMP ₁ becomes “H”, and when the N-channel MOS transistor M ₁ turns on, the capacitor C ₁ outputs. The electric charge is discharged and the potential V _T4 of the terminal T ₄ becomes 0 [V]. N-channel MOS transistor M
_Since the on-resistance of _{No. 1} is sufficiently low, the discharge time is much shorter than the charge time. When the power supply voltage V _cc becomes equal to or lower than the guaranteed operation voltage V _TH again at the time t ₄ after the momentary decrease, the same operation as at the first rising is performed, and the reset pulse RESE is applied from the terminal T _2.
T is output. In this case, the reset pulse width is T _I +
a t _d.

Finally, in the process of the power supply voltage Vcc decreasing to 0 [V], the reset pulse remains on (excluding t> T ₅ ).

Next, problems of this reset circuit will be described.

In FIGS. 4 and 5, at t <t ₀ or t> t ₅ , the operation of the voltage comparators COMP ₁ and COMP ₂ is generally unstable, and a vibration waveform may be output from the terminal T ₂ . Control systems often have RAM backed up by batteries, but if the power supply voltage drops and the reset signal is not input to the microprocessor reliably, a runaway occurs, and erroneous data is also fetched from the ROM due to the voltage drop. RA above
M may be rewritten. When such a phenomenon occurs, the entire control system instantly becomes a waste product.

[Problems to be solved by the invention]

The conventional reset circuit described above has a drawback that the reset pulse is not reliably output because the operation of the voltage comparison circuit is not guaranteed in the low power supply voltage region.

An object of the present invention is to solve this drawback, and a power supply voltage Vcc is a guaranteed operation voltage V _TH or less, such as a microprocessor.
It is an object of the present invention to provide a reset circuit that surely maintains a reset state up to a non-operation area of a control system logic circuit.

[Means for solving problems]

According to the present invention, one or more P-channel MOS transistors, a power supply voltage detection circuit in which one resistor is connected in series to the ground side thereof, and an inverter are connected to the conventional reset circuit described above. It is composed of a pair of P-channel MOS transistor and N-channel MOS transistor, and outputs from the reset signal terminal T ₂ and an inverter circuit that outputs an “H” level or “L” level signal according to the detected power supply voltage. It is configured by adding an additional circuit consisting of one N-channel MOS transistor that controls the reset signal level, ensuring a reset signal even in the low power supply voltage region where a reliable reset signal output cannot be guaranteed only by the conventional circuit. It is supposed to be output to.

That is, the reset circuit of the present invention includes one p-channel MOS transistor having one gate and drain connected, or n gate-drain connected and adjacent drain-source connected. , The source end of the P-channel MOS transistor and each P-channel
The back gate of the MOS transistor is connected to the power supply positive terminal, the drain end is connected to the ground via a resistor, and the (n + 1) th point is connected to the connection point between the drain end of the P-channel MOS transistor and the resistor. The gates of the P-channel MOS transistor and the second N-channel MOS transistor are connected, the source and back gate of the (n + 1) th P-channel MOS transistor are connected to the positive terminal of the power supply, and the second N-channel MOS transistor is connected. The source and back gate of which are respectively connected to ground, and the drains of the both transistors are connected to each other, the gate to the drain of the inverter circuit, the source and back gate to ground,
It is characterized in that the drain has third N-channel MOS transistors respectively connected to the connection points with the first N-channel MOS transistors.

〔Example〕

 Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the reset circuit of the present invention, and FIG. 2 is a graph showing the operation of the additional circuit in FIG.

In this embodiment, a circuit within a range surrounded by a dotted line is added to the conventional circuit shown in FIG. The conventional circuit is connected at two points of the power supply bus Bs, the connection point of the resistor R ₃ of the reset signal output circuit and the first N-channel MOS transistor M ₂ , and is connected in series between the power supply bus Bs and the ground. Connected first and second P-channel MOS transistors M ₃ and M
₄ and a resistance R ₄ and a power supply voltage detection circuit, and an inverter circuit composed of a third P-channel MOS transistor M ₅ and a second N-channel MOS transistor M _{6 which are} similarly connected in series between the power bus Bs and ground. And a third N-channel MOS transistor M ₇ connected to the reset signal output circuit.
When it is more configuration, the output of the T ₅ points of the power supply voltage detection circuit to each of the inverter circuits gates, the output of the inverter circuit are inputted to the gate of the third N- channel MOS transistor M _7.

Next, the operation of the additional circuit shown in FIG. 1 will be described with reference to FIG.

When the power supply voltage Vcc rises from 0 to t ₆
P-channel MOS transistor M ₃ is already on, but the second P-channel MOS transistor M ₄ is off, so that between the first and second P-channel MOS transistors M ₃ and M ₄ . The potential of the terminal T ₅ rises with the power supply voltage Vcc, but the second P-channel MOS transistor M ₄
The potential of the terminal T ₆ between the resistor R ₄ and the resistor R ₄ is the ground potential.

At this time, the third N-channel MOS transistor M ₇
Is also in the off state, the reset signal output terminal T ₂ rises slightly together with the power supply voltage Vcc. However, since the logic circuit element such as the microprocessor does not operate at all in such a low voltage region, the above-mentioned rewriting of the RAM does not occur, so there is no problem.

At time t ₆ , the second P-channel MOS transistor M ₄
Is also turned on, and the first and second P-channel MOS transistors M ₃ and M ₄ have high impedance,
A considerable potential difference occurs between the power source and the terminal T _{5 and} between the terminal T ₅ and the terminal T ₆ even with a small current, but a slight potential difference also occurs between the terminal T ₆ and the ground, and this “L” is applied to the gate of the inverter circuit. The level signal is input. Thus the third P- channel MOS transistor M ₅ is turned on for the inverter circuit, the second N- channel MOS transistor M ₆ takes the OFF state, when the power supply voltage Vcc "H" level signal as the third N- It is input to the gate of the channel MOS transistor M ₇ and is connected to the third and third N-channel MOS transistors M ₇
Is turned on, the potential of the terminal T ₂ is grounded, and the reset output RESET is output.

After that, at time t ₇ , the inverter circuit inverts and outputs the “L” level signal due to the rise in the potential of the terminal T ₆ ,
The N-channel MOS transistor M ₇ is turned off, the potential of the reset signal output terminal T ₂ approaches the power supply voltage Vcc, and the reset RESET releases the reset of the logic circuit.

When the power supply voltage Vcc falls, the operation is performed in the reverse order of the rise, and the reset output RESET is output.
Finally, even in the low voltage region near 0, there is no problem for the same reason as at the time of rising.

The first N-channel MOS transistor M ₂ and the third N-channel MOS transistor M ₇ are connected to each other for reset operation.
Since the OR is taken, it becomes possible for both parties to cooperate to reliably output the reset signal even in the non-operation area beyond the reach of the conventional circuit.

In the embodiment, the P-channel MO of the power supply voltage detection circuit of the additional circuit is used.
Two S transistors were connected in series, but the specified voltage value V
_The required number may be used depending on _N.

〔The invention's effect〕

As described above, the present invention provides a power supply voltage detection circuit in which one or more P-channel MOS transistors and resistors are newly connected in series to the conventional reset circuit, a set of P-channel MOS transistors and N-channel. By adding an inverter circuit consisting of MOS transistors and a circuit consisting of one N-channel MOS transistor that controls the output of the reset signal, in the area of low power supply voltage which was uncertain in the conventional reset circuit. The reset circuit of the present invention can be surely applied, and by using the reset circuit of the present invention, the control system including the microprocessor, the ROM, and the RAM backed up by the battery is surely protected from the fluctuation of the power supply voltage. It can and has a great effect.

Moreover, this reset circuit uses CMOS including a voltage comparator, and it is also advantageous that it can be easily made into a monolithic IC.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a reset circuit according to the present invention, FIG. 2 is a graph showing operating characteristics of an additional circuit portion in the embodiment of FIG. 1, and FIG. 3 is a conventional reset. FIG. 4 is a circuit configuration diagram showing the circuit, and FIGS. 4 and 5 are graphs showing operating characteristics of the conventional reset circuit shown in FIG. Vcc ...... supply voltage, _{V N} ...... specified voltage, V _TH ...... guaranteed operating voltage, V _REF ...... reference voltage, V _T4 ...... terminal voltage of the capacitor _{C 1, R 1, R 2} , R 3, R 4 ...... Resistance, COMP ₁ ...... First voltage comparison circuit, COMP ₂ ...... Second voltage comparison circuit, C ₁ ...... Capacitor, L _SI ...... Constant current source, M ₁ ...... N-channel MOS transistor, M ₂ …… First N-channel MOS transistor, M ₆ …… Second N-channel MOS transistor, M ₇ …… Third N-channel MOS transistor, M ₃ …… First P-channel MOS transistor transistors, _{M 4} ...... second P- channel MOS transistor, _{M 5} ...... third P- channel MOS _{transistor, T 1, T 2, T} 3, T 4, T 5, T 6 ...... terminal, RESET ...... Reset output, t _d …… Although the capacitor is charged to the reference voltage V _REF Required time, T _I ... Time for the power supply voltage Vcc to fall below the guaranteed operating voltage VTH.

Claims (1)

[Claims] 1. A first N-channel MOS transistor whose drain is connected to a power supply terminal through a first resistor and whose source is grounded.
A transistor and a comparator for comparing a power supply voltage with a guaranteed operating voltage, the first N-channel MO from the comparator when the power source voltage drops below the guaranteed operating voltage.
A signal is output to the gate of the S transistor to output the first N
In a reset circuit for making a channel MOS transistor conductive and outputting a reset signal to a logic circuit from a connection point of the first resistor and the first N-channel MOS transistor, a gate and a drain are connected and a back gate is the power supply. A series circuit of one or a plurality of P-channel MOS transistors connected to a terminal, the sources and drains of adjacent transistors are connected, and the source of the P-channel MOS transistor located at one end of the series circuit is the power supply terminal. The other end of the P-channel MOS transistor has a series circuit in which the drain is grounded via a second resistor,
A power supply voltage detection circuit for detecting the power supply voltage in a low voltage region, a first gate connected to a connection point between the series circuit and the second resistor, and a source and a back gate connected to the power supply terminal. An inverter having a P-channel MOS transistor, a second N-channel MOS transistor having a gate and a drain connected to the gate and the drain of the first P-channel MOS transistor, and a source grounded; and a gate having a drain of the inverter A third N-channel MOS transistor having a source and a back gate grounded and a drain connected to a connection point between the first N-channel MOS transistor and the first resistor. Characteristic reset circuit.