JPH0618193B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0618193B2 JPH0618193B2 JP17218687A JP17218687A JPH0618193B2 JP H0618193 B2 JPH0618193 B2 JP H0618193B2 JP 17218687 A JP17218687 A JP 17218687A JP 17218687 A JP17218687 A JP 17218687A JP H0618193 B2 JPH0618193 B2 JP H0618193B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- semiconductor device
- film
- antireflection
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 title description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 210000002381 plasma Anatomy 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に係り、特に金属配線の
形成方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming metal wiring.
従来、金属配線のパターン形成時、金属表面特に段部で
の光の反射によるパターン形状の異常を防ぐため、数10
0Åのシリコン被膜を金属表面に被着して露光し、パタ
ーン形成後、このシリコン被膜をプラズマエッチング等
で除去していた。Conventionally, when forming a pattern of metal wiring, in order to prevent the pattern shape from being abnormal due to the reflection of light on the metal surface, especially the stepped portion,
A 0 Å silicon film was deposited on the metal surface and exposed to light, and after the pattern was formed, the silicon film was removed by plasma etching or the like.
前述した従来の反射防止シリコンを用いた金属配線形成
法では、配線形成後、反射防止シリコンをＣＦ４プラズ
マ等を用いて除去する際、下地基板表面の絶縁物層例え
ばシリコン酸化膜を同時にエッチングして、配線の段差
を増大させたり、アロイ・スパイク防止用バリアメタル
例えばＴｉＷを同時にエッチングしたりする欠点があ
る。In the above-described conventional metal wiring forming method using antireflection silicon, when the antireflection silicon is removed using CF 4 plasma or the like after the wiring is formed, the insulating layer such as the silicon oxide film on the surface of the base substrate is simultaneously etched. As a result, there are drawbacks such that the step difference of the wiring is increased and the barrier metal for preventing alloy spikes such as TiW is simultaneously etched.
また、反射防止用シリコン上にレジスト残渣等の汚れが
あった場合や、反射防止用シリコンの表面の一部が酸化
された場合、エッチングムラやシリコン残り等の異常が
発生する欠点もある。Further, there is a defect that when the antireflection silicon is contaminated with resist residues or the like, or when a part of the surface of the antireflection silicon is oxidized, abnormalities such as etching unevenness and silicon residue occur.
本発明の目的は、前記欠点が解決され、エッチングして
はならないところがエッチングされる心配がなく、エッ
チングムラや、シリコン残り等の事故が発生しないよう
にした半導体装置の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a semiconductor device in which the above-mentioned drawbacks are solved, there is no fear of etching places that should not be etched, and etching irregularities and accidents such as silicon residue do not occur. is there.
本発明の半導体装置の製造方法の構成は、半導体基板の
一主表面上に金属配線を形成する工程において、除去せ
ずに、これを酸化シリコンに変化せしめる処理工程を有
していることを特徴とする。The structure of the method for manufacturing a semiconductor device of the present invention is characterized in that, in the step of forming the metal wiring on the one main surface of the semiconductor substrate, it has a treatment step of converting it into silicon oxide without removing it. And
次に本発明について図面を参照して詳細に説明する。 Next, the present invention will be described in detail with reference to the drawings.
第１図(A)乃至第１図(C)は本発明の一実施例の半導体装
置の製造方法を工程順に示す断面図である。まず第１図
(A)において、シリコン基板１上にシリコン酸化膜２を
形成し、アルミニウム膜３を順に被着した後、反射防止
用シリコン膜４を500Åの厚さで被着し、フォトレジス
ト５でパターニングする。次に、反射防止用シリコン膜
４、及びアルミニウム膜３を選択エッチングし、フォト
レジスト５を除去する（第１図(B)）。この後、例え
ば、バレル型プラズマ灰化装置を用いて、８００ＷのＯ
２プラズマ中で、２時間処理を行なうと、反射防止用シ
リコン膜４は、シリコン酸化膜６に変化する（第１図
(C)）。この時、アルミニウム膜３の側面にも、数１０
Åのアルミナ膜が形成されるが、特に問題は無く、アル
ミニウム膜３を保護する後割を持つ。また、下地シリコ
ン基板１上の酸化膜２は、エッチングされること無く、
安定である。この後、層間絶縁膜、又は表面保護膜とし
て、ＣＶＤ二酸化シリコン（SiO2）等を成長しても、シ
リコン酸化膜６は、層間絶縁膜又は表面保護膜の一部と
しての役割を持つ。1 (A) to 1 (C) are sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. First, Fig. 1
In (A), a silicon oxide film 2 is formed on a silicon substrate 1, an aluminum film 3 is sequentially deposited, and then an antireflection silicon film 4 is deposited to a thickness of 500Å and patterned with a photoresist 5. . Next, the antireflection silicon film 4 and the aluminum film 3 are selectively etched to remove the photoresist 5 (FIG. 1 (B)). After this, for example, using a barrel type plasma ashing device, 800 W of O
When the treatment is performed in 2 plasmas for 2 hours, the antireflection silicon film 4 changes into a silicon oxide film 6 (see FIG. 1).
(C)). At this time, several 10
Although the alumina film of Å is formed, there is no particular problem and it has a rear part to protect the aluminum film 3. Further, the oxide film 2 on the underlying silicon substrate 1 is not etched,
It is stable. After that, even if CVD silicon dioxide (SiO 2 ) or the like is grown as an interlayer insulating film or a surface protective film, the silicon oxide film 6 serves as a part of the interlayer insulating film or the surface protective film.
次に本発明の他の実施例の半導体装置の製造方法を説明
する。本実施例は、図面が前記一実施例の場合と同様で
ある。前記一実施例では、反射防止シリコン膜４を、Ｏ
２プラズマで２時間処理したが、本実施例は酸素（O2）
の代りに水蒸気（H2O）を含んだＯ２ガスを用いること
により、シリコンの酸化速度が速くなり、およそ４分の
１の時間の３０分程度で、反射防止シリコン膜４をシリ
コン酸化膜６に変化せしめることが可能となる。Next, a method of manufacturing a semiconductor device according to another embodiment of the present invention will be described. The present embodiment is the same as the case of the above-described one embodiment in the drawings. In the embodiment, the antireflection silicon film 4 is
It was treated with 2 plasmas for 2 hours. In this example, oxygen (O 2 ) was used.
By using an O 2 gas containing water vapor (H 2 O) instead of the above, the oxidation rate of silicon is increased, and the antireflection silicon film 4 is formed into a silicon oxide film in about 30 minutes, which is about a quarter of the time. It becomes possible to change to 6.
以上説明したように、本発明は、反射防止用シリコンを
除去せずに、シリコン酸化膜に変化せしめることによ
り、反射防止用シリコンを除去する際の前述した問題点
を排除し、製造プロセスを安定化できる効果がある。As described above, the present invention eliminates the above-mentioned problems in removing antireflection silicon and stabilizes the manufacturing process by changing the silicon oxide film without removing antireflection silicon. There is an effect that can be converted.
第１図(A)乃至第１図(C)は本発明の一実施例の半導体装
置の製造方法を工程順に示す断面図である。 １……シリコン基板、２，６……シリコン酸化膜、３…
…アルミニウム膜、４……反射防止用シリコン膜、５…
…フォトレジスト。1 (A) to 1 (C) are sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. 1 ... Silicon substrate, 2, 6 ... Silicon oxide film, 3 ...
… Aluminum film, 4 …… Antireflection silicon film, 5…
… Photoresist.
Claims (1)
防止用シリコン膜が設けられた半導体装置の製造方法に
おいて、前記金属配線上に被着した反射防止用シリコン
膜を除去せずに、これを酸化シリコンに変化せしめる処
理工程を有することを特徴とする半導体装置の製造方
法。1. A method of manufacturing a semiconductor device in which an antireflection silicon film is provided on a metal wiring on a main surface of a semiconductor substrate, without removing the antireflection silicon film deposited on the metal wiring. And a method of manufacturing a semiconductor device, which comprises a processing step of converting it into silicon oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17218687A JPH0618193B2 (en) | 1987-07-10 | 1987-07-10 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17218687A JPH0618193B2 (en) | 1987-07-10 | 1987-07-10 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6415951A JPS6415951A (en) | 1989-01-19 |
| JPH0618193B2 true JPH0618193B2 (en) | 1994-03-09 |
Family
ID=15937170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17218687A Expired - Lifetime JPH0618193B2 (en) | 1987-07-10 | 1987-07-10 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0618193B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0547227A4 (en) * | 1991-07-05 | 1994-08-10 | Kobe Steel Ltd | Optical surface inspection device for mill roll |
| DE4231312C2 (en) * | 1992-09-18 | 1996-10-02 | Siemens Ag | Anti-reflective layer and method for the lithographic structuring of a layer |
-
1987
- 1987-07-10 JP JP17218687A patent/JPH0618193B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6415951A (en) | 1989-01-19 |
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