JPH061819B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell of a semiconductor memory device, particularly a bipolar memory device, which is stable in operation even with respect to a soft error due to α particles and has a high-speed access. A memory cell suitable for obtaining time.

[Background of the Invention]

For the bipolar type memory device, for example, Japanese Patent Publication No. 53
No. 7105. However, the structure of the memory cell in which the load impedance changes depending on the operating state is not mentioned here.

Bipolar memory device, especially Random Access Memory
A memory cell (hereinafter referred to as a RAM) (hereinafter simply referred to as a cell) is a first multi-emitter transistor.
The flip-flop circuit shown in the figure is generally used. The bases and collectors of the multi-emitter transistors Q ₁ and Q ₂ are cross-connected to each other to form a flip-flop. The stored information is held in this cell by the holding current (Ist) flowing through the holding current supply line A. That is, when the transistor Q ₁ is conducting, the holding current (Ist)
Flows from the emitter E ₂₁ . And the transistor Q ₁
Collector current flows through the load Z _H1 connected between the collector of the transistor Q ₁ and the word line W ₁ , causing a potential drop.

On the other hand, the base current of Q ₁ flows through the load ZH2 connected to the collector of the transistor Q ₂ and causes a potential drop. Generally, the larger the difference in potential drop between the loads Z _H1 and Z _H2 , the more stable the operation of the cell. That is, by maintaining the base potential of the transistor Q ₂ lower than the base potential of the transistor Q _1, the transistor Q ₂ nonconductive, keep the conductive state of the transistor Q ₁ stably. As described above, it is necessary to constantly supply the holding current to the cell, and the larger the holding current, the more the power consumption in the cell increases. Therefore, in the case of high integration, the loads Z _H1 and Z _H2 are increased and the holding current is decreased to prevent an increase in power consumption.

Next, the operation of selecting a cell and reading the stored information, that is, the operation of the selected state of the cell is as follows.

A reference potential is applied to the bases C ₁ and C ₂ of the read transistors Q ₃ and Q ₄ . Then, this reference voltage is compared with the internal potential of the cell. When the transistor Q ₁ is conductive, the collector potential of the transistor Q ₂ , that is, the base potential of the transistor Q ₁ (hereinafter referred to as V _C1 ) becomes higher than the reference potential. Therefore, the read current flowing through the bit line B ₁ flows from the transistor Q ₁ and the collector current thereof causes a potential drop in the load resistance R _L1 . Therefore, the collector potential of the transistor Q ₁ , that is, the base potential of the transistor Q ₂ (hereinafter referred to as V _C0 ) becomes lower than the reference potential, and the read current of the bit line B ₂ flows from the read transistor Q ₄ . In this way, the stored information is read by detecting which bit line the read current flows from the read transistor. In general, the larger the read current, the faster the read speed and the easier the access time. Therefore, a cell suitable for a RAM with high integration, low power consumption, and high access time is a cell that reliably holds stored information even if the holding current is small and that can perform a read operation with a large read current. For this,
The load resistance needs a load whose impedance can be switched between the holding state and the selected state. In Fig. 1, the effective load in the holding state is R _H1 , and the selected state (read and write states). Sometimes the effective load is shown as R _L1 . In general, the load R _H1 uses a resistance of several tens KΩ to several hundreds KΩ, and the load R _L1 uses a non-linear element such as a diode.

FIG. 2 shows a cell array in which cells are arranged in a matrix. The selection of the cell CEL0 in the cell array is performed as follows. Select only the word selection drive circuit WD0,
The word line W ₀₀ to which the cell CEL0 is connected is driven from a low potential to a high potential.

Further, the digit line drive circuit YD1 is selected, and the read operation is performed so that the read current flows from the cell CEL0. In this way, when the cell CEL0 is in the selected state, the other cells take the following states, respectively. The cell CEL1 is in a state where only the word line is in the selected state (hereinafter referred to as XS state), the cell CEL2 is in the state in which only the digit line is in the selected state (hereinafter referred to as YS state), and the cell CEL3.
Are both in the non-selected state, that is, the held state.

Then, when the word line drive circuit WD1 is selected to select the cell CEL2 and the word line W _{10 is set} to a high potential,
The state of the cell CEL0 shifts from the selected state to the YS state. Thereafter, when the digit line drive circuit YD0 is selected to bring the cell CEL3 into the selected state, the state of the cell CEL2 shifts from the selected state to the XS state. For this purpose, the state of the cell shifts among various states, but it is necessary to stably hold the stored information during this period. Further, in order to speed up the fall time of the word lines W ₀₀ and W ₀₁ , a discharge current source I _CH0 is provided, and this current is sent by switching only to the word line selected by the diodes D ₀ and D ₁ . . Therefore, the discharge current I _CH0 flows in addition to the holding current I _ST1 or I _ST2 from the cell whose word line is selected.

Since the cells connected to the same word line share the holding current and the discharge current in this way, the cell collector potential V
_When there is a difference in _C1 , current drift occurs, and it becomes difficult for current to flow from cells with a low collector potential.

FIG. 3 shows the current dependence of the collector potentials V _C1 and V _C0 of the transistors forming the cell. This drawing shows the potential of the word line as a reference, and when the cell is in the holding state, for example, when the holding current per cell is 5 μA, V _C0 becomes -0.3V. That is, the operating voltage of the flip-flop (V _C1 −
V _C0 ) becomes 300 mV. Next, in the cell in the XS state, the discharge current I _CH0 is added to each cell in addition to the holding current, so that the current flowing from the cell is about 100 μA.
At this time, the collector voltages V _C1 and V _C0 are −0.12 V and −0.
46V, the operating voltage of the flip-flop is 340mV
Becomes On the other hand, the read current is 2m from the selected cell.
Since A flows, the collector voltages V _C1 and V _C0 are -0.39V.
And -0.95V, and the read is performed by setting the reference potential in the middle. In this figure, the load is Z
It is assumed that _H1 is 100 KΩ, Z _L1 is a series connection of a Schottky barrier diode (SBD) and a resistance of 250 Ω. When the load Z _L1 is only SBD, the collector potential V _C0 is as shown by the broken line, so the read current is 200 mA.
With the above, the operating voltage of the flip-flop is 200 mV
Even if a reference potential is set in the middle, the read current flows from both the cell and the read transistor, and stable read operation cannot be performed. Further, if an attempt is made to increase the read current by using a pn junction diode, the base and collector junctions of the transistor forming the flip-flop will be forward biased and the transistor will be saturated. Therefore, the read current cannot be increased. On the other hand, when the Schottky barrier diode is used, the forward voltage is about 0.4 V, saturation of the base and collector junction does not occur, and a large read current can flow.

In order to realize a high-speed and high-integrated RAM with low power consumption by using the cell having the above-described characteristics, the holding current is reduced and the read current is increased, that is, the resistance values of the loads R _H1 and R _H2 are increased. increased, by increasing the resistance value of the load R _L1 and R _L2, it is necessary to reduce the equivalent resistance of the load R _L1 and R _L2. That is, it is necessary to largely switch the load impedance between the selected state and the held state. When the impedance switching is increased in this way, there is a problem that the operation margin of the cell is reduced at the time of the cell state transition described above.

FIG. 4 shows the operational margin when the cell shifts from the selected state to the YS state. At time P ₀ point, the word line potential indicates the collector potential of the cell when it falls from the selected high potential to the non-selected low potential. The collector potential of the cell that shifts from the XS state to the holding state is V _C1 (XS-N
S).

It is indicated by V _C0 (XS-NS), and the collector potentials of the cells transitioning from the selected state to the YS state are indicated by V _C1 (S-YS) and V _C0 (S-YS). At this time, the flip-flop operating voltage (V
The potential difference between _C1 and V _C0 ) becomes narrower than other cells, that is, the operating margin is reduced.

FIG. 5 shows the collector potential V _C1 (XS) of the cell in the XS state when the selected state of the digit line is switched at time P ₁ .
V _C0 (XS) and collector potentials V _C1 (S-XS) and V _C0 (S-XS) of the cells that shift from the selected state to the XS state are shown. At this time as well, the operating margin of the latter cell is reduced.

This is because the collector potential of the selected cell is
This is because immediately after the read current stops flowing from the cell, the potential does not become the same as the collector potential of the cells connected to the same word line. For example, the read current flows before time P _{1 in} FIG. 5, but even after the read current stops flowing from the cell at time P ₁ , the collector potential V _C1 (S-XS) of this cell is It does not recover to the same potential as the collector potential V _C1 (XS) of the cells on the same word line, and remains at a low potential. Therefore, the holding current and the discharging current flow from the cell having the high collector potential (the holding current is unbalanced). Therefore, the holding current stops flowing from the cell that shifts from the selected state to the XS state, and approaches the collector potential V _C0 (S-XS). As a result, the operating voltage of the flip-flop of the cell becomes narrow, and the operating margin of the resulting cell decreases.

This phenomenon becomes more remarkable as the amount of change in the impedance of the load resistance that switches between the selected state and the held state increases.

That is, the larger the ratio of the read current to the holding current per cell, the more remarkable.

Further, when a load is formed by a series load of a Schottky barrier diode (SBD) of resistors R _L1 and R _L2 and a resistor, SB
The larger the capacity C _{SBD of} D becomes, the more remarkable it becomes. The value of C _SBD is also related to the operating margin of the cell at the rise of the word potential and the soft error rate due to α particles and the like. Fig. 6 shows C _SBD
And the cell operation margin. The operating margin of the cell at the rise of the word line potential, that is, the flip-flop operating voltage increases as C _SBD increases as shown by the characteristic curve CH1, and the cell becomes stable.

On the other hand, the decrease in the operating margin due to the deviation of the holding current in the above two cases becomes more remarkable as C _SBD increases, as indicated by the characteristic curve CH2.

Furthermore, in order to prevent soft error due to α particles, C
_SBD needs to be increased.

(See IEICE Transactions Sho 55-76 [C9]) For this reason, the characteristic CH2 is not desirable, which is a problem in realizing high speed and highly integrated RAM.

[Object of the Invention]

An object of the present invention is to provide a bipolar RA having a large change in impedance of a load resistance, that is, a large read current and a small holding current, a low power consumption, and a high access time.
For M, its operation is to provide a stable memory cell.

[Outline of Invention]

It is necessary that C _SBD is large in order to _prevent soft errors caused by α particles. Therefore, even if C _SBD is large, it is necessary to alleviate the decrease in the operating margin of the cell due to the above-mentioned drift of the holding current. This drift is caused by the difference in collector potential V _C1 between cells connected to the same word line, as described in FIG. As a method to reduce this difference,
One is a method of reducing the difference in the time constant of V _C1 at the time of cell state transition. Speaking of FIG. 5, time P ₁
The collector potential V _C1 (S-XS) at the same time may be made faster and the same as the collector potential V _C1 (XS) of the cells connected to the same word line. That is, the time constant of the collector of the cell transistor is reduced, and the load R _H1
And R _H2 should be reduced or C _SBD should be reduced. Reducing the loads R _H1 and R _H2 leads to an increase in holding current, which is a problem for high integration. Further reduction of C _SBD is not preferable in terms of soft error countermeasures due to α particles.

Another method is a collector potential V _C1 of the cell in the selected state (S), the collector potential V _C1 of the cell in the XS state
This is a method of reducing the difference (ΔV _C1 ) from (XS). This is Δ before time P _{0 in} FIG. 4 and time P _{1 in} FIG.
By reducing V _C1 , the difference ΔV _{C1 in} collector potential after the state transition is reduced. Speaking difference delta _C1 of the collector potential in FIG. 3, a method for reducing the collector potential V _C1 (XS) and the difference [Delta] V _C1 of the collector potential V _C1 of the selected state (S) of the XS state. For this purpose, the collector potential V _C1 (XS) is lowered to bring it closer to the collector potential V _C1 (S), or conversely, the collector potential V _C1 (S) is raised to bring it closer to the collector potential V _C1 (XS). It is possible to reduce Δ _C1 .

Set the current amplification factor of the transistor of the cell emitter E ₁₁ to H
_FE-R, and that of the transistor of the emitter E ₂₁ is H _FE-H
Where I _{XS is} the current flowing from the cell in the XS state and I _R is the read current, the collector voltage V of the cell in the XS state is
_C1 (XS) and the collector potential VV _C1 (S) in the selected state are respectively given by the following equations.

Here, K ₁ = R _L1 · I _R and K ₂ = R _HL · I _X2 .

From Expression 4), in order to reduce the collector potential difference ΔV _C1 , it is sufficient to increase H _FE-R and decrease H _FE-H .

The characteristic curve CH3 is shown in FIG. 6 as a result of obtaining the C _SBD dependency of the operating voltage of the flip-flop which indicates the operating margin of the cell by this method. By making a difference between H _FE and the collector potential V _C1 (S) of the selected cell,
Difference in collector potential V _C1 (XS) of cells in XS state ΔV _C1
Since smaller, C _SBD large area, that the operating voltage is sufficiently large at the time of rise of the word line potential shown in characteristic curve CH1, and a large area of the required C _SBD from the soft errors by α particles or the like, It is possible to prevent the operating voltage from decreasing due to the uneven distribution of the holding current.

Example of Invention

An embodiment of the present invention will be described below with reference to FIGS. 7 and 8.

FIG. 7 is a circuit diagram of a cell and shows an example in which the loads R _H1 and R _H2 are constituted by a resistor R _H , and the loads R _L1 and R _L2 are constituted by an SBD and a resistor R _L. The collectors C and bases B of the transistors Q ₁₁ and Q ₂₁ are common, the emitter 11 is connected to the digit line B 1, and the emitter 21 is connected to the holding current supply line A.

FIG. 9 shows a sectional view of the cell in FIG. P ^{-on the} semiconductor substrate 1, N
^{A +} collector region 4 is formed and an epitaxial layer 5 is formed. The P-type base region 6 is formed in this region by using the ion implantation technique, and only the region where the transistor 21 is formed is further ion-implanted to form the P-type base region 7. N ⁺ emitter regions 8 and 9 are formed in the base regions 6 and 7 by ion implantation or diffusion. Since the emitter is formed under the same conditions, the base width of the transistor 21 formed in the P-type region 7 that has been twice ion-implanted is thicker than the base width of the transistor 11, so that H _FE
Becomes smaller. Removal of the collector to the outside is done using the N ⁺ collector pull-up region 10. Further, the resistance R _H is formed in the P-type resistance region, and the resistance R _L is formed in the N ⁺ collector region 4. Further, the SBD is formed in the epitaxial region 11. V-groove isolation region 2 is used for isolation between elements.
And 3

The above is the H _FE of the transistor Q _{21 and} the H _FE of the transistor Q ₁₁ .
_The manufacturing method of forming the base region of the transistor Q ₂₁ by ion implantation twice in order to make it smaller than _FE has been described. In addition to this, as a manufacturing method for making a difference in H _FE , a method of completely independently forming the P-type base region 6 of the transistor Q _{11 and} the P-type base region 7 of the transistor Q ₂₁ under different conditions by ion implantation or diffusion, further formed with N ⁺ emitter region 8 and the transistor Q ₂₁ of the N ⁺ emitter region 9 the different conditions of the ion implantation or diffusion independently of the transistor Q _11, the transistor Q ₁₁ and the transistor Q
It is possible to make a difference in _HFE of ₂₁ .

Further, although the H _FE is made different by implanting the ions twice, the conductivity is different between the P-type region 6 and the P-type region 7, so that P forms a resistor used for peripheral circuits other than the cell. It can be used as a mold resistance region. Since the P-type regions having different conductivity can be used for the formation of the resistance as described above, it is possible to most appropriately select the dimensional ratio (the ratio of the width to the length) due to the floating capacitance and the processing accuracy in forming the resistance. It will be possible.

Although the memory cell having the load shown in FIG. 7 has been described as an example of the embodiment, the cell having the resistance R _H as the loads R _H1 and R _H2 and the load shown in FIG. 9 as the loads R _L1 and R _L2 . Also, the effect of the present invention can be expected. This load is characterized in that the impedance of the load switches between the holding state and the selected state. Incidentally, C _C shown in FIG. 9 is intended to prevent soft errors due to α rays particles.

It has been shown in FIG. 7 that the operation of the cell at the time of shifting from the selected state to another state can be stabilized by reducing the H _{FE of the} transistor Q ₂₁ . However, if attention is paid only to the XS state, the collector potential V _C1 (XS) decreases as H _FE decreases. Therefore, the difference from the collector potential V _C0 (XS) in the XS state, that is, the operating voltage of the flip-flop becomes small. This is prevented by the cell shown in FIG. In this case, R _L1 is provided in series with the SBD and the resistor R _L so that the potential drop occurs at R _L1 even with the holding current and discharge current flowing from the cell in the XS state. For example, if R _{L1 is set} to 1 KΩ, the collector potential V _C0 in the XS state shown in FIG. 3 decreases by about 100 mV, and it is possible to compensate for the decrease in the collector potential V _C1 caused by decreasing H _FE .

The characteristic curve CH4 of FIG. 6 shows the C _SBD dependency of the flip-flop operating voltage in the state where H _FE is made different in this cell. As described above, by using the cell shown in FIG. 10, it is possible to more effectively improve the operational margin of the cell by making a difference in H _FE in the region where CS BD is large.

〔The invention's effect〕

As described above, according to the present invention, it is possible to increase the operational margin of a cell for RAM that is suitable for high speed and high integration. Therefore, a high-speed, highly-integrated RAM with stable operation and low power consumption can be obtained. realizable.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a memory cell, FIG. 2 is a cell array configuration diagram, FIG. 3 is a current-voltage characteristic diagram of the memory cell, and FIGS. 4 to 5 are memory cell at the time of state transition. FIG. 6 shows a change in collector potential, and FIG. 6 shows SB of the flip-flop operating voltage.
FIG. 7 is a diagram showing memory cell dependency, FIG. 7 is a memory cell circuit diagram, FIG. 8 is a sectional view for specifically explaining the present invention, and FIG.
FIG. 10 is a load circuit diagram of the memory cell, and FIG. 10 is a memory cell circuit diagram. E ₁₁ and E ₂₁ ... Emitter of cell transistor, W ₁ ... Word line, B ₁ and B ₂ ... Digit line, 6 ... P-type base region of transistor for forming high H _FE , 7 ... Forming low H _FE P-type base regions, 8 and 9 ... N ⁺ emitter regions for

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuo Kanaya 1-280, Higashi Koikekubo, Kokubunji, Tokyo (Inside Central Research Laboratory, Hitachi, Ltd.) (56) Reference JP-A-55-156363 (JP, A)

Claims (4)

[Claims] 1. A bipolar memory cell comprising a flip-flop cross-coupled with a multi-emitter transistor having a first emitter through which a read current flows and a second emitter through which a holding current flows, and a selected state of the memory cell. In a semiconductor memory device including a memory cell formed such that the value of the load impedance connected to the collector of the transistor is different between the time of holding, the state of holding, and the time when only the word line is in the selected state, Is a first resistance element, a Schottky barrier diode connected in series with the first resistance element, and a parallel connection with the first resistance element and the Schottky barrier diode, and the first resistance element A second resistance element having a resistance value larger than that of the first resistance element of the transistor having the first emitter. Than the current amplification factor of the semiconductor memory device being characterized in that to reduce the second current amplification factor of the transistor having the emitter of the second. 2. The semiconductor memory device according to claim 1, wherein the load impedance further has a capacitance connected in parallel. 3. The base region of the multi-emitter transistor is formed so that a thickness of a portion of the base region having the first emitter is smaller than a thickness of a portion of the base region having the second emitter. The semiconductor device according to claim 1 or 2, characterized in that: 4. A first P-type region formed simultaneously with a portion of the base region having the first emitter of the base region of the multi-emitter transistor, and a base region having the second emitter. The second P-type region formed at the same time as the portion forms a P-type resistance region having a different conductivity, which is used in a circuit other than a memory cell. 4. The semiconductor memory device according to any one of items 3.