JPH0618207B2 - Method for manufacturing heterojunction bipolar transistor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a heterojunction bipolar transistor using a heterojunction such as a compound semiconductor.

[Conventional technology]

2. Description of the Related Art In recent years, active research and development have been conducted on semiconductor devices toward higher integration and higher speed. In particular, a bipolar transistor (hereinafter referred to as H
BT) has high emitter injection efficiency, high gain and high speed, and is attracting attention as a next-generation semiconductor element. This HBT can be realized with the progress of thin film multi-layer crystal growth technology of compound semiconductors by the molecular beam epitaxial growth method, the organometallic pyrolysis vapor phase growth method and the like.

In this HBT, the maximum oscillation frequency f _max, which is one index indicating the high speed and high frequency characteristics, is expressed by the following equation.

Here, f _T is the current gain cutoff frequency, R _B is the base resistance, C _BC is the base-collector junction capacitance in the intrinsic region of the transistor, and C _bc is the base-collector parasitic capacitance in the external base region of the transistor.

As is clear from the equation (1), as one means for realizing the high speed operation of the HBT, the base-collector junction capacitance C
_It is necessary to minimize _BC , the base-collector parasitic capacitance C _bc, or the base resistance R _B. Conventionally, in order to realize this high-speed operation, the intrinsic region of the transistor is miniaturized, the base-collector junction capacitance C _BC is reduced, and the substrate on which the transistor is formed is selectively selected from the surface side of the substrate to the external base region. The base-collector parasitic capacitance _Cbc is reduced by implanting oxygen ions with high energy to semi-insulate the base-collector junction.
In addition to these, the external base region is ion-implanted with a dopant that forms the same conductivity type as that of the base layer, and the subsequent heat treatment activates the dopant to reduce the sheet resistance of the external base layer and to form it thereafter. The base resistance R _B is reduced by reducing the contact resistance with the base electrode.

FIG. 2 shows a sectional view of a conventional HBT chip using GaAs / AlGaAs as a heterojunction.

On the semi-insulating substrate 21, a collector layer 22 made of n-type GaAs, a base layer 26 made of p-type GaAs, and n-type AlG.
An emitter layer 27 made of aAs is formed. The base layer 26 and the collector layer 2 immediately below the emitter layer 27
2 constitutes the intrinsic region of the transistor and is responsible for the actual transistor operation. In a region outside this intrinsic region, a dopant (for example, Mg) that selectively forms oxygen ions and p-type conductivity from a surface of the substrate using a mask (not shown) previously provided on the emitter layer 27 is used. 2) is sequentially ion-implanted and heat-treated to form an ion-implanted insulating layer 211 and a base contact layer 212 made of p-type GaAs. With such a configuration, the base-collector parasitic capacitance C _bc in the region outside the intrinsic region is reduced, the sheet resistance of the base contact layer 212 and the contact resistance with the base electrode 29 are simultaneously reduced, and the base resistance R is reduced. _B was reduced.

[Problems to be solved by the invention]

In such a conventional HBT, since the intrinsic region of the transistor is defined by the mask provided on the emitter layer 27, the miniaturization of the intrinsic region is limited by the lithography technique for forming this mask. It That is, in the current photolithography technology, 1 μ
m or less, and 0.5 in electron beam lithography
It is difficult to form a fine mask of μm or less with good reproducibility. Therefore, there is a limit in reducing the base-collector junction capacitance in the intrinsic region.

Further, the ion implantation step and the heat treatment step associated therewith for forming the ion-implanted insulating layer 211 and the base contact layer 212 induce crystal defects in the base contact layer 212 and impurities in each layer of the transistor to the adjacent layers. It was spreading. That is, the base contact layer 21
The crystal defect of No. 2 caused trapping of carriers and prevented sufficient reduction in base resistance. Also, diffusion of impurities,
In particular, diffusion of impurities in the base layer 26 into the emitter layer 27 causes an increase in recombination current, resulting in a significant decrease in emitter injection efficiency. Moreover, even with such ion implantation, the base contact layer 212 and the collector layer 22 are still opposed to each other, so that the base-collector parasitic capacitance C _bc can be reduced by about 30% to 40% at most. There wasn't.

An object of the present invention is to provide a heterojunction bipolar transistor that can significantly reduce the base-collector junction capacitance, the base resistance, and the base-collector parasitic capacitance in the intrinsic region without requiring the ion implantation process that induces the above problems. It is to provide a manufacturing method.

[Means for solving problems]

A method of manufacturing a heterojunction bipolar transistor according to the present invention includes a step of forming a collector layer made of a first semiconductor material on a semi-insulating semiconductor substrate, a mask having a predetermined pattern on the collector layer, and insulating a side surface of the mask. A conductive side wall, a step of etching part or all of the exposed portion of the collector layer using the mask and the insulating side wall, and the etching surface made of an insulating material or a semi-insulating semiconductor material. A spacer layer, and a step of sequentially epitaxially growing a base contact layer made of a second semiconductor material on the spacer layer; a step of etching the insulating side wall to expose the collector layer; the base contact layer and the base contact layer; A base layer made of a third semiconductor material and an emitter made of a fourth semiconductor material on the exposed portion of the collector layer. Configured to include sequentially and a step of epitaxially growing.

[Action]

In the present invention, the junction region between the collector layer and the base layer in the intrinsic region is defined by the insulating side wall. Therefore, by setting the thickness of this side wall thin, the base-collector junction capacitance C _BC can be significantly reduced. .

Furthermore, in the present invention, the collector layer immediately below the external base region is etched, and a spacer layer made of an insulating material or a semi-insulating semiconductor material is formed in this etched region by epitaxial growth. Base-collector parasitic capacitance C _bc depending on thickness
Or the base layer-collector parasitic capacitance _Cbc can be made almost zero by directly etching the collector layer and forming the spacer layer directly on the semi-insulating semiconductor substrate.

Further, in the external base region, since the base contact layer made of the second semiconductor material is formed by the epitaxial growth method, the base resistance can be significantly reduced by adjusting the doping concentration or the thickness of the base contact layer.

Moreover, since each of these layers is formed by the epitaxial growth method, it is possible to prevent the induction of crystal defects and the diffusion of impurities without the need for the ion implantation step and the heat treatment step accompanying it.

〔Example〕

Hereinafter, the present invention will be described with reference to npn type AlGaAs / GaAsHBT.
Will be described as an example with reference to the drawings.

1 (a) to 1 (d) are element cross-sectional views for explaining one embodiment of the present invention in the order of manufacturing steps. First, the first
A semi-insulating substrate 1 made of GaAs as shown in FIG.
N-type GaA with a donor (eg, Si) topped on
The collector layer 12 made of s has a thickness of 0.5 μm to 1.0
After growth using molecular beam epitaxy or metal organic decomposition vapor deposition or the like _μm, SiO 2, S
A mask 13 made of an insulator such as i ₃ N ₄ and having an etching cross section substantially perpendicular to the substrate is formed. this is,
When Si ₃ N ₄ is used as the mask 13, CF ₄ + O
It is realized by processing by reactive ion etching in a mixed gas of ₂ or SF ₆ gas atmosphere. Next, mask 1
An insulating side wall 14 made of a material different from that of the mask 13 is formed on the side surface of the mask 3. The insulating sidewall 14 is formed by the following procedure. First, if the mask 13 is made of Si ₃ N ₄ , for example, SiO ₂ is formed on the entire surface of the substrate by using a film forming method with good step coverage such as chemical vapor deposition. Next, the SiO deposited on the flat portion of the substrate by using an etching method having anisotropy in the etching progress direction, for example, reactive ion etching in a CF ₄ gas atmosphere.
₂ is selectively etched away to form the insulating sidewall 14.

Next, as shown in FIG. 1B, the collector layer 12 is removed by etching using a mask 13 to expose the semi-insulating substrate 11. As the etching means, reactive ion etching with an atmosphere gas such as BCl ₃ gas, Cl ₂ gas or the like, or a reactive ion beam etching, which can obtain a substantially vertical etching cross section, is suitable.

Next, as shown in FIG. 1B, the collector layer 12 is etched using the mask 13 and the insulating side wall 14 as a mask. In the case of the present embodiment, the exposed portion of the collector layer 12 is entirely removed by etching to expose the semi-insulating substrate 11. As the etching means, reactive ion etching or reactive ion beam etching with an atmosphere gas such as BCl ₃ gas or Cl ₂ gas that can obtain a substantially vertical etching cross section is suitable. After that, the exposed region of the semi-insulating substrate 11 is doped with the same material as that of the semi-insulating substrate 11 with a deep energy level donor impurity (eg, oxygen) or a deep energy level acceptor impurity (eg, Cr, Fe). The semi-insulated GaAs is epitaxially grown to reach the upper surface of the collector layer 12 to form the spacer layer 15. Further, an acceptor (for example, Be) is highly concentrated (for example, 4 × 1) on the spacer layer 15.
0 ^{19 to} 10 × 10 ¹⁹ cm ⁻³ ) doped p-type GaA
The base contact layer 16 made of s is epitaxially grown. For the epitaxial growth of the spacer layer 15 and the base contact layer 16, a highly selective growth method typified by a metal organic thermal decomposition vapor deposition method is suitable.

Subsequently, as shown in FIG. 1C, the insulating side wall 14 is selectively etched to expose the collector layer 12. For this etching, for example, if the insulating sidewall 14 is SiO ₂ and the mask 13 is Si ₃ N ₄ , buffered hydrofluoric acid is suitable. After that, a base layer 17 made of p-type GaAs doped with an acceptor (eg, Be) is formed on the collector layer 12 and the base contact layer 16 with a thickness of several tens of nanometers to several hundreds of nanometers and a donor (eg, Si) -doped n layer. An emitter layer 18 of AlGaAs type is epitaxially grown in order to a thickness of several hundred nanometers.

Next, as shown in FIG. 1 (d), the mask 13 and the emitter layer 18 are partially etched by a known method to expose predetermined regions where electrodes on the collector layer 12 and the base layer 17 are to be formed. And an emitter electrode 1 made of an ohmic contact metal (eg AuGe / Ni) for n-type GaAs.
9 and collector electrode 110, and ohmic contact metal (eg AuZn, AuCr,
HB by forming a base electrode 111 made of AuMn, etc.
T is completed.

In this embodiment, the spacer layer 15 is made of semi-insulating GaAs containing a donor or acceptor impurity forming a deep energy level, but GaAs made of an intrinsic semiconductor not doped with impurities may be used. good.
This functions as a semi-insulating material that exhibits a specific resistance of about 10 ⁸ [Ω · cm] at room temperature. Further, an insulating material which is lattice-matched to GaAs such as calcium fluoride and which can be epitaxially grown may be used as the spacer layer.

〔The invention's effect〕

As described above, in the present invention, the junction region between the collector layer and the base layer in the intrinsic region of the transistor is defined by the insulating side wall. Therefore, by setting the thickness of the side wall to be small, the submicron order or subquarter A micron-order bonding region can be easily formed. Further, in the external base region, since the spacer layer made of an insulating material or a semi-insulating semiconductor material can be formed on the semi-insulating substrate, the base layer or the base contact layer and the collector layer do not directly contact or face each other. be able to. Further, since this base contact layer is formed by epitaxial growth, it can be set to have a high concentration and a sufficient thickness.

Therefore, according to the present invention, the base resistance, the base-collector parasitic capacitance, and the base-collector junction capacitance in the intrinsic region of the transistor can be significantly reduced.
The operating frequency of BT can be greatly improved.

Moreover, since the ion implantation and the heat treatment step associated therewith are not required, it is possible to prevent the emitter implantation efficiency from being lowered due to the impurity diffusion.

[Brief description of drawings]

1 (a) to 1 (d) are sectional views of an element for explaining one embodiment of the manufacturing method of the present invention in the order of steps, and FIG. 2 is a sectional view showing an example of a conventional heterojunction bipolar transistor. is there. 11, 21 ... Semi-insulating substrate, 12, 22 ... Collector layer, 13 ... Mask, 14 ... Insulating side wall, 15 ... Spacer layer, 16,212 ... Base contact layer, 1
7, 26 ... Base layer, 18, 27 ... Emitter layer, 1
9, 28 ... Emitter electrode, 110, 210 ... Collector electrode, 111, 29 ... Base electrode, 211 ... Ion implantation insulating layer.

Claims (1)

[Claims] 1. A step of forming a collector layer made of a first semiconductor material on a semi-insulating semiconductor substrate, and a step of forming a mask having a predetermined pattern on the collector layer and insulating side walls on side surfaces of the mask. Etching a part or all of the exposed portion of the collector layer by using the mask and the insulating side wall, and a spacer layer made of an insulating material or a semi-insulating semiconductor material on the etching surface, and the spacer layer A step of sequentially epitaxially growing a base contact layer made of a second semiconductor material thereon, a step of etching the insulating side wall to expose the collector layer, and a third step of exposing the collector layer to the base contact layer and the collector layer. And a step of sequentially epitaxially growing a base layer made of a semiconductor material and an emitter layer made of a fourth semiconductor material. Method of manufacturing a heterojunction bipolar transistor, wherein the door.