JPH0618210B2 - Heterojunction bipolar transistor - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a bipolar transistor using a heterojunction as an emitter-base junction.

[Technical background of the invention and its problems]

Conventional bipolar transistors use npn or the same semiconductor material for the emitter, base and collector layers.
It has a pnp structure. In this case, both the emitter junction and the collector junction are homojunctions.

Recently, a bipolar transistor in which one or both of an emitter junction and a collector junction is a heterojunction has attracted attention and is becoming an object of research and development. One of the advantages of the heterojunction bipolar transistor is that the emitter injection efficiency can be increased by forming the emitter layer from a semiconductor material having a wider bandgap than the base layer. Due to the difference in band gap between the emitter layer and the base layer, carrier injection from the emitter to the base easily occurs when the emitter junction is forward biased.
This is because carrier injection from the base to the emitter is suppressed. Therefore, a higher current gain can be obtained as compared with a normal homojunction bipolar transistor.

The basic concept of such a heterojunction bipolar transistor has been known for a long time, and some publications have been made recently. The conventional basic structure when a heterojunction is used for the emitter junction is shown in FIG.
The figure shows an example using a GaAs-GaAlAs system, in which an n ₊ type GaAs substrate 1 is used, on which an n type GaAs collector layer 2, a p type GaAs base layer 3, and an n type Ga _1-x Al _x As emitter layer 4 are formed. It has a structure in which layers are sequentially laminated. 5 is a collector electrode, 6 is a base electrode, 7
Is an emitter electrode. Emitter layer 4, the emitter electrode 7 side constituted by the first emitter layer 4 ₁ of high impurity concentration (n ^+), a low impurity concentration than that of the base layer 3 side ^- by the second emitter layer 4 ₂ (n) I am configuring. Many of those that are conventionally presented, are common in that they to have a sufficient thickness to the second emitter layer 4 _2. As described above, the reason why the emitter layer has a two-layer structure of a high impurity concentration layer and a low impurity concentration and the thickness of the second impurity layer of a low impurity concentration is sufficiently large is that the emitter junction capacitance C _JE is reduced and the switching speed is reduced. It is said that this is for the purpose of improving the (for example, H. Kroemer, “Heterostrructure Bipola
r Transistors and Itegrated Circuits ”, Proc.IEEE,
Vol. 70, No.1, pp. 13-25, January 1982). In fact, in substantially different one step junction as a boundary joining surface impurity concentration, when the thickness of the low impurity concentration layer is sufficiently large, C _JE alpha the junction capacitance C _JE by using the impurity concentration N _E of the low impurity concentration layer It is well known that it is expressed as N _E ^1/2 .

Here, in order to clarify the following discussion, the concept of transistor switching speed is clarified. Generally, the switching operation of a transistor includes turn-on and turn-off, and a turn-on time t _on and a turn-off time t
_The propagation delay time t _pd obtained by averaging _off is used as a reference for the switching speed. The turn-on time t _on is the time for the output current to rise from 0% to 50%, and the turn-off time t _off is the time for the output current to drop from 100% to 50%. The above relationship is shown in FIG.

The present inventors have recently examined in detail the relationship between the thickness of each layer, the impurity concentration and the switching speed of a heterojunction bipolar transistor as shown in FIG. 1 by a numerical analysis model (for example, Kurata, “Bipolar Transistor "Theory of Operation", 1980 Modern Science Company, M. Kurata, "Nu
merical Analysis for Semiconductor Devices ”, 198
2, Lexington Books DCHeath and Company. As a result, a conclusion contradictory to the conventional theory was obtained. That is, according to the numerical analysis model, the switching speed of a transistor (hereinafter referred to as type A) having a thick second emitter layer with a low impurity concentration as in the conventional example is such that the emitter does not have such a second emitter layer. It is significantly inferior to that of a transistor having only one high impurity concentration layer (hereinafter referred to as type B). The analysis results are shown in Table 1.

The conditions given to this numerical analysis are as follows in the circuit of FIG.
Collector power supply E _C = 2 [V], load resistance R _L = 200
[Ω], input signal voltage V for turning off the transistor Q
_off = 0.5 [V], the input signal voltage V _on to be turned _on is the value shown in the table. In the type A, the second emitter layer has an impurity concentration N _E = 3 × 10 ¹⁶ cm ⁻³ and a thickness ω = 1 μm.
Is. J _E and J _{C in} Table 1 are the current densities of the emitter and collector, respectively.

The reason why the result is contrary to the conventional wisdom is as follows. Generally, in order to perform a high-speed switching operation of a bipolar transistor, it is necessary to set the current density of each of the emitter and collector to 10 ³ to 10 ⁴ A / cm ² or more. This is clear from an example of a bipolar logic integrated circuit and the result of analysis using a numerical analysis model. In the case of having a thick second emitter layer with a low impurity concentration as in type A, the carrier supply capacity from the emitter to the base is lower than in type B, so in order to obtain a predetermined emitter and collector current density, the emitter. A deep forward bias voltage must be applied to the base-to-base junction. Under these operating conditions, excess carriers accumulate in the thick second emitter and collector layers,
This results in an increase in turn-off time and an increase in propagation delay time.

To summarize the above results, although the type A of the emitter junction capacitance C _JE is smaller than the type B, the switching speed of the type B is superior.
This means that not only the emitter junction capacitance C _JE but also the total emitter capacitance C _E = C _JE + C _DE must be taken into consideration as a factor that determines the switching speed of the transistor. C _DE is known as an emitter diffusion capacitance determined by the excess carrier accumulation amount. In the conventional heterojunction bipolar transistor, since the thick second emitter layer with a low impurity concentration is provided, C _DE is C
It is much larger than that of _JE , and the effect on the switching speed due to the reduction of C _JE is not observed at all due to that of C _DE .

From the above, it has been clarified that the type B is more advantageous than the type A in terms of switching speed. However, type B has a drawback that the breakdown voltage of the emitter junction is extremely low because the emitter layer having a high impurity concentration directly forms a junction with the base layer. Normal pn
The avalanche phenomenon is the main cause of the breakdown at the junction, but even if the adranche phenomenon can be avoided, there is a breakdown due to the tunnel effect. In particular, in the case of a heterojunction, the current based on the tunnel effect has many components governed by a large number of interface states existing at the heterojunction interface in addition to the components determined by the direct band-to-band transition of carriers. For this reason, it is not unusual for the actual tunnel current to become much larger than the simple theoretical value, and the emitter junction breakdown voltage becomes extremely small.

[Object of the Invention]

The present invention has been made based on the above consideration, and it is an object of the present invention to provide a heterojunction bipolar transistor which provides optimum design criteria with respect to switching speed and breakdown voltage.

[Outline of Invention]

In the transistor according to the present invention, the emitter layer is composed of a semiconductor material having a wider bandgap than the base layer, and the emitter layer is composed of a first emitter layer having a high impurity concentration and a second emitter layer having a low impurity concentration. It is based on. In this respect, the transistor according to the present invention belongs to the above-mentioned type A. In addition to such a basic structure, the present invention comprises a base layer composed of a first base layer having a low impurity concentration on the emitter side and a second base layer having a higher impurity concentration than the first base layer on the collector side. . Then, the relation between the impurity concentration N _E of the second emitter layer and its thickness W _E and the impurity concentration N _B of the first base layer and its thickness W _B is expressed by the maximum electric field of the emitter-base junction in the state of no applied voltage. As a condition to make the switching speed sufficiently high within the range where the allowable electric field is not exceeded, It is characterized in that it is set to satisfy. In the above formula (1), q is the absolute value of electronic charge (−1.6 × 10 ⁻¹⁹ Coulomb), ε ₀ is the dielectric constant of vacuum (= 8.86 × 10 ^−14).
Farad / cm), ε _SE and ε _SB are the relative permittivities of the second emitter layer and the first base layer, respectively, and V _bi is the built-in potential of the heterojunction formed by the second emitter layer and the first base layer.

The reason for giving such a design standard will be described below. The internal potential difference generated across the junction when the voltage applied to the heterojunction between the emitter and the base is zero is V _bi . The electric field distribution generated at the heterojunction portion due to this potential difference is as shown in FIG. FIG. 4 (a) shows that when the thickness W _E of the second emitter layer and the thickness W _B of the first base layer are sufficiently large, FIG. 4 (b) shows the thickness W _E of the second emitter layer and the thickness of the first base layer. When the thickness W _B is equal to the thickness W _{E, dep} and W _{B, dep} of the depletion layer extending due to the internal potential difference, respectively, in the figure (c), W _E and W _B are smaller than W _{E, dep} , W _B and _dep , respectively. This is the case. Figure 4 (a),
In the case of (b), the following equations (2) to (4) are established according to a well-known theory.

From equations (2) and (3) Is erased, Becomes Similarly, in the case of FIG. 4 (c), the following equations (6) to (8)
Is established.

If E _max is calculated from these three equations, Becomes However, in the above description, the maximum value of the electric field in the depletion layer is E _max , the minimum value of the electric field in the second emitter layer is E _{min, E} , and the minimum value of the electric field in the first base layer is E _{min, B.}

Based on the above relationship, the impurity concentration N of the second emitter layer
_E and the thickness W _E, and the impurity concentration N _B and the thickness W _B of the first base layer are set so as to satisfy the relationship of the expression (1) within a range in which the maximum electric field shown in the expression (9) does not exceed the allowable maximum electric field. As a result, a sufficiently high switching speed is realized while ensuring the breakdown voltage.

The built-in potential V _bi of the heterojunction between the second emitter layer and the first base layer is represented by the following formula (10).

Here, k is the Boltzmann constant, T is the absolute temperature, n _i (T) is the intrinsic electron density of the base layer, X _B is the electron affinity of the first base layer, X _E is the electron affinity of the second emitter layer. (Ten)
In the formula, the first term on the right-hand side is the same as that in the normal homozygote, and the second term is the term unique to the heterozygote.

Specifically, the numerical sequence of V _bi is shown below for typical combinations of impurity concentrations when n-type Ga _0.7 Al _0.3 As is selected as the second emitter layer and p-type GaAs is selected as the first base layer. Is.

According to the present invention, By setting the
A heterojunction bipolar transistor capable of high-speed switching operation while ensuring a breakdown voltage between bases can be realized.

Example of Invention

Examples of the present invention will be described below. The structure of one embodiment using the GaAlAs-GaAs system is shown in FIG. This will be described according to the manufacturing process. First, the n ⁺ type GaAs substrate 1 having a high impurity concentration
1 is used as a starting substrate, and a low impurity concentration n-type GaAs collector layer 12 doped with, for example, Si as an impurity is epitaxially grown thereon. This is a case where the collector-base junction is a homojunction, and when introducing a heterojunction into this junction as well, the n-type Ga _1-x Al _x As layer may be epitaxially grown. In either case, it is preferable to use the MBE method or MOCVD method for the epitaxial growth. The same applies to the following steps. Thereafter, the second base layer 13 2 made of p-type GaAs having a relatively high impurity concentration doped with e.g. Be as an impurity on the collector layer _12, followed by a low impurity concentration p ^- first base layer 13 made of -type GaAs ₁ is epitaxially grown. The thickness of all base layers 13 is preferably 1000 Å or less in order to realize high-speed switching operation. Thereafter, the second emitter layer 1 made of n ⁻ -type Ga _{1 -x} Al _x As with a low impurity concentration is formed on the base layer 13.
4 ₂ , and then the first emitter layer 14 ₁ made of n ⁺ type Ga _1-x Al _x As having a high impurity concentration is epitaxially grown. In both cases, the impurity is S _i , for example. The relationship between the time the second emitter layer 14 ₂ concentrations and thicknesses and the first base layer 13 ₁ of the concentration and the thickness (1) is set so as to satisfy the equation (2). Finally, the peripheral portion is removed leaving the emitter center by etching, to expose the second base layer 13 and _second surface, the collector, base, completed by forming the electrodes 15, 16 and 17 of the emitter.

A more specific numerical example is given and demonstrated. Ga bandgap energy 1.80eV as a first emitter layer 14 _1
0.7 Al _0.3 As layer is used and the donor impurity concentration is N _EO = 1
0 ²⁰ and cm ^-3, and the second emitter layer 14 ₂ to the donor concentration _N E = 10 ¹⁷ cm ^-3 in the same material, the thickness and _W E = 500 Å. On the other hand, the acceptor concentration N as the first base layer 13 ₁
GaAs having a band gap energy of 1.42 eV with _B = 3 × 10 ¹⁶ cm ^-3 and a thickness W _B = 500 Å is used. The second base layer 13 acceptor concentration N _BO = 10 ₂ is the same material
¹⁸ cm ^-3 . At this time, the built-in potential V _bi at room temperature T = 300 ° K is X _E = 3.
77 eV, X _B = 4.07 eV, n _i (T) = 1.101 × 1
As 0 ⁷ cm ^-3, the V _bi = 1.46V.

Therefore, when the applied voltage between the emitter and the base is zero, and if the low-concentration second emitter layer and the low-concentration first base layer are sufficiently thick, the depletion layer thickness W _{E, dep}
And W _{B, dep} and maximum electric field Is calculated from Eqs. (2) to (4), W _{E, dep} = 651Å, W _{B, dep}
= 2332Å, To get However, ε _SE = 12.0 and ε _SB = 12.9 are used. However, in the present case, W _E = W _B = 500Å
Therefore, using this to calculate both sides of Eq. (1), the left side = 2.66 × 10 ⁵ (1 / cm), the right side = 1.62 × 10
⁵ (1 / cm), which satisfies the equation (1). At this time, the maximum electric field E _max is E _max = 1.70 × 10 ⁵ V / cm from the equation (9).
Becomes For the impurity concentration N _E = 3 × 10 ¹⁶ cm ⁻³ , the maximum electric field value that can be tolerated without causing junction breakdown is about 5.1.
Since it is × 10 ⁵ V / cm (eg SMSze, “Physi
cs of Semiconductor Devices ", 1969, Wiley-Intersci
ence), the above E _max is lower than this, and the above design example can be actually adopted. For reference, when the applied voltage such that E _max becomes the maximum allowable electric field is obtained, the value is about 3.3 V, and a practically sufficient breakdown voltage is secured.

Next, as another design example, using the same material as above, N _EO =
10 ²⁰ cm ^-3 , _NE = 10 ¹⁷ cm ^-3 , N _BO = 10 ¹⁸ cm ^-3 , N
_{The case where B} = 10 ¹⁷ cm ⁻³ and W _E = W _B = 500 Å is taken as an example. At this time, V _bi = 1.49 V, W _{E, dep} = 977
Å, W _{B, dep} = 1050Å, To get At this time, both sides of the equation (1) are left sides = 4.20 x 1
0 ⁵ (1 / cm) and the right side = 1.65 × 10 ⁶ (1 / cm), which also satisfies the expression (1). Also, E _max = 2.49 ×
Although it is 10 ⁵ V / cm, the maximum allowable electric field corresponding to the impurity concentration of 10 ¹⁷ cm ^-3 is about 6.4 × 10 ⁵ V / cm, and E
_{Since the} applied voltage at which _max is this allowable value is about 4.5 V, this design example can also be actually adopted.

Table 3 shows the switching characteristics obtained by the numerical analysis model when the above two design examples are applied. The circuit conditions are the same as in Table 1.

As is clear from the comparison of these results with Table 1 above, the switching speed is slightly inferior to the type B but far superior to the type A. Moreover, in the type B, it is difficult to secure the breakdown voltage between the emitter and the base, whereas in this embodiment, it is easy to secure the breakdown voltage practically sufficient.

The present invention is not limited to the above embodiment. For example, as a combination of semiconductor materials, GaP may be used for the wide bandgap emitter layer, Si for the narrow bandgap base layer, and GaA for the wide bandgap emitter layer.
It is also possible to use Ge for the base layer having a narrow bandgap.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing an example of a conventional heterojunction bipolar transistor, FIG. 2 is a diagram for explaining switching characteristics of a transistor, and FIG. 3 is a circuit for similarly obtaining switching characteristics. FIGS. 4 (a) to 4 (c) are diagrams showing an impurity concentration distribution and an electric field distribution for explaining the features of the present invention,
FIG. 5 is a diagram showing a heterojunction bipolar transistor according to an embodiment of the present invention. 11 ...... ^{n +} -type GaAs substrate, 12 ...... n-type GaAs collector layer, 13 ₁ ...... p ^- -type GaAs first base layer, 13 ₂ ...... p
-Type GaAs second base layer, 14 ₁ ... n ⁺ -type Ga _1-x Al _x As first emitter layer, 14 ₂ ... n ^- type Ga _1-x Al _x As second emitter layer, 15-17 ... electrode.

Claims (2)

[Claims] 1. A heterostructure comprising an emitter layer made of a semiconductor material having a wider bandgap than that of a base layer, and a first emitter layer having a high impurity concentration on the electrode side and a second emitter layer having a low impurity concentration on the base side. In the junction bipolar transistor, the base layer is composed of a low impurity concentration first base layer on the emitter layer side and a high impurity concentration second base layer on the collector layer side, and an impurity concentration N of the second emitter layer. _E and thickness W _E, and the relationship between the impurity concentration N _B of the first base layer and the thickness W _B, are defined as the maximum electric field of the emitter-base junction in the state where the applied voltage is zero. Within the maximum allowable electric field, A heterojunction bipolar transistor characterized by being set so as to satisfy. However, in the above formula, q: absolute value of electronic charge ε ₀ : dielectric constant of vacuum ε _SE : relative permittivity of second emitter layer ε _SB : relative permittivity of first base layer V _bi : second emitter layer and first Built-in potential of heterojunction formed by base layer 2. The emitter layer is Ga _1-x Al _x As and the base layer is GaA.
The heterojunction bipolar transistor according to claim 1, wherein the collector layer is GaAs or GaAlAs.