JPH0618226B2 - Bumped film carrier and method of manufacturing the same - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to wireless bonding of a semiconductor chip for an ultra-thin high-density integrated circuit device, and to precisely form a chip-bonding pump on a film carrier side. And a method for manufacturing the same.

[Prior Art] Generally, when manufacturing an IC, an LSI or the like, after bonding a semiconductor chip to a die pad of a lead frame, a wire for bonding a fine gold wire or the like between each electrode of the chip and the outer lead of the lead frame. Wire bonding for bonding one by one is known.

However, in the case of ultra-high-density integrated LSI, etc., the number of pins corresponding to the outer leads reaches several hundreds, so the distance between pins is close to each other by several tens of microns. There are limits to the manufacturing process and quality.

For this reason, in recent years, a tape automated bonding (TAB) method has been widely used in which each electrode of the semiconductor chip is directly thermocompression bonded to the inner lead.

The conventional TAB is a long tape film with a thickness of about 125μ formed of polyimide resin, polyester resin, glass epoxy resin, etc., and a copper foil with a thickness of about 35μ is laminated on the tape film. Drill perforations and device holes that mesh with the sprocket for feeding
In addition, a film in which a predetermined circuit pattern, inner leads, etc. are formed in a continuous manner by a photoresist and etching as many pieces like a photographic film, and each lead portion is electroless tin-plated or electrolytic gold-plated. It uses a carrier.

Further, the semiconductor chip is one in which bumps for thermocompression bonding are formed on the pad portion of the diffused wafer, and a barrier layer (barrier metal) is formed on the back surface of the chip with a predetermined metal, and a gold layer is formed on the barrier layer. A bump of a predetermined size is formed from a metal such as tin or tin, and the bump is thermocompression-bonded to each lead to connect the chip electrode and an external circuit by wireless bonding.

In this conventional example of the TAB method, a protrusion (bump) for bonding is formed on the semiconductor chip side with gold or tin. However, since the barrier metal or bump is formed, a metal film is formed on the diffused wafer. Process-photolithography process-strike treatment process-plating process-resist removal process-photolithography process-photolithography process-etching process-resist removal process-annealing process, etc., and one wafer with bumps thus obtained Each of them is attached to a nest plate with wax, and is diced after dicing, and then the bonding is performed.

Therefore, the manufacturing process is quite complicated, and it is difficult to precisely deposit a large number of minute bumps on each electrode of the small chip, which inevitably increases the production cost and makes it only for a special purpose.

For this reason, recently, means for forming bumps with a thickness of 10 to 30 .mu. Made of metal such as gold on the inner lead side of the film carrier is becoming popular, and the following method is well known.

First, the first example is a method in which the inner lead end is photoetched and a mesa-shaped bump slightly raised from the inner lid surface is formed there by injection plating.

The second example is a transfer bump method, in which a predetermined number of gold bumps are once deposited by plating using a mask on a glass substrate, and then this is thermocompression-bonded to the inner lead side of the film carrier. It is a method of transferring the bumps there.

[Problems to be Solved by the Invention] In the above first example, since the minute plating portion is formed at the tip of the inner lead by the conventional partial plating means, the plating deposition layer is actually a mesa-shaped bump although it is a mesa-shaped bump. Is thin and has an irregular shape, which causes variations in the plating thickness, and if it is left as it is, it will hinder the bonding with the chip.

Therefore, post-processing requires shaping of the bump surface,
Further, if perfect shaping cannot be performed, a bonding error is likely to occur, and there is a problem in terms of quality, productivity and cost.

On the other hand, according to the means of the second example, since precise alignment is required twice when forming the bumps on the glass substrate and when transferring the bumps to the film carrier, the yield in the mounting process is low. Especially, it may be difficult to mount a semiconductor chip having an ultra-multi pin structure.

In particular, when bumps are formed on a glass substrate, they become sharp mesa-shaped bumps at that time, but when they are thermally transferred to the film carrier side, they are turned upside down.

That is, the sharpened portion is attached to the surface of the inner lead,
The bottom surface having a larger area is upward (inverted taper shape), and the diameter of the bump top portion becomes larger than that of the bottom portion and tends to be larger than the width of the inner lead.

Therefore, the lead interval cannot be made extremely fine, and it is unsuitable for a chip with a super-multi-pin structure.

Moreover, since the tops of the bumps are wide and flat, the top surfaces of the bumps are less likely to be deformed by heating and pressure during bonding with the chip.

Furthermore, when the top surface of the bump is deformed due to the pressing force and is bonded to the chip electrode, the fresh metal surface (new surface) inside the bump is not exposed one after another, so the bonding ability is deteriorated, resulting in high accuracy and high quality. However, there is a problem that the chip bonding is difficult.

In addition to the above, each frame (circuit pattern) formed on a conventional film carrier is in a state in which the leads of all frames are connected by a common pattern during the etching process, and The leads are all electrically connected.

For this reason, conventionally, after the chips are bonded, the common pattern is punched for each frame in a separate step, and the leads are separated and independent.

Therefore, if a punching error occurs, the film carrier already mounted on the chip is likely to be lost, and the electrical check for the chip bonding error cannot be performed until after the chip is divided in the final process, which hinders the process quality control. was there.

In addition to the above, in the conventional film carrier with bumps, the bumps are formed only on the inner leads, and after the chips are joined by the inner lid bonding (ILB), the outer lead bonding (OLB) is performed in a separate process. It was joined to the electrode.

In the case of this OLB, unlike the bonding of the chips, the surface treatment material of the bonding portion uses a metal such as tin, and the processing thickness is considerably smaller than that of the bumps (2 to 3 μ).

As described above, ILB and OLB are required to have completely different bonding functions and processing steps, and conventionally, the two have been completely separated and processed.

Therefore, there is also a problem that it takes a considerable number of steps including setup.

Furthermore, in the bump formation in both the first and second known examples, the plating deposition rate is as high as 1 μ / tens of seconds, and it takes a considerable time to form the bump.

However, when the chips are directly formed, each wafer on which a large number of chips are arranged is processed. Therefore, when the chips are divided into a large number of chips, the work cost per chip can be relatively low.

On the other hand, when the bumps are formed on the film carrier side by the conventional means, there is a problem that the above-mentioned construction cost is considerably worried because each frame is processed.

[Means for Solving the Problems] The present invention has been made in view of the above problems, and is a method for directly forming a bump on a lead tip of a semiconductor chip mounting lead frame or a film carrier, It is an object of the present invention to provide a bump forming method in which the bumps are formed at precise positions and a high-quality one can be obtained, and a semiconductor chip having an ultra-high pin count can be mounted with high efficiency.

As a means for achieving the above object, in order to obtain a cathode potential required when performing a partial plating treatment for bump formation, the entire pattern formed in advance on the film carrier is cut by punching the electrically connected portion. Then, after electrically separating all the inner leads, each inner lead is brought into contact with a probe, and a predetermined plating power source is applied between the probe and the cathode to control the plating current, plating time, etc. Precise bumps can be formed on the tips of the leads.

In addition, the bumps formed on the tip of the inner lead that has been divided in advance are designed for ultra-multi-pin structure semiconductor chips with a shape in which the new surface can be exposed in sequence from the surface during bonding and the size is smaller than the width of the inner lead. Even at the time of completion of chip bonding, an electrical check can be performed if necessary.

Further, a main bump for bonding (ILB) with a semiconductor chip is formed on the tip of the inner lead, and a sub bump for bonding (OLB) with an external circuit electrode is formed on a predetermined portion of the outer lead. ILB and OL
Both B can be continuously processed.

[Operation] As described above, in order to obtain the cathode potential necessary for the plating treatment, the inner leads are divided beforehand, and the probes that are in contact with the respective inner leads are connected in series with resistors, which are connected in parallel with the resistors. The plating current value flowing through each inner lead is measured through the sweep signal generator section, the A / D converter and the computer, the data is analog-digital converted and read by the computer, and the sampling interval time is set to the current value. Multiply and convert to Coulomb quantity.

Further, while the electrochemical equivalent of the deposited metal and the amount of metal deposited during the sampling interval can be obtained from the Coulomb amount, the plating area for bump formation at the tip of each inner lead is set in advance, so The plating deposition thickness can be obtained by dividing the amount of the deposited metal by the plating area.

That is, kit = shρ (1) holds.

However, if electrochemical equivalent …… k plating current value …… i sampling interval time …… t plating area …… s plating deposition thickness …… h deposited metal specific gravity ρ, from the above formula (1), h = kit / Sρ is obtained.

Therefore, when the accumulated value of the deposited thickness reaches a predetermined thickness, the switch portion is turned off and the plating for forming the bumps is completed, whereby the bumps having a uniform thickness as a whole can be formed at the tip of the tape carrier.

In this case, in order to prevent the plating area from changing, it is necessary to perform a masking plating process or to form a plating resist on the tip of the inner lead.

For example, 100 pins per side (that is, 400 pins in total)
In the case of the TAB, if 100 seconds is used for 1 pin of A / D conversion with 1 second as the measurement cycle using the instrument of 4 A / D conversion elements.
It will be shared by the D conversion elements, and 1/1 per pin
The measurement time is 00 sec = 10 msec.

In general, the conversion speed of the 12-bit successive comparison type A / D inverter is several + μsec including the time of software, and therefore the above measurement is sufficiently possible.

Therefore, if the accumulated plating thickness reaches the predetermined value and the deposition rate is about 1 μ / sec, the variation in the plating thickness among 100 pins is within 1 μ, and the tolerance of the variation is the same. Can be related to the plating current density.

Since the bumps can be formed independently for each inner lead in this way, the size, thickness, shape, etc. of the bump can be accurately formed. Therefore, the bump can be made smaller than the width of the inner lead, and at the time of ILB. It is easy to form a new surface on the bonding surface of the bump, and the bonding result can be electrically monitored.

Furthermore, the outer lead is made of metal such as tin or solder,
By forming the second bump (width bump) for B, the bonding with the external circuit electrode can be continuously and automatically processed.

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

A film carrier 1 shown in FIG. 1 is formed by forming a polyimide resin film in which copper foils are laminated into a long tape shape, and a square hole (perforation) 2 for feeding a film in the polyimide resin film.
And a piece composed of an outer lead 4 which is provided with a device hole 3 and which is connected to an electrode of an external circuit board (not shown), and an inner lead 6 which is located at the tip of the outer lead 4 and is connected to the electrode of the semiconductor chip 5. This is a general one in which a large number of common patterns 7 connected by etching are connected to each other, and a common pattern 7 to which all the frames are connected is also formed by etching.

In this embodiment, first, a predetermined portion of the film carrier is treated with a plating resist by photoetching or the like to expose the copper foil portion only at a necessary portion to form a bump forming portion described later.

Next, a predetermined portion of the command pattern 7 is punched by punching to electrically isolate the outer leads 4 from each other.

As means for forming bumps on the film carrier 1, processing is performed under the structure shown in FIG.
The outer lead 4 of the film carrier 1 in the above state is on the cathode electrode K side.

Further, a predetermined number of probes 9 are arranged corresponding to each of the outer leads 4, an opening / closing switch 10 and a resistor 11 for controlling plating current conduction are connected in series to the probe 9, and the resistor 11 is connected to the cathode electrode 12. A predetermined plating power source 13 and a timer 14 are connected between this and the anode electrode A (plating solution injection nozzle or the like).

Further, the driving is controlled by the timer 14, and the sweep signal generator 15 is provided between each of the resistors 11 and the open / close switch 10 so that the voltage drop of each of the resistors 11 can be sequentially measured, and the output thereof is analog digital of the next stage. Converter (A / D converter)
After being input to 16 and converted into a digital signal, it is input to a control computer (CPU) 17, and the on / off switch 10 is controlled to be turned on / off by a relay sequence control output signal of the CPU 17.

Incidentally, the sweep signal generator 15 is, as shown in FIG.
A large number of proximity sensors 19 correspondingly connected to the respective probes 10 are circumferentially arranged on the base 18, and each is connected to the CPU 17, and the rotor 2 rotating at a constant speed.
The number 0 is provided so that it sequentially contacts the proximity sensor 19, and it is possible to know from which number of the proximity sensor 19 the signal is output.

Under the above conditions, when forming bumps on the tips of the leads, the plating solution is first sprayed and the timer 14 is operated to close the anode 8 and the cathode 12 to apply a predetermined DC voltage. By doing so, bumps can be deposited and formed at predetermined locations.

The bump metal is gold, tin, aluminum, copper or the like.

In the present invention, during the above-mentioned plating treatment, a large number of plating spots are sequentially scanned at regular intervals, and the plating current of the relevant portion is controlled and controlled so that a precise deposition amount of the plating metal can be obtained.

Next, the above operation will be described with reference to the time chart of FIG.

First, when the timer 14 is turned on, the plating current is applied as shown in (a), and at the same time, the sweep signal generator 15
Is driven, and the sweep signal shown in (b) is generated.

That is, when the roller 20 rotates, the pulsed sweep signals are generated at a constant interval of 1 to n, but n after one cycle.
The measurement of the plating state is started from the time when the +1 to n + n sweep signals are generated.

In this way, as shown in (d), the plating metal deposition state is intermittently measured for several times during a constant current measurement period. The switch 10 is opened, and the energization of the plating current is stopped. [See (e)] When the last open / close switch 10 is opened, the deposition of all plating is completed. [Refer to (f)] That is, during the current measurement period, the resistance 1 of the corresponding circuit
A voltage drop value (plating current value) of 1 is obtained from the A / D converter.

This value is written in a state of being sequentially added to a predetermined memory address in the CPU 17.

The result of this addition is Therefore, assuming that the measurement cycle is T, the total charge is Q = AT.

For example, the electrochemical equivalent of monovalent gold is m, the specific gravity of gold is ρ,
If the plating area is s and the plating thickness is h, then mQ = mA
T = shρ holds.

Therefore, h = mAT / sρ = A · mT / sρ, but since mT / sρ in the above equation is a preset constant, it can be expressed by h = A · C (C is a constant).

Here, since h is a required plating thickness, if h is a set value, A = h / C is also a constant.

Therefore, the measured value X obtained via the probe 9 is X <
In the state of A, the plating can be continued as it is, and in the case of X ≧ A, the plating can be terminated.

When the plating is completed, the plating process is stopped only for the specific inner lead 6 by opening only the open / close switch 10 to stop the energization in response to the stop command signal from the CPU 17.

Of course, at this time as well, the plating current is applied to each of the other inner leads 6, but they also stop in the same manner when the predetermined plating thickness is reached. It is possible to control the plating process.

Further, by such plating control means, it is possible to deposit the plating metal on the end of the inner lead in a state of gradually rising, so that it is possible to form a bump having a thickness, shape and size optimum for bonding. As shown in FIG. 5, a bump 22 having a diameter smaller than the width W of the inner lead 6 was obtained, and the sectional shape thereof was also a truncated cone shape as shown in FIG.

With the shape of the bumps 22, when bonding with the chip 5, the heads are crushed by the heating pressure as shown in FIG. The new surface of the deposited metal is exposed, and strong bonding can be performed.

Next, another embodiment of means for obtaining the bump will be described.

In this method, a bump is formed by directly performing a minute partial plating on each inner lead 6 by using a means according to Japanese Patent No. 1261266 "Plating method and apparatus for minute area".

That is, as shown in FIG. 8, the inner lead 6 of the film carrier is brought into contact with the mask 23 for setting the area to be plated, and the outer tube 24 forming a predetermined closed space is connected to the mask 23. The inside of the outer tube 24 is kept in a constant negative pressure state. Further, a nozzle 25 for jetting a plating solution is arranged in the outer tube 24 in a state of being close to the work, and this is connected to the anode pole A while the inner lead 6 is connected to the cathode pole K. There is.

The electric control system connected to the probe 9 is the same as that of the above-mentioned embodiment, and therefore its explanation is omitted.

In this state, the noble metal such as gold is plated. However, since the distance between the electrodes is close as described above, the plating is performed at a high current density, and the inside of the mantle tube 24 is in a negative pressure state. Therefore, the plating solution staying in the vicinity of the nozzle is forcibly sucked and removed, and a fresh plating solution can be constantly supplied, so that extremely precise minute partial plating can be performed, and the processing time is extremely short.

The plated metal deposit (bump 2
In 2), the thickness is sufficient for bonding (30 μm) and the cross-sectional shape is trapezoidal, and the contour of the plated portion can be a precise bump 22 corresponding to the mask shape.

Moreover, as described above, since the control for compensating the plating thickness is provided, the bumps 22 are provided between the inner leads 6.
There is no variation in thickness, and the accuracy of plating thickness intersection ± 1.0μ can be sufficiently maintained.

Further, when the means according to the present embodiment is used, the plating accuracy, as well as the plating processing time and the process yield are far better than the partial plating means using a resist, so that the production cost can be suppressed to a very low practical value. There is.

Next, another embodiment will be described with reference to FIG.

First, there are a plurality of processing steps, and a first bump forming step relating to a plating processing configuration similar to that of the first embodiment,
The second bump forming process having the same structure is continuously provided.

The first bump forming step is for processing metal plating such as gold suitable for ILB, whereas the second bump forming step is for processing metal plating such as tin suitable for OLB. In addition, the control threshold value in each CPU 17 is changed so that the plating processing suitable for each plating thickness can be performed.

Then, plating resist is photo-etched on predetermined portions of the inner lead 6 and the outer lead 4, respectively,
Set the plating point.

After that, the leads are electrically separated by punching, and then, in the first bump forming step, first, the main bumps 26 are formed on the inner leads 6 with gold or the like by the same method as in the first embodiment.

The main bump 26 has a material, thickness, size, and shape suitable for bonding with a chip as described at the beginning.

After that, in the second bump forming step in the next stage, the sub bump 27 is formed on the outer lead 4 by tin or the like by the same method as in the first embodiment.

The sub-bump 27 has a material, thickness, size, and shape suitable for bonding with the electrode of the external circuit element, and can be easily realized by adjusting the set value of the plating processing control system.

The film carrier 1 obtained by the above continuous process,
Since multiple bumps for different purposes are processed at the same time, both inner lead bonding and outer lead bonding can be processed easily.

Needless to say, the method of forming a plurality of bumps can utilize the minute partial plating method in the negative pressure sealed space, which is advantageous in terms of productivity and quality.

As shown in FIG. 10, in order to maintain the tip position of the inner lead 6 projecting in the device hole 3 of the film carrier 1, a frame body 29 connected to the film carrier body by a bridge 28 is used. A single or a plurality of bumps can be formed by the means according to the present invention even for the one interposed between the outer lead 4 and the outer lead 4.

[Effects of the Invention] As described above, according to the present invention, the following effects are obtained.

． Since a bump having a diameter smaller than the width of the inner lead can be formed and the forming position can be made accurate, it is most suitable for a film carrier for ultra-multi-pins having leads with an extremely fine pitch.

． Since the thickness of the bumps can be controlled extremely precisely, the bumps that are truly necessary for chip bonding can be formed, and the yield in the bonding process can be improved.

． Since the shape of the bump can be frusto-conical, a new surface is sequentially exposed at the bonding surface with the chip during bonding, so high-quality bonding can be performed.

． Since each lead is electrically divided in advance, this dividing treatment step is not required after chip bonding,
The yield in the lead cutting process is improved, and the presence or absence of a bonding error can be easily checked.

． Since multiple types of bumps can be formed on each of the outer lead and the inner lead, depending on the application,
Both outer lead bonding and inner lead bonding can be processed continuously, and productivity can be greatly improved.

． Since a bump forming process on a film carrier has been conventionally used, it is considerably rationalized as compared with a known method and can be formed with much higher precision, and the yield can be further improved, so that a high quality product can be provided at an extremely low price.

[Brief description of drawings]

FIG. 1 is a plan view of one frame of a general film carrier, and FIG. 2 and the following figures are related to an embodiment of the present invention.
FIG. 2 is an explanatory view of a process of forming bumps on the film carrier, FIG. 3 is an explanatory perspective view showing a structure of a sweep signal generator used in the same process, and FIG. 4 is a time chart diagram of the same process. FIG. 5 is a partial plan view showing a bump formed on an inner lead, FIG. 6 is a partial sectional view of the same as above, FIG. 7 is an explanatory sectional view showing a state of chip bonding, and FIG. 8 is another bump forming means. FIG. 9 is a schematic structural cross-sectional view of a partial plating apparatus using negative pressure according to the embodiment, and FIG. 9 shows a main portion of the same embodiment in which a plurality of types of bumps are formed on each of the inner lead and the outer lead. Partial perspective view, first
FIG. 0 is a partial perspective view of a main portion according to an example in which the above-described plurality of types of bumps are formed on the film carrier on which the protective frame for the inner leads is formed. 1 ... Film carrier 4 ... Outer lead 6 ... Inner lead 7 ... Common pattern 8 ... Anode electrode 9 ... Probe 10 ... Open / close switch 13 ... Plating power supply 14 ... Timer 15 ... Sweep signal generation Device 16 ... A / D converter 17 ... CPU 22 ... Bump 26 ... Main bump 27 ... Sub bump

Claims (6)

[Claims] 1. A synthetic resin film carrier main body made of a material suitable for bonding a semiconductor chip to the front and / or back surface of each tip of the inner leads, the bonding portion (top) area being smaller than the bottom area, and the inner lead surface. A sub bump having a shape similar to that of the above-mentioned main bump, which is formed of a material suitable for forming a main bump having a shape raised by a predetermined thickness from the above, and bonding an external circuit board electrode to a predetermined portion on the front surface and / or the back surface of the outer lead. A film carrier with bumps, which is capable of processing both inner lead bonding and outer lead bonding. 2. The film carrier with bumps according to claim 1, wherein the inner leads of the synthetic resin film carrier body are independently separated according to each circuit. 3. A frame body having a structure connected to the film carrier body by a bridge is interposed between a synthetic resin film carrier body and the inner leads to hold the positions of the main bump and the sub bump. A film carrier with bumps according to claim 1, characterized in that the film carrier has bumps. 4. An inner lead of a film carrier body is electrically separated, and a predetermined number of probes abutting on each of the separated inner leads are used as a cathode electrode to plate the inner lead at a predetermined portion. The nozzle side that injects the solution is used as an anode electrode, and a predetermined plating power supply is connected between both electrodes, and the plating solution is injected to the inner lead portion, and the plating current is measured through the probe and at the same time the current value is measured. A method of manufacturing a film carrier with bumps, wherein the amount of deposited plating and the shape of plating are controlled individually for each inner lead. 5. A plating treatment part is set by subjecting a predetermined portion of the surface of the inner lead and / or the outer lead of the film carrier body to a resist plating treatment, and the partial plating is treated to deposit and form the bump. The method for manufacturing a film carrier with bumps according to claim 4, characterized in that. 6. A plating portion is set by closely adhering a mask to a predetermined portion of the surface of the inner lead and / or the outer lead of the film carrier body, and a jacket tube is connected to the mask to form a closed space and a negative pressure is applied. 5. The bump according to claim 4, characterized in that the bumps are formed by applying a plating solution from a nozzle arranged in the outer tube and energizing it through the probe when in the state. Of manufacturing a film carrier with an adhesive.