JPH0618315B2 - Circuit device having flip-flop - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a circuit device having a flip-flop suitable for a control circuit of a tape recorder, a VTR or the like for mode switching such as recording, reproducing, fast-forwarding and stopping.

Conventional technology The mode setting circuit of the conventional general tape recorder is
It is constructed by an RS flip-flop, and the flip-flop is reset when the power is turned on. FIG. 1 shows an example of a mode setting circuit of a conventional tape recorder. The mode setting RS flip-flop (1) has two OR type NAND gates (2).
(3) has a set terminal S for receiving a low level reset signal, a reset terminal R for receiving a low level reset signal, a Q output terminal and an output terminal. A power supply circuit (5) connected to an AC power supply via a power switch (4) includes a rectifier, a smoothing circuit and a voltage stabilizing circuit, and a flip-flop (1) and a set signal generating circuit.
(6), reset signal generation circuit (7), power-on signal generation circuit
It is a circuit that supplies DC power supply voltage to (8) The set signal generating circuit (6) includes a resistor (9) connected between the power supply circuit (5) and the set terminal S, and a normally open contact set switch (9) connected between the set terminal S and ground. 10) and always applies a high level voltage (first voltage level) to the set terminal S, and outputs a low level (second voltage level) set signal only when the switch (10) is turned on. Is configured to grant. The reset signal generation circuit (7) is composed of a resistor (11) connected to the power supply circuit (5) and a reset switch having a normally closed contact structure connected between the output end of the resistor (11) and the ground. A low level voltage is normally generated through the reset switch 12 and a high level voltage is generated when the reset switch 12 is turned off. The output of the reset signal generating circuit (7) is connected to the reset terminal R via the NOR gate (13). Therefore, a low level (second voltage level) signal is supplied as a reset signal to the reset terminal R of the flip-flop (1). The power-on signal generation circuit (8) is the power circuit (5)
Connect a differentiating circuit consisting of a capacitor (14) and a resistor (15) between the output line (5a) and the ground of the capacitor (1
It is constructed by deriving the detection line (16) from between the resistor (15) and the resistor (15). The detection line (16) is NOR
Connected to the input terminal of the gate (13).

If the flip-flop (1) is a flip-flop for setting the play mode of the tape recorder, the switch (10) is a place switch, and the switch (12) is a stop switch,
When the place switch (10) is turned on, the flip-flop (1) is set and a high level play control signal is sent from the Q output terminal. Then, when the stop switch (12) is turned off, the flip-flop (1) is reset, the Q output terminal becomes low level, and the play control signal disappears. When the power switch (4) is turned on to use the tape recorder, a high-level differential pulse is generated from the power-on signal generation circuit (8), and a low-level reset signal is output via the NOR gate (13). It is applied to the flip-flop (1), and the flip-flop (1) is always in the reset state.

FIG. 2 shows a mode setting circuit in the case where the RS flip-flop (17) is composed of two NOR gates (18) and (19). In this example, a set signal generation circuit for generating a high level set signal between the set terminal S and the power supply line (5a).
(20) is connected, power supply line (5a) and NAND gate (22)
A reset signal generation circuit (21) for generating a low-level reset signal is connected between the input signal and one of the input terminals.
The output of the NAND gate (22) is the flip-flop (1
It is connected to the reset terminal R of 7). Also power line
A power-on signal generation circuit (23) consisting of a resistor (24) and a capacitor (25) connected between (5a) and ground generates a low level differential pulse on the detection line (26) and NAN
It is configured to supply to the other input terminal of the D gate (22). In the case of the circuit of FIG. 2 as well, the flip-flop (17) can be put into the reset state in synchronism with the power-on as in the circuit of FIG.

By the way, the circuit of FIG. 1 requires the NOR gate (13), the circuit of FIG. 2 requires the NAND gate (22), and further the capacitor (14) or (25) to form the differential pulse. . Therefore, miniaturization and simplification of the circuit configuration are hindered.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to reduce the size and simplification of a circuit device that resets the flip-flop when the power is turned on.

The first invention of the present application for achieving the above object is to generate a DC voltage in response to an operation of the power switch and the power switch, wherein the DC voltage is generated when the power switch is operated. Has a power supply circuit configured to rise with an inclination toward a constant value, a set terminal and a reset terminal, the voltage of the reset terminal is higher than a threshold level and the set terminal is An RS flip-flop configured to be in a set state when the voltage is lower than the threshold level, and to be in a reset state when the voltage of the set terminal is higher than the threshold level and the reset terminal is lower than the threshold level. A first resistor connected between the power supply circuit and the set terminal, and a resistor connected to the power supply circuit. A second resistor connected between the set terminal and
A set signal generating circuit for applying a voltage lower than the threshold level to the set terminal when the RS flip-flop is set, and a voltage lower than the threshold level for setting the RS flip-flop in the reset state. A reset signal generating circuit that is applied to a reset terminal, is connected between the second resistor and the reset terminal, and a voltage applied from the power supply circuit to the reset terminal when the power switch is turned on is applied. A resistor voltage divider that divides the input voltage of the reset terminal so that the time when the voltage applied to the set terminal from the power supply circuit becomes higher than the threshold level becomes higher than the time when the voltage applied to the set terminal becomes higher than the threshold level. Circuit having flip-flop consisting of It is those related to the location.

A second invention of the present application is to generate a DC voltage in response to an operation of the power switch and the power switch, wherein the DC voltage has a slope toward a constant value when the power switch is operated. Has a power supply circuit configured to rise up and a set terminal and a reset terminal, and is in a set state when the voltage of the reset terminal is lower than the threshold level and the set terminal is higher than the threshold level. And an RS flip-flop configured to be in a reset state when the voltage of the set terminal is lower than the threshold level and the reset terminal is higher than the threshold level, the power supply circuit and the set terminal. A first resistor connected between the first resistor and a second resistor connected between the power supply circuit and the reset terminal. A resistor, a first inverter connected between the first resistor and the set terminal, a second inverter connected between the second resistor and the reset terminal, and the RS flip-flop. A set signal generating circuit for giving a signal for putting the amplifier to the set state to the set terminal through the first inverter, and a signal for putting the RS flip-flop in the reset state through the second inverter. A reset signal generation circuit for giving to the reset terminal is connected between the first inverter and the set terminal, and when the power switch is turned on, the power circuit passes through the first inverter. At the time when the voltage applied to the set terminal becomes lower than the threshold level, the power supply circuit passes through the second inverter. A circuit device having a flip-flop comprising a resistance voltage dividing circuit for dividing the input voltage of the set terminal so that the voltage applied to the reset terminal becomes lower than the threshold level. Is.

The correspondence between the two inventions and the embodiment will be described. The power supply circuit is the power supply circuit (5) including the rectifier, the smoothing circuit, etc. shown in FIGS. 3 and 5, and the first and second The resistors are the resistors (9) and (11) in FIGS. 3 and 5,
The voltage dividing circuit is a circuit including resistors R1 and R2, the set signal generating circuit is a circuit including a set switch (10a), and the reset signal generating circuit is a reset switch (12).
It is a circuit including a).

Effect of the Invention According to the first aspect of the invention, the RS flip-flop can be reset when the power is turned on with a relatively simple configuration in which the voltage dividing circuit is connected to the stage preceding the reset terminal. According to the second aspect of the invention, the RS flip-flop is reset when the power is turned on by a relatively simple structure in which the voltage dividing circuit is connected to the stage before the set terminal.

Example Next, an example of the present invention will be described with reference to FIGS. Figure 3 shows the RS flip-flop (1)
A play mode setting circuit of a tape recorder including two OR type NAND gates (2) and (3) is shown as in the figure. Also in the circuit of FIG. 3, a power switch (4), a power circuit (5) and a power line (5a) having the same configuration as in FIG. And the set terminal S. Set signal generation circuit
(6a) is a resistor (9) connected between the power supply line (5a) and the set terminal S, and a normally open contact set (play) connected between the output end of the resistor (9) and the ground. ) Switch (10a)
, Which normally outputs a high level (first voltage level) voltage, but generates a low level (second voltage level) set signal when the switch (10a) is turned on.
The reset signal generation circuit (7a) consists of a resistor (11) connected to the power supply line (5a) and a reset (stop) with a normally open contact structure connected between the output end of this resistor (11) and ground. It consists of a switch (12a). (20) is a voltage dividing circuit, which is connected between the output line (21) of the reset signal generating circuit (7a) and the reset terminal R of the RS flip-flop (1).
The voltage dividing circuit (20) is composed of a first resistor R ₁ connected in series with the line (21) and a resistor R ₂ connected between the output terminal of the resistor R ₁ and the ground. , Has a partial pressure ratio of. NAN of RS flip-flop (1)
The D gates (2) and (3) are composed of C-MOS and have high input impedance and low input leakage current characteristics. Also,
The threshold level V _s of the flip-flop (1) set and reset is substantially the same.

FIG. 4 shows the voltage change when the power switch (4) is turned on in the circuit of FIG. When the power switch (4) is turned on at time t _{0 in} FIG. 4, there is a slope according to the time constant determined by the smoothing circuit included in the power circuit (5) and the capacitor connected to the power line (5a). Then, the power supply voltage rises, and the output of the set signal generating circuit (6a) follows the power supply voltage and rises to the low level V _L (second
Voltage level) to a high level V _H (first voltage level). The output of the reset signal generating circuit (7a) is, if by a voltage dividing circuit (20) is not, as indicated by a dotted line in FIG. 4 (B), consisting of a low level V _L to the high level V _H. Since the set signal generation circuit (6a) and the reset signal generation circuit (7a) are connected to the same power supply circuit (5), the output voltage rise time T ₀
Will be the same. Since the flip-flop (1) has a high input impedance C-MOS structure, the resistance (9) of the set signal generating circuit (6a) is substantially independent of the voltage change of the set terminal S at the rise of the power supply voltage. . Therefore, Fig. 4
The voltage at the set terminal S shown in (A) follows the rise of the power supply voltage and is at a high level V equal to the steady-state power supply voltage after T ₀ time.
_{Reach H} (first voltage level). Then, if Threading Shiyu hold level to be approximately intermediate between V _S of V _H, excisional terminal voltage from power point t ₀ to ₁ hour after T crosses Threading Shiyu hold level V _S.

On the other hand, since the voltage dividing circuit (20) is provided between the reset signal generating circuit (7a) and the reset terminal R, the reset terminal voltage does not reach the high level V _H equal to the power supply voltage and is divided. It is limited to the voltage Vh. Now, reset signal generation circuit
If the value of the resistor (11) of (7a) is r, the high level Vh of the reset terminal voltage is given by the following equation.

Figure 4 from power point t ₀ shown in (B) time T ₀ until steady state is reached the high level Vh of reset terminals S, the voltage of the excisional terminal S shown in FIG. 4 (A) is a high level V _H It is equal to the time to reach. Therefore, the time t ₂ at which the reset terminal voltage crosses the threshold level V _S in FIG.
It is after t ₁ . The flip-flop (1) has a voltage lower than the threshold level V _{S at the set} terminal S.
It is set when it is applied to the
Since it is configured to be reset when it is applied to, the period t ₀ to t _{1 in} FIG. 4 (A) is a set signal generation period, and the period t ₀ to t _{2 in} FIG. 4 (B). The period is a reset signal generation period. Since after the completion of excisional signal generation period t ₀ ~t ₁ is reset signal generation period t ₀ ~t ₂ exists, flip-flop (1) must be reset state upon power-up.

after t ₃ point, turns on the excisional (play) switch (10a), excisional terminal S is grounded, excisional terminal voltage V _A is low from a high level V _H (first voltage level)
It changes to V _L (second voltage level), a low level V _{L set} signal is generated, and the Q output terminal changes from low level to high level. Flip Flop (1) set state (play mode set state), reset (stop) switch (1
When 2a) is turned on, the reset terminal R is connected to the voltage dividing circuit (20).
A reset signal of low level V _L is generated, and the Q output terminal changes from high level to low level.

As is clear from the above, according to this embodiment, V _H > V h> V
Only by providing the voltage dividing circuit (20) satisfying _S , the reset operation when the power is turned on becomes possible. Therefore, the circuit configuration can be simplified and downsized.

FIG. 5 shows a mode setting circuit of the second embodiment. The RS flip-flop (17) of this embodiment includes two N-channel MOS transistors having a high input impedance and a low input leakage current.
It is composed of OR gates (18) and (19). As in the case of FIG. 3, the flip-flop (17) is also set so that the threshold levels V _S of the set and the reset are almost the same. The set signal generation circuit (6b) connects a resistor (9) to the power supply line (5a) to obtain a high level set signal, and a set (play) with a normally open contact between the output terminal and the ground. It is configured by connecting a switch (10b) and further providing an inverter (24). This output line (23) is connected to a set terminal S via a voltage dividing circuit (20) composed of resistors R ₁ and R _2. It is connected to the. Reset signal generator (7
b) is the power line to obtain a high level reset signal
A resistor (11) is connected between (5a) and the reset terminal R, and a reset (stop) switch (12b) having a normally open contact structure is connected between this resistor (11) and the ground, and an inverter ( twenty four)
Is provided.

The operation of the circuit of FIG. 5 will be described with reference to FIG. 6. By turning on the power switch (4), the output voltage of the power circuit (5) rises with a constant time constant. The outputs of the set signal generating circuit (6b) and the reset signal generating circuit (7b) gradually decrease as shown in FIGS. 6 (A) and 6 (B). At this time, the output voltage of the reset signal generation circuit (7b) becomes the reset signal as it is as shown in FIG. 6 (B), but the output voltage of the set signal generation circuit (6b) is the voltage divider circuit. And is supplied to the set terminal S. As a result, at time t ₁ when the input voltage of the set terminal shown in FIG. 6 (A) crosses the threshold level V _S , the input voltage of the reset terminal shown in FIG. 6 (B) becomes the threshold level V _S. It becomes earlier than the time point t ₂ when the vehicle crosses, and the reset state is surely obtained. Therefore, according to the second embodiment, it is possible to obtain the same effect as that of the first embodiment.

Modifications The present invention is not limited to the above-described embodiments, but can be modified. For example, the present invention is not limited to tape recorders, but can be applied to VTRs, optical disc devices, magnetic disc devices, and the like. Further, various modifications may be made to the set and reset signal generation circuits.

[Brief description of drawings]

1 and 2 are circuit diagrams showing a conventional mode setting circuit, FIG. 3 is a circuit diagram showing a mode setting circuit according to a first embodiment of the present invention, and FIG. 4 is a circuit diagram showing each part of FIG. FIG. 5 is a waveform diagram showing the state, FIG. 5 is a circuit diagram showing the mode setting circuit of the second embodiment of the present invention, and FIG. 6 is a waveform diagram showing the state of each part of FIG. (1) …… RS flip-flop, (2) (3) …… NAND gate, (4) …… Power switch, (5) …… Power circuit, (6a) (6
b) ... Set signal generation circuit, (7a) (7b) ... Reset signal generation circuit, (17) ... RS flip-flop, (18) (19) ...
... NOR gate, (20) ... voltage divider circuit.

Claims (2)

[Claims] 1. A power switch, and a DC voltage generated in response to an operation of the power switch, wherein the DC voltage rises with a slope toward a constant value when the power switch is operated. And a set terminal and a reset terminal, and when the voltage of the reset terminal is higher than a threshold level and the set terminal is lower than the threshold level, the set state is set, and the set An RS flip-flop configured to enter a reset state when a voltage of the terminal is higher than a threshold level and the reset terminal is lower than the threshold level, and is connected between the power supply circuit and the set terminal. First
, A second resistor connected between the power supply circuit and the reset terminal, and a set signal generation for applying a voltage lower than the threshold level to the set terminal when the RS flip-flop is set. A circuit, a reset signal generation circuit for applying a voltage lower than the threshold level to the reset terminal when the RS flip-flop is in a reset state, and connected between the second resistor and the reset terminal. When the voltage applied to the reset terminal from the power supply circuit is higher than the threshold level when the power switch is turned on, the voltage applied to the set terminal from the power supply circuit is the threshold level. The reset terminal so that it occurs after the time when it goes higher than A circuit device having a flip-flop composed of: 2. A power switch and a DC voltage generated in response to an operation of the power switch, wherein the DC voltage rises with a slope toward a constant value when the power switch is operated. And a set terminal and a reset terminal, and when the voltage of the reset terminal is lower than a threshold level and the set terminal is higher than the threshold level, the set state is set, and the set An RS flip-flop configured to enter a reset state when a voltage of the terminal is lower than a threshold level and the reset terminal is higher than the threshold level, and is connected between the power supply circuit and the set terminal. First
Resistor, a second resistor connected between the power supply circuit and a reset terminal, a first inverter connected between the first resistor and the set terminal, and the second resistor A second inverter connected between the reset terminal and the reset terminal; and a set signal generation circuit for giving a signal for setting the RS flip-flop to the set terminal to the set terminal via the first inverter, A reset signal generating circuit for applying a signal for resetting the RS flip-flop to the reset terminal via the second inverter; and a reset signal generating circuit connected between the first inverter and the set terminal, When the power switch is turned on, the voltage applied to the set terminal from the power circuit via the first inverter is the threshold level. The input voltage of the set terminal is set so that the voltage applied to the reset terminal from the power supply circuit via the second inverter is lower than the threshold level. A circuit device having a resistance voltage dividing circuit for dividing voltage and a flip-flop composed of.