JPH0618366B2 - Timing recovery circuit for modem - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a modulation / demodulation device connected to a communication line.
The present invention relates to a timing reproduction circuit that reproduces reception timing.

〔Overview〕

In a modulator / demodulator that is connected to a communication line and performs timing recovery from the transmitted signal, the received input is converted from analog to digital, this digital output is demodulated and input to the transversal filter, and the output of the transversal filter is output. By extracting the reception timing, modifying the tap coefficient of the transversal type filter with this reception timing, and using the output as the reproduction timing, it is possible to perform highly accurate timing reproduction by using all digital circuits. It was done.

[Conventional technology]

The timing reproduction of the digital processing transmission apparatus is important not only for providing a judgment and identification point but also for providing a sampling point which influences the characteristics of the entire receiving system including automatic equalization.

Conventionally, there is a nonlinear extraction method (“application of digital signal processing”, edited by The Institute of Electronics, Information and Communication Engineers, Corona Publishing Co., P.169) as one of the timing recovery techniques for a modulator / demodulator.

In this method, the line spectrum of the modulation frequency f _b is QAM,
Since it is not included in the PSK signal, this is generated by a non-linear operation such as squaring or full-wave rectification, and is a method of extracting with a narrow band filter.

FIG. 5 is a block diagram showing a circuit configuration when this conventional example system is applied to the baseband region. Analog / digital converter 51, demodulator 52, narrow band filters 53, 54, 55 constituting the reception timing extraction unit, multiplication circuit 5
6, 57, adder circuit 58, and digital phase-locked loop 59 for timing recovery
It is composed of f _s is the sampling frequency.

Here, the effects of carrier frequency and phase shift are suppressed by adding waveforms from two demodulated data of in-phase and quadrature. The reception timing extracted by the narrow band filter 55 is input to the digital phase locked loop 59. The digital phase locked loop 59 performs timing reproduction by comparing a certain fundamental frequency with this reception timing and changing the division ratio of the fundamental frequency.

This digital phase locked loop 59 can also be realized by an analog voltage suppression oscillator.

FIG. 6 is a block configuration diagram of a circuit using an analog voltage controlled oscillator instead of the digital phase locked loop 59. Reference numeral 61 is an input terminal, reference numeral 62 is a phase comparator,
Reference numeral 63 is a low pass filter, reference numeral 64 is an analog voltage controlled oscillator, and reference numeral 65 is an output terminal.

Since the frequency of the analog voltage control oscillator 64 is variable depending on the voltage, the reception timing and the analog voltage control oscillator 64
The output timing is compared with the output waveform of 1 to control the voltage in the direction in which the phase difference disappears to reproduce the reception timing.

[Problems to be solved by the invention]

However, in such a conventional timing reproduction circuit,
Digital phase locked loop 59 and analog voltage controlled oscillator
There are the following problems because 64 is used.

When the digital phase-locked loop 59 is used, the accuracy of the reception timing depends on the frequency at which the digital phase-locked loop 59 operates, so in order to obtain the reception timing with high accuracy, this frequency must be set high. There was a flaw that had to be made.

Further, although accuracy is improved when the analog voltage controlled oscillator 64 is used, an additional circuit is required, and the hardware is integrated into a circuit for downsizing of the device, economic efficiency, and low power consumption. There is a problem in achieving (LSI).

The present invention solves such conventional problems,
It is an object of the present invention to provide a timing reproduction circuit for a modulation / demodulation device in which timing reproduction can be obtained with high accuracy and a timing reproduction circuit can be easily integrated into an LSI.

[Means for solving problems]

The present invention uses an input terminal connected to a communication line to input a received waveform, a fixed oscillator that oscillates at a fixed frequency, and a received waveform from the input terminal as input, and performs analog-digital conversion in synchronization with the output of the fixed oscillator. An analog-to-digital conversion circuit that performs the above, a demodulation circuit that demodulates the output signal of this analog-to-digital conversion circuit, a unit that extracts the reception timing from the output of this demodulation circuit and reproduces the timing, and extracts this timing reproduction output. In the timing reproduction circuit of the modulation / demodulation device having an output terminal, the means for performing the timing reproduction by extracting the reception timing is a transversal filter having the output of the demodulation circuit as an input, and the output of this transversal filter. Extract the reception timing from the taps of the transversal filter A reception timing extraction circuit that outputs a correction signal and a tap coefficient correction circuit that corrects the tap coefficient of the transversal filter by the output of the reception timing extraction circuit, and the output of the transversal filter includes the reproduction timing signal of the reproduction timing signal. It is characterized in that the output terminal is connected to obtain reproduction data.

[Work]

According to the present invention, the input reception waveform is subjected to analog-digital conversion, the converted digital signal is demodulated and input to the transversal filter. On the other hand, the output of the transversal filter is converted into a reception timing signal by multiplying the value of the tap coefficient corrected by the tap coefficient correction circuit and adding them.

The tap coefficient correction circuit is controlled by the output of the reception timing extraction circuit connected to the output of the transversal filter.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, a reception waveform input terminal 2 to which a phase-modulated waveform is input is connected to an input of an analog / digital converter 1. A fixed oscillator 3 is connected to the analog / digital converter 1. Although this determines the sampling frequency of the analog-digital converter 1, it does not have to be synchronized with the reception timing of the modem. The demodulator 4 is connected to the output of the analog-digital converter 1, demodulates the analog-digital converted value, and outputs the demodulated value to the transversal filter 5. Each output of the transversal filter 5 is input to the adder circuit 7 via the tap coefficient correction circuit 6, and the output of the adder circuit 7 is sent to the output terminal 8 as a reception timing signal. Further, the output of the adder circuit 7 is branched and input to the reception timing extraction circuit 9, and the output of the reception timing extraction circuit 9 corrects each tap coefficient.
Connected to. The output terminal 8 is further provided with an automatic equalizer, C
A receiving system such as a PC judging device is connected.

The taps of the transversal filter 5 are set for every 1/2 cycle of the demodulation frequency, and the tap coefficients are controlled by the output of the reception timing extraction circuit 9. The reception timing extraction circuit 9 has the same structure as the timing extraction unit shown by the dashed line in the conventional circuit shown in FIG. 5, and the output 8 of the transversal filter corresponds to the demodulator output shown in FIG. . Therefore, the reception timing signal here is
It can be said that the demodulated signal is resampled at the reception timing.

The transversal filter 5 realizes a low-pass filter, and tap coefficients therefor can be realized by changing the value of the impulse response of the low-pass filter according to the output of the reception timing extraction circuit 9. . However, since it takes time to calculate the impulse response each time, the value of the impulse response that can be taken for each tap is calculated and stored in the coefficient ROM in advance. When taking an intermediate value between the values stored in the coefficient ROM, it is obtained by temporary interpolation.

Here, the interpolation method when switching from the transmission timing to the reception timing will be described. That is, the tap coefficient to be taken by the transversal filter 5 is mathematically derived.

FIG. 2 is a block configuration diagram showing an example of a circuit for obtaining interpolation by an analog method. The transversal filter 5 of this embodiment realizes the interpolation shown in FIG. A method of obtaining the tap coefficient of the transversal filter 5 will be described based on.

In FIG. 2, the digital / analog converter 10, a low-pass filter 11, and a sampling circuit 12 are provided. The input point a of the digital-analog converter 10, the input point b of the low-pass filter 11, and the sampling circuit 12 are shown. The signals at the input point c and the output point d of the sampling circuit 12 are S _n , S (t), x (t), and x _n . However,
S _n and x _n are digital signals, S (t), x
(t) is an analog signal. Extending this to a digital signal, Becomes This equation (1) is the digital sampling data S
The continuous output signal S (t) when _n is converted into an analog signal through the D / A converter 10 is shown. The output signal x (t) when this S (t) passes through the low-pass filter 11 is Becomes The impulse response of the low pass filter 11 at this time is h (t). Then, the sampling value x _n when this output signal x (t) is sampled at the reception timing cycle T'is x _n = x (nT ') (3) where T is the sampling cycle and T'is the reception timing. It is a period, and when | t | ≦ T / 2, u (t) = 1, and when | t |> T / 2, u (t) = 0.

Substituting equation (1) into equation (2), However, And can be represented by the digital input value S _n of the output x (t) of the low-pass filter 11.

When the tap coefficient when the output is set to x _n is obtained from the equations (3) and (4), If nT ′ = mT + α, Becomes

Therefore, if g (α + (m−k) T) is the tap coefficient of the transversal type filter, x _n shown in the equation (5) is obtained.
Is the output of the transversal filter, and the reception timing signal (1 / T ') can be obtained from the value sampled at an independent frequency (1 / T).

The tap coefficient g (α + (m−k) T) is obtained as the impulse response of the low pass filter 11 shown in the model from the equation (5).

The accuracy of the reception timing obtained by this method can be improved by increasing the number of taps of the transversal filter and the number of significant digits of the tap coefficient.
If these calculations are performed with an accuracy of 16 significant digits, accuracy as high as that of the clock of several tens of MHz of the prior art can be realized.

Further, since this circuit can be realized by all digital circuits, it can be very easily made into an LSI.

In the case of an echo canceller type two-wire full-duplex modem,
The received waveform is converted from analog to digital at the transmission timing. The analog-digital converted value is subjected to subtraction of the echo signal obtained from the transmission data of its own station, and then converted to the reception timing. Particularly, when operating in the slave mode, accurate timing reproduction is required, but the timing reproduction method of the present invention can be applied.

Specifically, in FIG. 1, the baud rate frequency, f _b = 1 / T = 2.4 kHz, the transmission waveform shaping 20% roll-off filter, the sampling frequency of the analog / digital converter 1
f _s = 4.8 kHz (this is asynchronous with the above baud rate frequency).

FIG. 3 is a diagram showing an outline of frequency characteristics of a low-pass filter used in a transversal filter and a transmission waveform shaping filter.

The low-pass filter used here is a 30% roll-off filter with a sampling frequency of 4.8 kHz.

The tap coefficient of the transversal filter is generated by using a ROM that receives the control signal as an address input.
The configuration can be simplified by using the method of storing the tap coefficient corresponding to each address of.

FIG. 4 is a diagram showing a simulation result of the interpolation method. The transversal filter has 200 taps and the tap coefficient is calculated directly from the impulse response formula of the low pass filter, and the tap coefficient is stored in the coefficient ROM.
It is a graph when the difference of the value read from the above and obtained by linear interpolation is regarded as an error. At this time, the phase difference between the transmission timing and the reception timing is assumed to be different from the transmission baud rate clock by half the interval of the coefficient ROM.

〔The invention's effect〕

As described above, the present invention can accurately perform timing reproduction by using the transversal filter in the timing reproduction system of the modulation / demodulation device.

Further, since this circuit can be realized by all digital circuits, there is an excellent effect that it can be very easily made into an LSI.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a block diagram showing a circuit for explaining the interpolation method. FIG. 3 is a diagram showing characteristics of various filters. FIG. 4 is a diagram showing a simulation result of the interpolation method. FIG. 5 is a block diagram showing a conventional circuit. FIG. 6 is a block diagram showing a circuit example using a VCO. 1 ... Analog / digital converter, 2 ... Reception waveform input terminal, 3 ... Fixed oscillator, 4 ... Demodulator, 5 ... Transversal filter, 6 ... Tap coefficient correction circuit,
7 ... Addition circuit, 8 ... Output terminal, 9 ... Reception timing extraction circuit, 10 ... Digital / analog converter, 11 ...
… Low-pass filter, 12 …… Sampling circuit, 51 ……
Analog-digital converter, 52 ... Demodulator, 53, 54,
55 ... Narrow band filter, 56, 57 ... Multiplication circuit, 58 ... Addition circuit, 59 ... Digital phase-locked loop (DPL)
L), 61 ... input terminal, 62 ... phase comparator, 63 ... low pass filter, 64 ... analog voltage controlled oscillator (VC)
O), 65 ... Output terminal.

Claims (1)

[Claims] 1. An input terminal connected to a communication line for inputting a reception waveform, an analog-digital conversion circuit for performing analog-digital conversion using the reception waveform of the input terminal as an input, and an output signal of the analog-digital conversion circuit. In the timing recovery circuit of the modulation / demodulation device, which comprises: a demodulation circuit for performing demodulation, a means for performing timing recovery by extracting the reception timing from the output of this demodulation circuit, and an output terminal for extracting the timing recovery output, The conversion circuit is provided with a fixed oscillator for giving a fixed frequency sampling signal, and the means for extracting the reception timing and reproducing the timing includes a transversal filter having the output of the demodulation circuit as an input, and a transversal filter of the transversal filter. Extract the reception timing from the output and The transversal filter includes a reception timing extraction circuit that outputs a tap coefficient correction signal of a sversal type filter, and a tap coefficient correction circuit that sequentially corrects the tap coefficient of the transversal type filter by the output of this reception timing extraction circuit. A timing reproduction circuit of a modulation / demodulation device, characterized in that the output terminal of the reproduction timing signal is connected to the output of the above to obtain reproduction data.