JPH0618433B2 - Image signal processing method and apparatus - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for processing an image signal used in an image scanning recording apparatus such as a scanner or a facsimile, and particularly to an original image by a one-dimensional photoelectric conversion element array. The present invention relates to a method and apparatus for processing an image signal obtained by photoelectric scanning.

(Prior Art and Problems Thereof) A one-dimensional photoelectric conversion element array such as a CCD line sensor, a CPD line sensor, and a MOS type line sensor is intended to be applied to applications requiring high output resolution such as a platemaking scanner. If, the upper limit of the input resolution is
It is determined by the shape and characteristics peculiar to the one-dimensional photoelectric conversion element array used. That is, the one-dimensional photoelectric conversion element array is formed by linearly arranging a large number of photoelectric conversion elements having a certain area, and the arrangement direction is the main scanning direction. Therefore, the input resolution in the main scanning direction is It depends on the number of photoelectric conversion elements. Therefore, in order to increase the input resolution in the main scanning direction, it is necessary to increase the number of photoelectric conversion elements included in the one-dimensional photoelectric conversion element array, but there is a limit for one device.

On the other hand, the input resolution in the sub-scanning direction is determined by the shape, charge storage time, and scanning speed in the sub-scanning direction in, for example, an accumulation type device. Therefore, without changing the shape of the device, it is possible to increase the amount of irradiation light to shorten the accumulation time and increase the input resolution in the sub-scanning direction. Causes another problem such as fever. Even if the illumination of the original image is made strong and the accumulation time can be shortened, if the obtained signal charges are read out at high speed within the accumulation time, at high gradation (for example, 12 bits) required for plate making,
The conversion speed of the A / D converter in the next stage cannot catch up, and in order to cope with it, it is necessary to take measures such as parallel processing using a plurality of expensive A / D converters, which makes the processing circuit complicated and expensive. It causes another problem such as

A method of arranging a plurality of one-dimensional photoelectric conversion element arrays in a linear or staggered manner to form a high-resolution plate-making scanner is also proposed. In this case, alignment of the one-dimensional photoelectric conversion element array is performed. In addition, it takes time and effort to adjust the optical system, and the processing circuit for the obtained image signal is complicated and expensive.

(Object of the Invention) The present invention solves the above-mentioned problems of the prior art, and uses a relatively small number of one-dimensional photoelectric conversion elements to form a scanner with a simple structure and at a low cost. It is an object of the present invention to provide an image signal processing method and apparatus capable of processing.

(Means for Achieving the Object) In order to achieve the above object, the image signal processing method according to the present invention is: In an image signal processing method for obtaining an output resolution higher than the input resolution by A / D converting the input image signal obtained by scanning and performing interpolation processing on the input image signal, the interpolation processing is a) a first interpolation process of sequentially storing image signals of two pixels adjacent in the main scanning direction and interpolating those image signals in the main scanning direction based on the output resolution; and (b) adjoining in the sub scanning direction. The first image signal group and the second image signal group are sequentially stored in the first and second line storage means for each scanning line segment, and these image signal groups are interpolated in the sub-scanning direction based on the output resolution. In the process Thus, (b-1) a step of outputting the first image signal group stored in one line storage means and storing the second image signal group in the other line storage means in synchronization with it. b-2) The first and second image signal groups stored in the first and second line storage means are output to obtain an interpolated image signal group of scanning lines corresponding to the output resolution, and each interpolated image is obtained. A second interpolation process including a step of sequentially outputting a signal group, and a step (b-3) of switching the second image signal group to the first image signal group, the first and second One of the interpolation processes is executed, and the other interpolation process is executed for the image signal obtained by the interpolation process. The device displays the original image in the main scanning direction and the sub scanning direction. One-dimensional photoelectric conversion element array for photoelectrically scanning at a predetermined input resolution, A / D converter for converting an input image signal from the one-dimensional photoelectric conversion element array into a digital signal, and main scanning and sub-scanning for the digital signal In an image signal processing apparatus that has an interpolating unit that interpolates in the direction and obtains an output resolution higher than the input resolution, the interpolating unit is (a-1) an image of two pixels adjacent in the main scanning direction. Storage means for sequentially storing signals, and (a-2) first calculation means for calculating an image signal for interpolating the image signal stored in the storage means in the main scanning direction based on the output resolution, A first interpolating means including (b-1) a first image signal group and a second image signal group which are adjacent to each other in the sub-scanning direction, and are stored for each scanning line segment.
Line storage means, and (b-2) control means for outputting the first image signal group stored in one line storage means and storing the second image signal group in the other line storage means in synchronization with it. And (b-3) an interpolation image signal group of scanning line segments corresponding to the output resolution is calculated based on the first and second image signal groups stored in the first and second line storage means. Second calculation means for sequentially outputting each of the interpolated image signal groups, and (b-4) switching means for switching the second image signal group to the first image signal group after outputting the interpolated image signal group, A second interpolating means comprising: an interpolating means for executing the processing by any one of the first and second interpolating means, and for the image signal obtained by the interpolating processing, the other interpolating means. Is performed.

(Operation) By adding interpolation processing to the input image signal obtained from the one-dimensional photoelectric conversion element array, the output resolution can be improved with respect to the input resolution of the one-dimensional photoelectric conversion element array.

The interpolation processing includes a first interpolation processing performed in the main scanning direction,
The second interpolation process performed in the sub-scanning direction is clearly distinguished,
After performing either one of the interpolation processes, the other interpolation process is performed based on the interpolated image signals, so that a simple circuit required for one-dimensional interpolation in each of the main scanning direction and the sub scanning direction. Can perform two-dimensional interpolation processing.

In the second interpolation processing, the image signal group for one scanning line is stored in each of the two line storage units, and while the first image signal group stored in one line storage unit is being output. , The second image signal is stored in the other line storage means, and the first and second image signal groups stored in the first and second line storage means are output to output scanning line segments corresponding to the output resolution. After the interpolation image signal group is obtained, the second image signal group is switched to the first image signal group, so that the interpolation processing in the sub-scanning direction can be continuously performed by only two line storage means.

(Description of Embodiments) FIG. 2 is a block diagram showing an example of the configuration of a plate-making scanner to which the present invention is applied. An input image signal obtained by photoelectrically scanning an original image (not shown) by a one-dimensional storage type photoelectric conversion element (hereinafter referred to as CCD) 1 such as a CCD line sensor is a multi-gradation digital image signal by an A / D converter 2. Are converted into a plurality of line memories 3 for storing the input image signal. The image signal appropriately read from the line memory 3 is subjected to gradation correction in the gradation correction circuit 4 (color correction is also performed in the case of a color image signal), and then in the sharpness enhancement circuit 5 in the main scanning direction and the sub-scanning direction. The sharpness enhancement processing is applied to at least one of the directions, and is given to the interpolation circuit 6.

The interpolation circuit 6 performs the interpolation process according to the present invention, the details of which will be described later. The interpolated image signal is
An image signal having a desired magnification is converted by the magnification conversion circuit 7, and then a halftone dot generation circuit 8 performs halftone dot generation processing. An AOM (acousto-optical converter) drive circuit 9 receives a signal from the halftone dot generation circuit 8 and drives the exposure unit 10 to record a desired halftone dot image on a photosensitive material (not shown).

When a continuous-tone image (including characters) is recorded, the halftone dot generation processing by the halftone dot generation circuit 8 is not performed as indicated by the dotted line in the figure.

3 and 4 are conceptual diagrams showing an image input optical system including the CCD 1. The photoelectric conversion elements of the CCD 1 are arranged in the main scanning direction, and the reflected light from the original image 11 forms an image on the CCD 1 via the condenser lens 12.

Referring to FIG. 4, the input resolution (the number of read images per unit length when photoelectrically scanning the original image) is determined by the magnification (m) of the optical system and the size of one element of the CCD 1, and When the input resolution is L _inx , the input resolution in the sub-scanning direction is L _iny , and the lengths of one element of the CCD 1 in the main-scanning direction and the sub-scanning direction are dx and dy, respectively, the following relational expressions are established.

L _inx = m / dx (line / mm) (1) L _iny = m / dy (line / mm) (2) That is, in order to improve the input resolution, the element size is made small or the optical It suffices to increase the magnification of the system and increase the number of elements in one scanning line. However,
Performance factors such as storage time and operating frequency are not considered. As described above, there is a limit to the improvement in input resolution due to such dimensions.

By the way, generally, in the plate making scanner as described above, the resolution of the image signal given to the halftone dot generating circuit 8 is 10 to 20 line / mm (250 to 500 line / inch).
If the degree is good, the quality of the halftone image recorded on the light-sensitive material will be satisfactory for the time being. However, a higher resolution is desirable when more precise plate making is required, or when a line drawing original is processed, and in such a case,
The output resolution of the image processing circuit including the A / D converter 2 to the magnification conversion circuit 7 is, for example, 39.4 line / mm (1
000 line / inch) or more is desirable. Now
As an example of the design, this output resolution is 59.1 line / mm
(1500 line / inch), A4 size (297 x 210)
mm) Let us consider the case where the short side of the paper is the sub-scanning direction and this is processed in 1 minute using a CCD of 5000 elements. In this case, the number of times of recording in the sub-scanning direction per second is 210 × 59.1 ÷ 60 = 206.9 (times / sec), and the recording time per one time (that is, the recording time of one scanning line) is about 5 ms. Is. Therefore, in order to obtain an input resolution similar to this output resolution in the sub-scanning direction, it is necessary to set the illumination so that the accumulation time of the CCD is about 5 ms, which requires considerably powerful illumination.

Further, if the same input resolution is to be provided in the main scanning direction, the required number of CCD elements at this time is 297 × 59.1 = 17553 (pieces), and in the case of a 5000-element CCD, four pieces are required. It is necessary to lay one part linearly, and to realize this optical system, it is necessary to overcome difficult problems such as connecting CCDs and adjusting horizontal positioning. further,
Since the accumulation time needs to be set to about 5 ms as described above, the transfer clock frequency of accumulated charges is 17553 ÷ (5 × 10 ^-3 ) ≈3.5 × 10 ⁶ (Hz), which is obtained at this repetition rate. Output is 1 A /
The conversion speed is about 0.3 for processing by the D converter.
Must be less than μs. Generally, since the conversion speed of a 12-bit A / D converter for high gradation used for platemaking is 1 μs or more, parallel processing by a plurality of A / D converters is required, and the circuit becomes complicated and expensive. Become.

For this reason, when high output resolution is required such as in a platemaking scanner, it is not a good idea to raise the input resolution to the same level as the output resolution.
The input resolution is set to a value somewhat lower than the output resolution in consideration of the characteristics of D, the characteristics of the A / D converter, etc. An effective means is to interpolate in the direction to improve the image quality when output is performed with high resolution.

The interpolation circuit 6 of FIG. 2 is provided for such a purpose, and an example of its configuration is shown in the block diagram of FIG.

In FIG. 1, CCD 13 and A / D converter 14
Corresponds to the CCD 1 and the A / D converter 2 in FIG. Interpolation processing is performed in the shift register 15 and below, but in an actual plate-making scanner, as shown in FIG. 2, gradation correction is performed between the A / D converter 14 and the shift register 15 in FIG. And a circuit for enhancing sharpness is provided.

The CCD 13 is one having about 5000 elements, and the A / D converter 14 is one having 12 bits, which are generally available. Then, clock signals CK _im , CK _is , C provided from a clock generator (not shown)
By appropriately selecting the repetition frequency of K _om and CK _os , the ratio of the input resolution and the output resolution is set to, for example, 1: 4 in both the main scanning direction and the sub scanning direction. By doing so, even when high output resolution is required such as plate making, the CCD 13 and the A
A scanner can be configured using the / D converter 14. It should be noted that an example of a specific design under such a condition is shown at the end of this description, and should be referred to.

In the configuration of the interpolation circuit of FIG. 1, the two-stage shift register 15 includes the digital image signal from the A / D converter 14 for only two pixels (D _n , D _n-1 ) continuous in the main scanning direction. Store temporarily. Adders 16-1, 16-2, ... 1
6- (N-1), these image signals D _n, it receives the D _n-1, performs predetermined interpolation calculation. Here, N is a ratio of input / output resolution in the main scanning direction, and in this embodiment, N = 4 is set as described above. Therefore, the adder 16
Is three, and the adder 16-1 is (3D _n-1 + D
_n ) / 4 is calculated, and the adder 16-2 outputs (2D _n-1 + 2D
_n ) / 4, and the adder 16-3 calculates (D _n-1 +
Calculate 3D _n ) / 4.

Generally, according to the value of N, the calculation shown in the following table is performed to generate the interpolated image signal.

The adders 16-1, 16-2, ... Can be configured by using, for example, a lookup table. In that case,
A look-up table memory for multiplying D _n or D _n-1 by 1 / N and (N-1) / N, ... 12-bit to 8-bit is converted at the time of log conversion, and a table memory for reading the multiplication result value is provided with the 8-bit value of D _n or D _n-1 as an address, and the output is added. Good. However, D _n
It is easier to add the two terms for the terms for which the average value of D _n−1 and D _n−1 is taken and shift the result by 1 bit.

The data selector 17 has N input terminals 0, 1, 2,
, N-1, and the input terminal 0 has a shift register 15
Image signal D _n-1 is input from the output signal of the adder 16-1 is input to the input terminal 1, an output signal of the adder 16-2 is input to the input terminal 2, also an input terminal N- The output signal of the adder 16- (N-1) is input to 1. These input signals are sequentially selected according to the output count number of the N-ary counter 18 and output from the data selector 17.

The output image signal is output to the first line memory 19 and the second line memory 20 for each one scanning line.
It is stored alternately. Then, next, via the tri-state buffer amplifiers 21 to 24 acting as gates,
Reads are made on the read lines 25 and 26, respectively. In this case, the timing of the tri-state buffer amplifiers 21 to 24 is controlled so that the image signal of one scanning line which is previously scanned is always read out on the read line 25. The timing control and the timing control of writing and reading of the first and second line memories 19 and 20 are managed by the memory control 27.

The adders 28-1, 28-2, ..., 28- (M-1) are
In this way, one on each of the read lines 25 and 26.
Image signals of two adjacent scanning lines that are sequentially read out for each scanning line are received, and a predetermined interpolation calculation is performed between them. Here, M is a ratio of input / output resolution in the sub-scanning direction, and in this embodiment, M = 4 is set as in the case of N described above. Therefore, the number of adders 28 is three, which is the same as the number of adders 16. The interpolation calculation to be performed by the adder 28 is similar to the interpolation calculation performed by the adder 16 described above, and in general, the calculation in which N is replaced with M in the above table is performed to obtain the interpolated image. A signal is generated.

Note that D _n-1 and D _n in the table represent a pair of image signals that are adjacent to the adder 16 in the main scanning direction, but are adjacent to the adder 28 in the sub scanning direction. Will represent a pair of image signals. The adder 28 is the adder 1 described above.
Similar to item 6, it can be configured using a lookup table.

The data selector 29 has M input terminals 0, 1, 2,
, M-1, and the image signal on the read line 25 (that is, the image signal for one scanning line previously scanned) is input to the input terminal 0, and the adder 28 is input to the input terminal 1. -1
Output signal is input to the adder 28-2 at the input terminal 2.
Of the adder 28- (M-1) is input to the input terminal M-1. These input signals are sequentially selected according to the output count number of the M-ary counter 30 and output from the data selector 29.

FIG. 5 is a timing chart showing the operation of the interpolation circuit of FIG. The operation of the interpolation circuit shown in FIG. 1 will be described below with reference to FIG. The CCD 13 receives the input sub-scanning clock signal CK _is shown in FIG. 5 (a) and puts the charge accumulated in each photoelectric conversion element into a transferable state (specifically, CC
(Transferred to the CCD shift register in D13), and then in synchronization with the input main scanning clock signal CK _im of FIG. 5 (b),
The accumulated charges are sequentially transferred and read out. The image signal thus obtained is output by the A / D converter 14 to 12
It is converted into a multi-tone digital image signal of bits.

FIG. 6 (a) schematically shows a part of the input image signal, and A to J respectively represent one pixel. As described above, since the input resolution is set to 1/4 of the output resolution in both the main scanning direction and the sub scanning direction,
If a part of the image signal to be output is schematically shown, the sixth
It looks like Figure (b). In the figure, A to J indicated by dotted lines
Represents one pixel of the input image signal, and one pixel of the output image signal corresponds to the upper left shaded area. According to the present invention, when the input image signal obtained as shown in FIG. 6 (a) is subjected to interpolation processing and output with high resolution as shown in FIG. 6 (b), the image quality is improved. I have to.

The two-stage shift registers 15 are arranged adjacent to each other in the main scanning direction.
The image signals D _n and D _n-1 for pixels are temporarily stored. For convenience of explanation, it is assumed that D _n-1 is an image signal corresponding to the pixel A (hereinafter referred to as A) and D _n is an image signal corresponding to the pixel B (hereinafter referred to as B). These image signals are input to each input terminal of the data selector 17 as they are or after being subjected to interpolation calculation by the adder 16.
Now, since N = 4, A is directly input to the input terminal 0, (3A + B) / 4 is input to the input terminal 1, (2A + 2B) / 4 is input to the input terminal 2, and again. (A + 3B) / 4 is input to the terminal 3.

The data selector 17 sequentially selects and outputs these input signals according to the count value of the N-ary counter 18. The N-ary counter 18 is configured to be reset by the input main scanning clock signal CK _im which is the clock signal of the shift register 15 and count the output main scanning clock signal CK _om having a frequency four times as high as this clock signal. There is. In this way, while the shift register 15 temporarily stores A and B (that is, the time corresponding to the time for reading the pixel C in FIG. 6A during one input main scan). , From the data selector 17, A, (3A +
B) / 4, (2A + 2B) / 4, (A + 3B) / 4 are sequentially output. Top row and 5 in Figure 6 (c)
The row shows the image signal interpolated in the main scanning direction in this way.

The image data for which the interpolation in the main scanning direction has been completed is alternately written in the first and second line memories 19 and 20 for each one scanning line under the control of the memory control 27. FIG. 5 (e) shows an image signal group output from the data selector 17 and interpolated in the main scanning direction. L3, L4 and L5 are the third, fourth and fifth images, respectively.
This represents the signal of the line (scanning line). The memory control 27 uses the write / read control signals WR-1 and WR-2 (write instruction when low) shown in FIGS. 5 (j) and (k) and the address clock shown in (l) and (m). The signals Addr-1 and Addr-2 are given to the first and second line memories 19 and 20, respectively, and in response to this, (f),
As shown in (g), image signal groups L3, L
4, L5 are alternately written into the first and second line memories 19 and 20 for each scanning line. L3W and L5W in FIG. 5 (f) represent image signal groups L3 and L5 written in the first line memory 19, and L4W in (g) is also L4W.
Is the image signal group L4 written in the second line memory 20.
Is represented.

In this way, the first and second line memories 19, 20
Image signal groups L3, L4, L for each one scanning line written in
5 is a write / read control signal WR- of FIGS. 5 (j) and 5 (k).
1, in response to the high level of WR-2, they are sequentially read out repeatedly in accordance with the address clocks of (l) and (m). 1 each
The writing / reading time for one time (one scanning line) is defined by the output sub-scanning clock signal CK _os of FIG. 5 (c).
The memory control 27 uses the clock signal CK _os to write / read the control signal W shown in FIGS. 5 (j) and 5 (k).
Address clock A of R-1, WR-2 and (l), (m)
ddr-1 and Addr-2 are created and given to the first and second line memories, respectively.

L1R, L3R, L5R, L2R, and L of FIGS. 5 (f) and (g)
4R represents the image signal groups L1, L3, L5, L2, and L4 read repeatedly in this way. In this embodiment, the same image signal group is repeatedly read 7 times. For example, in the L3R data portion of FIG. 5 (f), the image signal group L3 for one scanning line is repeated 7 times consecutively. It has been read.

In this way, the first and second line memories 19, 20
The image signals read out from are distributed by the tri-state buffer amplifiers 21 to 24 acting as gates, and are led out to the read lines 25 and 26, respectively. The memory control 27 sends the memory alignment signal of FIG. 5 (n) to each tristate buffer amplifier 21.
To 24 to control the distribution of this image signal. For example, during the period T1 shown in the figure, a low memory alignment signal is applied to the tri-state buffer amplifier 21,
24 becomes an open state. Therefore, the image signal group L3 read from the first line memory 19 is led out onto the read line 26 via the tri-state buffer amplifier 22, while the image signal group L2 (before L3) read from the second line memory 20. (The image signal scanned and written in) is led out onto the read line 25 via the tri-state buffer amplifier 23. In this manner, the timing control is performed by switching so that the image signal of the one that is previously scanned and written is always led out onto the read line 25.

Now, the sixth one corresponds to the image signal group L2 for one scanning line.
Signals A, (3A + B) / 4, ... on the first line in FIG.
Assuming that the signals D, (3D + E) / 4, ... Of the fifth line also correspond to the image signal group L3 for one scanning line, the subsequent operation is performed during the period T1 in FIG. explain. The M-ary counter 30 _{is configured} to be reset by the input sub-scanning clock signal CK _is shown in FIG. 5A and count ( _upcount in this case) the output sub-scanning clock signal CK _os shown in FIG. 5C. There is. Since M = 4 in this embodiment, the output of the M-ary counter 30 is the fifth
As shown in FIG. _7H , 0, 1, 2, and 3 are repeated in synchronization with the output sub-scanning clock CK _os .

When the output counter value of the M-ary counter 30 is 0, the data selector 29 selects and outputs the signal applied to the input terminal 0. Now, to the input terminal 0, the image signal group L2 for one scanning line read out from the second line memory 20 and derived on the read line 25 as described above.
That is, A, (3A + B) / 4, ... Are given,
Therefore, the data selector 29 sequentially outputs the image signals A for one scanning line, (3A + B) / 4, .... This is shown as L2 in FIG. 5 (i), which illustrates the output of the data selector 29.
The output speed is determined according to the read speed of each image signal from the second line memory 20, but as shown in FIG. 5 so that each image signal is output in synchronization with the output main scanning clock signal CK _om . The address clock Addr-2 of m) may be defined. This also applies to the case of reading from the first line memory 19. Thus, the image signal of the first line in FIG. 6 (c) is output during the period t1 in FIG.

Next, when the output counter value of the M-ary counter 30 is 1,
The data selector 29 selects and outputs the signal given to the input terminal 1, that is, the output signal of the adder 28-1. Now, M = 4, and the signal on the read line 25 is L2 (that is, A, (3A + B) / 4, ...), and the signal on the read line 26 is L3 (that is, D, (3D +
E) / 4, ...), the adder 28-1 is configured to add a pair of image signals (for example, A and D, (3A + B) / 4) to the input terminals in synchronization with the output main scanning clock signal _CKom. And (3D + E) / 4) for each (3L2 + L3) / 4
Is calculated and output. The result of this calculation is shown in FIG.
(3A + D) / 4, as shown in the second line of (c)
(9A + 3B + 3D + E) / 16, ... And these interpolated image signals for one scanning line are output from the data selector 29 in the period t2 in FIG. This is shown as (3L2 + L3) / 4 in FIG. 5 (i).

Similarly, during the period t3 in FIG. 5, the operation (2L2 + 2L3) / 4 corresponding to the third line in FIG. 6 (c) is performed by the adder 28-2, and the result is M-ary. In response to the count value 2 of the counter 30, the data selector 29
Then, in the subsequent t4 period, the operation (L2 + 3L3) / 4 corresponding to the fourth line in FIG. 6 (c) is added by the adder 2
8-3 and the result is the M-ary counter 30
Is output from the data selector 29 in response to the count value 3 of. In this way, during the time T1 (corresponding to the unit input sub-scanning period and the unit input accumulation time of the CCD) of FIG. 5,
The first to fourth lines of FIG. 6 (c) are sequentially output in synchronization with the output sub-scanning clock signal CK _os .

In the next T2 period, the phase of the memory alignment signal of FIG. 5 (n) is reversed, so that the read line 25 has the image signal group L3 of the first line memory, that is, D, (3D +
E) / 4, ... Will be derived. Then, in the first t5 period of the T2 period, this image signal responds to the count value 0 of the M-ary counter 30 and the data selector 2
It is output from 9. In this way, the first of FIG. 6 (c)
~ The fifth line is output following the fourth line.

During the period t5, the input image signal group L4 for the next one scanning line from the CCD 13 is written in the second line memory 20. This image signal group L4 has the following t6.
Is read out on the read line 26 in the period from ~ t8,
Then, in the same manner as described above, interpolation calculation in the sub-scanning direction is performed by each adder 28, and the 6th to 8th lines in FIG. 6C are sequentially output from the data selector 29.

As described above, when the input image signal obtained with the resolution of FIG. 6 (a) is output with the resolution of FIG. 6 (b), the interpolation calculation of the image signal in the main scanning direction and the sub-scanning direction Then, an image signal as shown in FIG. 6 (c) is obtained.

FIG. 7 shows an example of the input image signal (a) and the output image signal (b) when such interpolation is performed. In the figure, the horizontal axis represents the pitch in the main scanning direction or the sub scanning direction, and the vertical axis represents the density value, for example. It can be clearly understood that the image quality is smoothed and improved, although the figure shows that the interpolation of 4 times is performed (that is, the ratio of the input resolution and the output resolution is 1: 4).

FIG. 8 is a block diagram showing another embodiment of the interpolation circuit. This interpolation circuit basically performs the same function as that of the interpolation circuit of FIG. 1, but unlike the interpolation circuit of FIG. 1, first performs interpolation in the sub-scanning direction and then interpolation in the main scanning direction. Is configured to do. That is, the interpolation circuit of FIG. 1 and the interpolation circuit of FIG. 8 are different only in the order of interpolation, and the configuration and operation of the functional portion for performing the respective interpolation are the same in both interpolation circuits. Therefore, only the interpolation order will be described below, and the description of the other parts will be replaced with the description of FIG. 1 described above.

In the interpolation circuit of FIG. 8, the first and second line memories 19 'and 20' alternately store the input image signal from the A / D converter 14 for each one scanning line. For example, now, the first line A, B, C, ... Of FIG. 6 (a) is written in the first line memory 19 ', and the second line D, E, F, ...
Is written. At this time, the adder 28
The interpolation calculation in the sub-scanning direction is performed by the data selector 29. From the output terminal of the data selector 29, A, B, ..., (3A shown in part of the first to fourth lines in FIG.
+ D) / 4, (3B + E) / 4, ..., (2A + 2D) /
4, (2B + 2E) / 4, ..., and (A + 3D) /
, (B + 3E) / 4, ... Are sequentially output for each scanning line.

Next, the two-stage shift register 15 sequentially and temporarily stores two of the image signals for one scanning line that are sequentially output as described above. For example, if the above A and B are stored, the adder 16 performs interpolation calculation in the main scanning direction, and the data selector 17
From the output terminal of A, (3A + B) / 4, (2A + 2
B) / 4, and (A + 3B) / 4 are sequentially output.
Then, B and C are stored in the shift register 15, and B, (3B + C) / 4, which are the continuations of the first line, are stored.
(2B + 2C) / 4 and (B + 3C) / 4 are sequentially output from the shift register 15. In this way, the interpolation in the main scanning direction is performed after the interpolation in the sub scanning direction,
An image signal similar to that of the interpolation circuit of FIG. 1 is output.

By the way, in the interpolation circuit of FIG. 1, the first and second line memories 19 and 20 are required to have a capacity enough to store one scanning line of the image signal after being interpolated in the main scanning direction. However, in the interpolation circuit of FIG. 8, the first and second line memories 19 'and 20' need only be able to store the image signal before interpolation for one scanning line, so the storage capacity can be reduced accordingly and it is economical. The advantage is that

In the above embodiment, the case where the input / output resolution ratios in the main scanning direction and the sub-scanning direction are equal (M = N = 4) has been described, but these ratios may be different.

Further, in the above embodiment, the case where only one CCD is used has been described. However, even when a plurality of CCDs are used, the method of the present invention can be applied to further increase the input resolution. Needless to say. Further, the method of the present invention can be applied to the processing of a line drawing original, in which case the input image signal is first processed in continuous tone by the method of the present invention, and then the binarization processing is performed. You can do it.

Finally, an example of a specific design when the input resolution is 1/4 of the output resolution will be shown below.

1. Input main scanning resolution Approx. 14.8 line / mm 2. Input sub-scanning resolution approx. 14.8 line / mm 3. CCD accumulation time 20 ms 4. 4. Number of CCD elements Effective number of 4384 elements (use one of 5000 elements) 5. CCD transfer clock frequency Approx. 880 KHz 6. Output main scanning resolution about 59.1 line / mm 7. Output sub-scan resolution Approx. 59.1 line / mm 8.1 Scan line recording time 5 ms 9. A4 size processing time about 1 min (62 sec) Since the required A / D conversion speed at the above CCD transfer clock frequency of 880 KHz is about 1.13 μs or less, one commercially available CCD (5000 elements) and A / D Converter (1
It becomes possible to manufacture an image scanning recording apparatus for plate making by using one (2 bits, conversion speed of about 1 μs).

The CCD accumulation time is 20 ms (T1, T2 in FIG. 5).
If the number of CCD elements is 4384, the CC
If the D transfer clock frequency is about 220 KHz, data can be read out within the accumulation time, but in the embodiment,
As shown in Fig. 5 (b), the data for one scanning line is read out in 1/4 of the accumulation time, so about 880K
A CCD transfer clock frequency of Hz is required. When it is desired to match the accumulation time with the readout time and utilize a slower transfer clock frequency, an extra line memory for storing image signals for one scanning line is provided, and these are circulated and sequentially It suffices to store the input image signal for each scanning line. With this configuration, it is possible to perform interpolation in the sub-scanning direction on the basis of the image signal for two scanning lines previously input while the image signal for one scanning line is input. .

(Effects of the Invention) As described above, according to the present invention, the output resolution higher than the input resolution of the one-dimensional photoelectric conversion element array is obtained by adding the interpolation processing to the input image signal obtained from the one-dimensional photoelectric conversion element array. First, a high-resolution image for platemaking is recorded using a commercially available CCD with a small number of elements and a 12-bit A / D converter with a relatively slow conversion speed. It becomes possible.

Second, it is possible to form a high-resolution image scanning recording apparatus for platemaking at a low cost with a small number of constituent parts.

Thirdly, if a plurality of commercially available CCDs with a small number of elements are used for plate making, it is difficult to adjust the positions of the CCDs and the optical system. Can this adjustment work be omitted altogether? , Or less.

Fourth, the image quality is smooth because the image signal having a coarse input resolution is interpolated. That is, it is possible to effectively prevent a situation in which, after some pixels having a certain gradation are consecutively moved to a pixel having another gradation, a gradation change in a reproduced image becomes abrupt. You can

Further, the method of the interpolation processing is the first method performed in the main scanning direction.
Since the interpolation processing and the second interpolation processing performed in the sub-scanning direction are clearly distinguished, and the interpolation processing in either direction is performed preferentially, the interpolation processing in the other direction is performed. Enables a large number of two-dimensional interpolation processes with a simple circuit required for one-dimensional interpolation in each of the main scanning direction and the sub-scanning direction.

Further, during the second interpolation processing, the image signal groups for one scanning line are respectively stored in the two line storage units, and while the first image signal group stored in one line storage unit is being output. , The second image signal is stored in the other line storage means, and the first image signal is stored in the first and second line storage means.
And the second image signal group is output to obtain the interpolation image signal group for the scanning line corresponding to the output resolution, and then the second image signal group is switched to the first image signal group. Thus, interpolation processing in the sub-scanning direction can be continuously performed.

As a result, the circuit for interpolation processing can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an interpolation circuit, FIG. 2 is a block diagram showing an example of a plate-making scanner to which the present invention is applied, and FIGS. 3 and 4 are conceptual diagrams showing an image input optical system. 5 and 5 are timing charts showing the operation of the interpolation circuit of FIG. 1, FIG. 6 is a schematic diagram of input / output image signals, and FIG.
FIG. 8 is a diagram showing an example of image signals before and after interpolation,
The figure is a block diagram showing another embodiment of the interpolation circuit. 13 ... CCD line sensor 14 ... A / D converter 15 ... Shift register 16, 28 ... Adder 17, 29 ... Data selector 18 ... N-ary counter 19, 19 ', 20, 20' ... Line memory 21-24 ... Tri-state buffer amplifier 27 ... Memory control 30 ... M-ary counter

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-58-84358 (JP, A) JP-A-59-35270 (JP, A) JP-A-60-47566 (JP, A)

Claims (2)

[Claims] 1. An input image signal obtained by photoelectrically scanning an original image with a predetermined input resolution in a main scanning direction and a sub-scanning direction by a one-dimensional photoelectric conversion element array is subjected to A / D conversion and interpolation processing to the input image signal. In the method of processing an image signal to obtain an output resolution higher than the input resolution, the interpolation processing (a) sequentially stores image signals of two pixels adjacent in the main scanning direction, and A first interpolation process for interpolating the signal in the main scanning direction based on the output resolution; and (b) a first image signal group and a second image signal group which are adjacent in the sub-scanning direction are sequentially sequentially scanned for each scanning line segment. A process of storing in the first and second line storage means and interpolating the image signal group in the sub-scanning direction based on the output resolution, (b-1) the first line storage means stored in one of the line storage means. Output one image signal group and Storing the second image signal group in the other line storage means, and (b-2) outputting the first and second image signal groups stored in the first and second line storage means. A step of obtaining an interpolated image signal group corresponding to the output resolution and sequentially outputting each interpolated image signal group, (b-3) switching the second image signal group to the first image signal group A second interpolation process including the step of executing one of the first and second interpolation processes, and performing the other interpolation process on the image signal obtained by the interpolation process. A method of processing an image signal, the method comprising: 2. A one-dimensional photoelectric conversion element array for photoelectrically scanning an original image in a main scanning direction and a sub-scanning direction with a predetermined input resolution, and an input image signal from the one-dimensional photoelectric conversion element array is converted into a digital signal. In an image signal processing device having an A / D converter and an interpolating means for interpolating the digital signal thereof in the main scanning direction and the sub-scanning direction, and obtaining an output resolution higher than the input resolution, the interpolating means comprises: (a-1) storage means for sequentially storing image signals of two pixels adjacent to each other in the main scanning direction; and (a-2) image signal stored in this storage means, based on the output resolution, main scanning First computing means for computing an image signal to be interpolated in the direction, and (b-1) a first image signal group and a second image signal group which are adjacent to each other in the sub-scanning direction. First and second stored for each scanning line segment
Line storage means, and (b-2) control means for outputting the first image signal group stored in one line storage means and storing the second image signal group in the other line storage means in synchronization with it. And (b-3) an interpolation image signal group of scanning line segments corresponding to the output resolution is calculated based on the first and second image signal groups stored in the first and second line storage means. Second calculation means for sequentially outputting each of the interpolated image signal groups, and (b-4) switching means for switching the second image signal group to the first image signal group after outputting the interpolated image signal group, A second interpolating means comprising: an interpolating means for executing the processing by any one of the first and second interpolating means, and for the image signal obtained by the interpolating processing, the other interpolating means. Image signal characterized by executing processing by Of the processing device.