JPH061898B2 - Sequential circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequential circuit composed of an ECL circuit, and more particularly to improving α ray resistance in such a circuit.

[Conventional technology]

As a means for improving the decrease in the α ray resistance in a highly integrated ECL sequential circuit, for example, Japanese Patent Laid-Open No. 60-14261.
No. 9, JP-A-60-143019,
E as shown in the circuit configuration diagram of FIG. 4 and the logic diagram of FIG.
CL sequential circuits have been proposed. In the figure, an OR circuit 1 is formed by a current switching circuit composed of transistors Q ₁ and Q ₂ and an emitter follower transistor Q _3, and an OR circuit 1 is composed of a current switching circuit composed of transistors Q ₄ and Q ₅ and an emitter follower transistor Q _6. 2 is formed, and is ORed by the current switching circuit including the transistors Q ₇ , Q ₈ and Q ₉ and the emitter follower transistor Q _10.
The circuit 3 is formed. W _A (thick line in Fig. 4)
Is a wide AND of the output of the OR gate 2 and the output of the OR gate 3. Further, D is a data input signal, T is a clock input signal, Y ₁ is a positive output signal, I _{1 to} I ₃ are constant current sources, V _CC and V _EE are power supply voltages, and V _REF is a reference voltage.

Next, the operation will be described. In the sequential circuits of FIGS. 4 and 5, when the clock signal T is "0" in the holding state,
Data is held by feeding back the positive output signal Y ₁ to the OR gate 3. That is, at this time, the gate 3 is through for the signal Y ₁ . When holding the data "1" and α rays to the collector node of the wired-AND transistor Q is connected to a line of (W _{A) 5} or Q ₉ hits, electrons are generated, "1"
The amount of charge held in the state decreases, and the potential decreases. Since this drop is charged through the resistors R ₁ and R ₂ , it becomes a spike shape with a pulse width of several hundred picoseconds, but this becomes noise and is fed back to the gate 3, so that the held data is The contents will be reversed.

Therefore, in the above-mentioned Japanese Patent Application Laid-Open No. 60-142619, in order to increase the holding current, the constant current sources I ₁ , I ₂ , I
₃ is changed to increase the current to improve the α-ray resistance. Further, in JP-A-60-143019, the amount of retained charge is increased by adding the capacitors C _{1 to} C ₄ to improve the α-ray resistance.

[Problems to be solved by the invention]

Since the conventional ECL sequential circuit improves the α-ray resistance,
Since it is configured as described above, there is a problem that power consumption increases as the amount of current increases, and switching speed decreases due to the addition of capacitance.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a sequential circuit capable of improving α-ray resistance without increasing power consumption and reducing switching speed. And

[Means for solving problems]

A sequential circuit according to the present invention includes a data input terminal to which a data signal which is a binarized signal is input, a clock signal having a first level indicating activation and a second level indicating deactivation. A clock input terminal, a positive output terminal, an inverting output terminal, a first input node connected to the clock input terminal, a second input node connected to the inverting output terminal, and an output node. When the clock signal input to the first input node is at the first level, a signal indicating activation of a predetermined level is output to the output node regardless of the signal input to the second input node. , When the clock signal input to the first input node is at the second level,
A data stabilizing circuit that outputs to the output node a signal corresponding to the signal that appears at the inverting output terminal that is input to the input node of, a first input node that is connected to the data input terminal,
An output from the data stabilizing circuit, which has a second input node connected to the output node of the data stabilizing circuit, a positive output node, and an inverting output node, is input to the second input node. When the signal has a predetermined level, which is a signal indicating activation, a signal based on the data signal input to the first input node is output to the positive output node and an inverted signal of the signal appearing at the positive output node at the inverted output node. Is output and the output from the data stabilizing circuit input to the second input node is a stabilizing signal having a level different from a predetermined level which is a signal indicating activation, and is input to the first input node. Irrespective of the data signal to be output, a signal corresponding to the stabilization signal input to the second input node is output to the positive output node and an inverted signal of the signal appearing on the positive output node is output. A data input circuit for outputting to a node, a first input node connected to the clock input terminal, a second input node connected to an output node of the data stabilizing circuit, and a positive output terminal A clock signal input to the first input node has a first input node, a positive output node, and an inverting output node.
At the level of, the signal based on the first level of the clock signal input to the first input node is output to the positive output node regardless of the signals input to the second and third input nodes. When the inverted signal of the signal appearing at the positive output node is output to the inverting output node and the clock signal input to the first input node is at the second level, the data stabilization input to the second input node is stabilized. A signal based on the output from the circuit and the signal appearing at the positive output terminal input to the third input node is output to the output node and the inverted signal of the signal appearing at the positive output node is output to the inverting output node. The data feedback circuit receives the signal appearing at the positive and inverted output nodes of the data input circuit and the signal appearing at the positive and inverted output nodes of the data feedback circuit, and returns the data feedback circuit. When the signal appearing at the positive output node of the circuit is a signal based on the first level of the clock signal input to the clock input terminal, the signal appearing at the positive output node of the data input circuit is set to the positive output terminal. And the signal appearing at the inverting output node of the data input circuit is output to the inverting output terminal, and the signal appearing at the positive output node of the data feedback circuit is a signal based on the output from the data stabilizing circuit. Then, a selection circuit for outputting the signal appearing at the positive output node of the data feedback circuit to the positive output terminal and outputting the signal appearing at the inverting output node of the data feedback circuit to the inverting output terminal is provided. It is configured.

[Operation] In the present invention, the output from the data stabilizing circuit is input to the second input node of the data input circuit in which the data signal is input to the first input node. The activation and stabilization based on the clock signal can be performed by the data stabilization circuit, and the capacity at the output node of the data stabilization circuit can be increased, so that the output of the data stabilization circuit, particularly the H level potential is output. It is possible to suppress the change from the H level to the L level due to the α ray during the operation.

〔Example〕

FIG. 1 is a circuit configuration diagram showing an embodiment of an ECL sequential circuit according to the present invention, and FIG. 2 is a logic diagram thereof. In the figure, a 2-input OR / NOR gate 11 for data input is formed by a current switching circuit composed of transistors Q ₁₁ , Q ₁₂ , and Q ₁₃ and an emitter follower transistor Q _14, and is composed of transistors Q ₁₅ , Q ₁₆ , and Q ₁₇ . The two-input NOR gate 12 for data stabilization is formed by the current switching circuit and the emitter follower transistor Q _18, and the current switching circuit including the transistors Q ₁₉ , Q ₂₀ , Q ₂₁ , and Q ₂₂ and the emitter follower transistor Q ₂₃ , A three-input OR / NOR gate 13 for clock input and data feedback is formed by Q ₂₄ .

W _A (thick line portion in FIG. 1) is a wire AND of the OR output (positive output) of the 2-input OR / NOR gate 11 and the OR output (positive output) of the 3-input OR / NOR gate 13, and W ₀ is 2
NOR output of input OR / NOR gate 11 (inverted output)
And the NOR output (inverted output) of the 3-input OR / NOR gate 13 is a wired OR. The output of the wired AND (W _A ) is the positive output signal Y ₁ of the sequential circuit of this embodiment,
It is fed back to the first input of the 3-input OR / NOR gate 13 for data feedback. The output of the wired OR (W ₀ ) is the inverted output signal Y ₀ of the sequential circuit of this embodiment, and is fed back to one input of the 2-input NOR gate 12 for data stabilization. The clock input signal T is applied to the other input of the 2-input NOR gate 12, and its output is one input of the 2-input OR / NOR gate 11 and the 3-input OR / NOR gate 1.
3 to the third input. The data input signal D and the clock input signal T are applied to the other input of the 2-input OR / NOR gate 11 and the second input of the 3-input OR / NOR gate 13, respectively. I _{11 to} I ₁₃ are constant current sources, V
_CC and V _EE are power supply voltages, and V _REF is a reference voltage.

Next, the operation will be described. The sequential circuit shown in FIGS. 1 and 2 is similar to the conventional sequential circuit shown in FIGS. 4 and 5 in that the state where the clock signal T is "0" is held and the positive output signal Y ₁ is input to three inputs. The data is retained by returning to the OR / NOR gate 13. However, unlike the conventional method, when holding the data "1", the data return 3
Input OR / NOR gate 13 is not through for signal Y ₁ . That is, the positive output signal Y ₁ is “1”.
At this time, the inverted output signal Y ₀ is “0”, and the inverted output signal Y ₀ of “0” is N when the data is held (T = “0”).
It is inverted to "1" by the OR gate 12 and three-input OR / N
Since it is given as the third input signal of the OR gate 13,
This is because the 3-input OR / NOR gate 13 will be closed (the output becomes independent of the operation of the first and second inputs).

Now, in this state, α is applied to the collector node of the transistor Q ₁₁ or Q ₁₉ connected to the line W _A of the wire AND.
It is assumed that the line hits and spike noise due to the potential drop occurs. At this time, this spike noise is 3 inputs OR / NO
It is fed back to the first input of the R gate 13,
Since the third input of the NOR gate 13 is "1" as described above and the gate is closed, the content of the held data "1" does not change. The output "1" of the NOR gate 12 is also input to the NOR gate 11 and the NOR gate 11 is closed with respect to the data signal D. Therefore, the change in the signal D does not change the data holding content.

The above has described the case where the data “1” is held, but the case where the data “0” is held is described next. At this time, since the inverted output signal Y ₀ is “1”, N
The output of the OR gate 12 becomes "0". Therefore, the 2-input OR / NOR gate 11 is through for the data signal D, and the 3-input OR / NOR gate 13 is through for the feedback signal (positive output signal Y ₁ ). However since performing AND operation by the wired-AND (W _A), wired-AND unless the feedback signal is "0"
(W _A ) data, that is, the positive output signal Y ₁ is the data signal D
Since it is irrelevant to the fluctuation of the data, the data "0" is held.

Now, in this state, it is assumed that the collector node of the transistor Q ₂₀ , Q _21, or Q ₂₂ connected to the line W ₀ of the wire-add OR is hit by the α line, so that the spike noise of the potential drop is generated. At this time, the output of the NOR gate 12 tries to invert from "0" to "1", but this state is 2
Input OR / NOR gate 11 and 3-input OR / NOR
Since the gate 13 will be closed, the stored contents will not change.

When the clock signal becomes "1", the output of the NOR gate 12 becomes "0" and the 2-input OR / NOR gate 11 becomes through for the data signal D. On the other hand, 3 inputs OR / N
In the OR gate 13, the second input clock signal T is "1".
Therefore, it is closed to the feedback signal, which allows rewriting of the data holding content.

Although the data input and the clock input are both one in the above embodiment, they may be plural. FIG. 3 shows a logic diagram of an embodiment when there are two data inputs and two clock inputs. In the figure, the 3-input OR / NOR gate 14 for receiving the data input signals D ₁ and ₂ is the second
The 3-input NOR gate 15 and the 4-input OR / NOR gate 16 that perform the same function as the 2-input OR / NOR gate 11 in the figure and receive the clock input signals T ₁ and T ₂ are respectively the 2-input NOR gates in FIG. 12 and 3 input OR
/ NOR Performs the same function as the NOR gate 13. Also in this embodiment, the same effect as that of the above embodiment is obtained.

〔The invention's effect〕

As described above, according to the sequential circuit of the present invention, the output from the data stabilizing circuit is input to the second input node of the data input circuit in which the data signal is input to the first input node. Therefore, activation and stabilization based on the clock signal of the data input circuit can be performed by the data stabilization circuit, the number of circuits can be reduced without providing a special circuit for that, and at the output node of the data stabilization circuit. Since the capacity can be increased, there is an effect that a change from H level to L level due to α rays can be suppressed when the output of the data stabilizing circuit, particularly, the H level potential is output.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 2 is a logic diagram thereof, FIG. 3 is a logic diagram of another embodiment of the present invention, and FIG. 4 shows a conventional ECL sequential circuit. Circuit diagram,
FIG. 5 is a logical diagram thereof. In the figure, Y ₁ is a positive output signal, Y ₀ is an inverted output signal, T
Is a clock signal, 12 is a 2-input NOR gate, and 13 is 3
Input OR / NOR gate. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A data input terminal to which a data signal which is a binarized signal is input, and a clock signal having a first level indicating activation and a second level indicating deactivation is input. A clock input terminal, a positive output terminal, an inverting output terminal, a first input node connected to the clock input terminal, a second input node connected to the inverting output terminal, and an output node, When the clock signal input to the first input node is at the first level, a signal indicating activation of a predetermined level is output to the output node regardless of the signal input to the second input node, The second level when the clock signal input to the input node of the
A data stabilizing circuit that outputs to the output node a signal corresponding to the signal that appears at the inverting output terminal that is input to the input node of, a first input node that is connected to the data input terminal,
An output from the data stabilizing circuit, which has a second input node connected to the output node of the data stabilizing circuit, a positive output node, and an inverting output node, is input to the second input node. When the signal has a predetermined level, which is a signal indicating activation, a signal based on the data signal input to the first input node is output to the positive output node and an inverted signal of the signal appearing at the positive output node at the inverted output node. Is output and the output from the data stabilizing circuit input to the second input node is a stabilizing signal having a level different from a predetermined level which is a signal indicating activation, and is input to the first input node. Irrespective of the data signal to be output, a signal corresponding to the stabilization signal input to the second input node is output to the positive output node and an inverted signal of the signal appearing on the positive output node is output. A data input circuit for outputting to a node, a first input node connected to the clock input terminal, a second input node connected to an output node of the data stabilizing circuit, and a positive output terminal The clock signal having a third input node, a positive output node, and an inverting output node, the clock signal input to the first input node is the first
At the level of, the signal based on the first level of the clock signal input to the first input node is output to the positive output node regardless of the signals input to the second and third input nodes. When the inverted signal of the signal appearing at the positive output node is output to the inverting output node and the clock signal input to the first input node is at the second level, the data stabilization input to the second input node is stabilized. A signal based on the output from the circuit and the signal appearing at the positive output terminal input to the third input node is output to the positive output node and the inverted signal of the signal appearing at the positive output node is output to the inverting output node. A data feedback circuit for receiving a signal appearing at the positive and inverting output nodes of the data input circuit and a signal appearing at the positive and inverting output nodes of the data feedback circuit. When the signal appearing at the positive output node of the return circuit is a signal based on the first level of the clock signal input to the clock input terminal, the signal appearing at the positive output node of the data input circuit is output as the positive output. The signal appearing at the inverting output terminal of the data input circuit and the signal appearing at the positive output node of the data feedback circuit become the stabilizing signal from the data stabilizing circuit. A selection circuit for outputting the signal appearing at the positive output node of the data feedback circuit to the positive output terminal and outputting the signal appearing at the inverting output node of the data feedback circuit to the inverting output terminal. Sequential circuit with.