JPH0619373B2 - Trigger jitter detection circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a trigger jitter detection circuit,
More specifically, it relates to detection of trigger jitter in waveform display by random sampling.

(Prior Art) In displaying and observing an input repetitive waveform, a signal A is randomly sampled and converted into digital data ◯, Δ, ... As shown in FIG. Time t ₁ t ₂ from the trigger is applied until the data ◯, Δ, ... Is sampled,
... are also measured, and the waveform data ◯, Δ, ... Stored in this waveform memory are arranged according to the relative time t ₁ t ₂ from the trigger point, as shown in FIG. As shown in c), the waveform signal A is reproduced and displayed.

By the way, in outputting the trigger pulse in such random sampling, for example, as shown in FIG. 9, the trigger control signal S is applied to the data terminal of the flip-flop.
₁ is added and an output signal S ₂ of a trigger comparator (not shown) for repeatedly comparing the input signal and the trigger level is added to the clock terminal, and the trigger control signal S ₁ is converted to the comparator output signal S ₂ as shown in FIG. It is performed by latching and outputting as a trigger pulse S ₃ . Then, the rising point of this trigger pulse S ₃ is used as the trigger point.

However, since the trigger control signal S ₁ and the comparator output signal S ₂ are completely asynchronous, as shown in FIG. 11, the rising edge of the trigger control signal S _{1 and} the rising edge of the comparator output signal S ₂ may conflict with each other in terms of time. The output signal S ₃ of the flip-flop may be unstable and metastable. The rising of the output signal S ₃ of the flip-flop in such a metastable state becomes jitter.

(Problems to be solved by the invention) However, when the time from the trigger point to the sampling pulse is measured using a signal accompanied by such a jitter, the accurate time cannot be measured, and the waveform is reconstructed. In this case, a data error as shown in FIG. 12 will occur.

The present invention focuses on such a point, and an object thereof is to provide a trigger jitter detection circuit capable of detecting the occurrence of trigger jitter with a relatively simple configuration.

(Means for Solving Problems) A trigger jitter detection circuit according to the present invention includes a sine wave oscillator, a sampling pulse generation circuit which outputs a sampling pulse synchronized with an output signal of the sine wave oscillator, a trigger pulse input signal and a trigger. A trigger control circuit that selectively outputs a trigger pulse according to a control signal, and two pulses that have a time difference corresponding to the phase difference of 90 ° of the sine wave signal according to the trigger pulse output from the trigger control circuit. And a amplitude Asi of the sine wave signal at the time when each pulse is output according to the output pulse of the double pulse generation circuit.
A / which converts nωt and Acosωt into digital signals X and Y
D converter and the sum of squares A ² (= X) of digital signals X and Y output from this A / D converter during normal operation without trigger jitter in advance.
² + Y ² ), and an arithmetic control unit is provided for comparing the sum of squares A ² at the time of normal operation and the measurement result at each measurement to determine the presence or absence of trigger jitter.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.
In FIG. 1, reference numeral 1 is a sine wave oscillator, the output signal of which is applied to a sampling pulse generating circuit 2 and an A / D converter 3. The sampling pulse generation circuit 2 outputs a sampling pulse in synchronization with the output signal of the sine wave oscillator 1, and uses, for example, a comparator for comparing the sine wave signal and zero potential as shown in FIG. This sampling pulse repeatedly samples an input signal and outputs waveform data.
A / D converter. 4 is a trigger control circuit,
The trigger pulse S ₃ is selectively output according to the trigger pulse input signal S ₂ and the trigger control signal S ₁ . As the trigger pulse input signal S _2, the other output signal of the trigger comparator, as the dummy output signal for calibration generated internally is also optionally added to obtain the reference output data in a normal operating state It is configured. Reference numeral 5 denotes a double pulse generation circuit, which outputs two pulses having a time difference T corresponding to the phase difference of 90 ° of the sine wave signal in accordance with the trigger pulse output from the trigger control circuit 4. Here, the pulse width is set to be an abnormal pulse when the trigger control circuit 4 is in the metastable state. The output pulse S _{4 of} this double pulse generation circuit 5
Is added to the A / D converter 3. The A / D converter 3 converts the amplitudes A sin ωt and A cos ωt of the sine wave signal at the time when each pulse is output according to the double pulse S ₄ added from the double pulse generation circuit 5 into digital signals X and Y, and an arithmetic control unit Output to 6. FIG. 3 is a circuit diagram showing a specific example of such a double pulse generating circuit 5.
In the figure, 7 is a pulse shaping circuit for shaping the output signal S ₃ of the trigger control circuit 4 into a trigger pulse S ₃ ′ having a predetermined pulse width. Reference numeral 8 is an OR gate. A shaping trigger pulse S ₃ ′ is directly applied to one input terminal and a shaping trigger pulse S ₃ ′ is applied to the other input terminal of a delay circuit 10 which gives a phase difference of a buffer amplifier 9 and 90 °. And a buffer amplifier 11 via a series circuit. The arithmetic control unit 6 preliminarily sets A / A during normal operation without trigger jitter.
The sum of squares A ² (= X ² + Y ² ) of the digital signals X and Y output from the D converter 3 is obtained, and the sum of squares A ² at the time of normal operation is compared with the measurement result at each measurement to generate the trigger jitter. Determine whether or not

The operation of the apparatus thus configured will be described with reference to the timing chart of FIG.

In the figure, (a) shows the trigger pulse S ₃ output from the trigger control circuit 4, (b) shows the shaping trigger pulse S ₃ ′ output from the pulse shaping circuit 7, and (c) shows the double pulse generation. Double pulse S output from circuit 5
₄ and (d) shows a sine wave signal output from the sine wave oscillator 1.

Trigger control signal S ₁ and trigger comparator output signal S ₂
The output data of the A / D converter 3 sampled by the first pulse of the double pulse S ₄ that is output in a normal state without trigger jitter and whose time relationship is not metastable is X, and Assuming that the output data of the A / D converter 3 sampled by the pulse is Y, X = Asinωt Y = Acosωt, where A ² = X ² + Y ² is satisfied.

On the other hand, in the state where the time relationship between the trigger control signal S ₁ and the trigger comparator output signal S ₂ causes meta-stable trigger jitter, assuming that the double pulse generation circuit 5 is composed of ECL logic, the output is Since the edge of the pulse changes more slowly than in the normal operation state, the output pulse of the double pulse generation circuit 5 becomes an abnormal state in which the time difference T is indefinite, only one pulse is output, and no pulse is output. . FIG. 5 is a waveform explanatory diagram of the output pulse of the double pulse generating circuit 5 as described above.
(A) shows an output pulse in a normal state, and (b) shows that the two pulses applied to the input terminals of the OR gate 8 in FIG. The state () in which the time difference T of the pulses is indefinite is shown, and (c) shows the rise of the two pulses due to the slow change of the two pulses applied to each input terminal of the OR gate 8 in FIG. The falling and the rising are overlapped, and as a result, only one pulse is output (), and (d) is a result 1 in which two pulses applied to each input terminal of the OR gate 8 in FIG. The state () in which no individual pulse is output is shown.
Here, by appropriately setting the pulse widths of the two pulses applied to the respective input terminals of the OR gate 8 in FIG. 3, the output pulse of the double pulse generating circuit 5 in most metastable states is (c). can do. Specifically, the delay time of the delay circuit 10 shown in FIG. 3 may be appropriately set with respect to the pulse interval of the double pulse corresponding to 90 ° of the frequency output from the sine wave oscillator. Focusing on the output data X and Y of the A / D converter 3 in such an abnormal state, in the case of, X ² + Y ² ≠ A ² , and in the case of no, X ² + Y ² ≠ A ² X = Y The value of X, Y is either unchanged from the previous time.

Therefore, the amplitude data A of the sine wave signal in a normal state where the trigger control signal S ₁ and the trigger comparator output signal S ₂ are not metastable in time relationship is stored in the arithmetic control unit 6 in advance, By comparing this value with the measurement result at each subsequent measurement, it is possible to determine whether or not trigger jitter has occurred. When it is determined that the trigger jitter is generated, the data may be removed from the waveform reproduction calculation, and highly reliable waveform reproduction can be performed.

FIG. 6 is a flow chart showing the flow of the determination process of the trigger jitter in the arithmetic control unit 6.

That is, in step, a dummy output signal is added to the trigger control circuit 4, and the time relationship between the trigger control signal S ₁ and the trigger comparator output signal S ₂ is not metastable. The amplitude data A of the sine wave signal is measured and stored in the arithmetic control unit 6. After measuring the amplitude data A in this way, the measurement operation after the step is started. In the step, the amplitude A is calculated from the orthogonal data of X and Y, and it is determined whether or not X ² Y ² ≈A ² is satisfied (step). When X ² + Y ² ≠ A ² , the jitter is large, so the measured data is discarded (step), and the process returns to the step again. When X ² + Y ² ≈A ² holds, it is determined whether X = Y holds (step). When X = Y, the jitter is large, so the measured data is discarded (step), but when X ≠ Y holds, it is determined whether the values of X and Y have changed from the previous time. (Step). If the value has not changed, the jitter is large, so the measured data is discarded (step), but if the value has changed, it is valid data with little jitter and is used for data processing.
(Step). In this way, a series of processes is ended by repeating the processes after the step until a predetermined number of data necessary for the reconstruction of the waveform are fetched (step).

FIG. 7 is a circuit diagram showing another specific example of the double pulse generation circuit 5. In the figure, In is an input terminal to which an input pulse Vin is applied, and is directly connected to one input terminal of the NAND gate U4 and is connected to the NAND gate U4 via a series circuit of an inverter gate U3 and a delay circuit L1 having a delay time l. It is connected to the other input terminal. As a result, the NAND gate U4 outputs a pulse having a pulse width l. Where Nand Gate U
The pulse width 1 of the pulse output from 4 is set to an appropriate value so that the pulse shown in FIG. 5 (c) is output in the metastable state as described above. U1 is a buffer gate capable of obtaining a differential output, and U2 is a buffer gate configured so that the input and the output are differential. R
1, R1 ', R2, R2' are terminating resistors, one ends of which are connected to the output terminal of the buffer gate U1 and the other ends of the resistors R1, R1 'are connected to the voltage source V. Q,
Q'is a transistor for impedance conversion, each base is connected to the output terminal of the buffer gate U1 via terminating resistors R2 and R2 ', and each emitter is connected to a voltage source -V via a resistor R3 for determining a current value. , And each collector is connected to the voltage source V via the resistors R6 and R6 'and to the input terminal of the buffer gate U2 via the capacitors C and C'. DLY is a coaxial cable whose one end is open and whose length is adjusted so that the delay time becomes 1/2 of the double pulse interval T, and the outer conductor is connected to the collector of the transistor Q via the balun L. The inner conductor is connected to the collector of the transistor Q'via a balun L. The input terminal of the buffer gate U2 has a positive voltage source + V via resistors R4 and R4 ', respectively.
And a negative voltage source -V via resistors R5 and R5 '.

In such a configuration, double pulses having a differential relationship are output to the output terminals OUT1 and OUT2 of the buffer gate U2. Where Balun L
Means that the ground capacitances on the lines of the outer conductor and the inner conductor of the coaxial cable DLY are apparently equal to each other, and the waveform quality is prevented from being significantly different due to the differential. In addition, capacitors C and C '
The circuit including the resistors R4, R4 ', R5, and R5' constitutes a level conversion circuit for converting the level of the generated double pulse into the ECL level. With such a configuration, it is possible to obtain a stable differential double pulse output without causing a time lag (skew) due to a difference in paths as in the circuit of FIG.

In the above embodiment, the example in which the phase difference of the double pulse is set to 90 ° has been described, but it is obvious that the same effect can be obtained even at −90 ° or ± 270 °.

(Effects of the Invention) As described above, according to the present invention, it is possible to realize a trigger jitter detection circuit that can detect the presence or absence of occurrence of trigger jitter with a relatively simple configuration, and the practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams showing a concrete example of the main part of FIG. 1, and FIG.
FIG. 5 is a timing chart for explaining the operation of FIG. 1, FIG. 5 is a waveform example diagram of the output pulse of the double pulse generation circuit, and FIG. 6 is a specific example of the processing flow in the arithmetic control unit of FIG. 7 is a circuit diagram showing another specific example of the main part of FIG. 1, FIG. 8 is an explanatory diagram of waveform measurement by random sampling, and FIG. 9 is a block diagram showing an example of a trigger pulse output circuit. , FIG. 10 to FIG. 12 are diagrams for explaining conventional operation. 1 ... Sine wave oscillator, 2 ... Sampling pulse generation circuit, 3 ... A / D converter, 4 ... Trigger control circuit, 5 ...
… Double pulse generation circuit, 6… Operation control unit.

Claims (1)

[Claims] 1. A sine wave oscillator, a sampling pulse generation circuit for outputting a sampling pulse synchronized with an output signal of the sine wave oscillator, and a trigger control for selectively outputting a trigger pulse according to a trigger pulse input signal and a trigger control signal. A circuit, a double pulse generation circuit for outputting two pulses having a time difference corresponding to a phase difference of 90 ° of the sine wave signal according to a trigger pulse output from the trigger control circuit, and a double pulse generation circuit of the double pulse generation circuit. The amplitude Asi of the sine wave signal at the time when each pulse is output according to the output pulse
A / which converts nωt and Acosωt into digital signals X and Y
D converter and the sum of squares A ² (= X) of digital signals X and Y output from this A / D converter during normal operation without trigger jitter in advance.
² + Y ² ), and an arithmetic and control unit is provided for comparing the sum of squares A ² during normal operation with the measurement result during each measurement to determine whether or not trigger jitter has occurred. circuit.