JPH0620068B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0620068B2 JPH0620068B2 JP63285685A JP28568588A JPH0620068B2 JP H0620068 B2 JPH0620068 B2 JP H0620068B2 JP 63285685 A JP63285685 A JP 63285685A JP 28568588 A JP28568588 A JP 28568588A JP H0620068 B2 JPH0620068 B2 JP H0620068B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- power supply
- metal
- integrated circuit
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は電源供給路を工夫した半導体集積回路装置に関
する。DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device in which a power supply path is devised.
（従来の技術） 従来の半導体集積回路装置の電源，接地用メタル配線の
一例を第４図，第５図に示す。第４図は集積回路チップ
のパターン平面図，第５図はその一部断面図で，１は電
源（ＶDD）端子，２１は接地（ＶSS）端子，３は電源用
メタル配線，４は接地用メタル配線，５は半導体基板，
６は電極領域，７は第１の絶縁膜，８は第１のメタル配
線，９は第２の絶縁膜，１０は第２のメタル配線であ
る。(Prior Art) FIGS. 4 and 5 show an example of conventional metal wiring for power supply and grounding of a semiconductor integrated circuit device. FIG. 4 is a pattern plan view of an integrated circuit chip, and FIG. 5 is a partial cross-sectional view thereof. 1 is a power supply (V DD ) terminal, 21 is a ground (V SS ) terminal, 3 is a metal wiring for power supply, and 4 is Metal wiring for grounding, 5 is a semiconductor substrate,
6 is an electrode region, 7 is a first insulating film, 8 is a first metal wiring, 9 is a second insulating film, and 10 is a second metal wiring.
即ち従来の電源，接地用メタル配線は，特に第４図から
も明らかなように，チップ周辺とか，チップ内部へ木の
枝のようにレイアウトされている。That is, the conventional metal wiring for power supply and ground is laid out around the chip or inside the chip like a branch of a tree, as is clear from FIG.
（発明が解決しようとする課題） しかしながら従来の電源，接地用メタル配線のレイアウ
トでは，電源用メタル配線３，接地用メタル配線４の引
き回しによるインダクタンス，抵抗分の増加と，それに
ともなうロジック部での電源，接地電圧の変動の増加が
起こる。またＩＣ微細化が進むに従って，エレクトロマ
イグレーションや電源ノイズ対策のために，電源，接地
用メタル配線３，４の幅を広く設計する必要があり，そ
の結果，全チップ面積の平面的に占める電源，接地用配
線領域が増加する。(Problems to be Solved by the Invention) However, in the conventional layout of the power supply and grounding metal wirings, the inductance and resistance increase due to the wiring of the power supply metal wiring 3 and the grounding metal wiring 4, and the accompanying increase in the logic portion Increased fluctuation of power supply and ground voltage occurs. Further, as IC miniaturization progresses, it is necessary to design the widths of the power supply and the metal wirings 3 and 4 for grounding to be a countermeasure for electromigration and power supply noise. The ground wiring area is increased.
そこで本発明は，（イ）電源抵抗，インダクタンスの減
少による電圧変動の抑制，（ロ）ＩＣ微細化にともなう
エレクトロマイグレーションの防止，（ハ）チップサイ
ズの縮小，主な目的としている。Therefore, the main objects of the present invention are (a) suppression of voltage fluctuation due to reduction of power supply resistance and inductance, (b) prevention of electromigration due to IC miniaturization, and (c) reduction of chip size.
［発明の構成］ （課題を解決するための手段と作用） 本発明は，半導体基板に形成された集積回路の電源供給
用メタル層，接地用メタル層，一般配線層を，前記半導
体基板上にそれぞれ絶縁膜を介して別層構造で配置し，
前記電源供給用メタル層，接地用メタル層は，平面的に
見て，前記集積回路領域にわたり全面的に設けられかつ
それぞれの周縁部全体がチップ周縁部に近接して沿う面
状体であることを特徴とする半導体集積回路装置であ
る。[Structure of the Invention] (Means and Actions for Solving the Problems) The present invention provides a power supply metal layer, a ground metal layer, and a general wiring layer of an integrated circuit formed on a semiconductor substrate on the semiconductor substrate. They are arranged in separate layers through insulating films,
The power supply metal layer and the ground metal layer are planar bodies that are provided over the entire integrated circuit region in plan view, and the entire peripheral edge portions of the power supply metal layer and the ground metal layer extend along the periphery of the chip. Is a semiconductor integrated circuit device.
即ち本発明は，半導体集積回路の電源供給用，接地用メ
タル配線を，一般信号配線層に対してそれぞれ別層に
し，前記電源供給用，接地用メタル配線をチップ表面全
体に配し，これらより各々の電位を半導体集積回路の電
源として供給することにより，つまり上記電源供給用，
接地用メタル配線の立体化，広幅化により，上記（イ）
〜（ハ）項の目的を達成するものである。That is, according to the present invention, the power supply and grounding metal wirings of the semiconductor integrated circuit are separated from the general signal wiring layer, and the power supply and grounding metal wirings are arranged on the entire surface of the chip. By supplying each potential as the power source of the semiconductor integrated circuit, that is, for supplying the power source,
Due to the three-dimensional and widening of the ground metal wiring, the above (a)
It achieves the purpose of (C).
（実施例） 以下図面を参照して本発明の一実施例を説明する。第１
図は同実施例の要部断面図，第２図，第３図は共にその
全体的平面図で，第２図は電源供給用メタル層の表面と
して見たもの，第３図は接地用メタル層の表面として見
たものである。これら図において２１はチップ，２２は
電源ＶDD用のメタル（例えばＡ１）層，２３は接地ＶSS
用のメタル（例えばＡ１）層，２４は電源用端子（パッ
ド），２５は接地用端子（パッド），２６は半導体基
板，２７は電極領域，２８は第１の絶縁膜，２９は第１
の信号配線層，３０は第２の絶縁膜，３１は第２の信号
配線層，３２は第３の絶縁膜，３３はメタル層２２，２
３間の第４の絶縁膜である。メタル層２２，２３は適宜
コンタクト孔を通して下層の信号配線層２９とか３１に
電源を与えている。Embodiment An embodiment of the present invention will be described below with reference to the drawings. First
The figure is a cross-sectional view of the main part of the embodiment, FIGS. 2 and 3 are overall plan views thereof, FIG. 2 is seen as the surface of the power supply metal layer, and FIG. 3 is the ground metal. It is seen as the surface of the layer. In these figures, 21 is a chip, 22 is a metal (for example, A1) layer for power supply V DD , and 23 is ground V SS.
Metal (for example, A1) layer, 24 is a power supply terminal (pad), 25 is a ground terminal (pad), 26 is a semiconductor substrate, 27 is an electrode region, 28 is a first insulating film, and 29 is a first
Signal wiring layer, 30 is a second insulating film, 31 is a second signal wiring layer, 32 is a third insulating film, 33 is a metal layer 22, 2.
3 is a fourth insulating film. The metal layers 22 and 23 supply power to the lower signal wiring layers 29 and 31 through contact holes as appropriate.
この構成の特徴は，基板２６に形成された集積回路の電
源ＶDD供給用メタル層２２，接地ＶSS用のメタル層２
３，信号配線層２９及び３１を，基板２６上にそれぞれ
絶縁膜２８，３０，３２，３３を介して別層構造で配置
し，ＶDD用メタル層２２，ＶSS用メタル層２３を，平面
的に見て，集積回路領域にわたり全面的に設けられかつ
それぞれの周縁部全体がチップ周縁部に近接して沿う面
状体としたことである。The feature of this configuration is that the metal layer 22 for supplying the power supply V DD and the metal layer 2 for the ground V SS of the integrated circuit formed on the substrate 26.
3. The signal wiring layers 29 and 31 are arranged on the substrate 26 via the insulating films 28, 30, 32, and 33, respectively, in a separate layer structure, and the V DD metal layer 22 and the V SS metal layer 23 are flat. In view of the above, it is to be a planar body that is provided over the entire area of the integrated circuit, and the entire peripheral edge portions of the integrated circuit area are in close proximity to the peripheral edge portion of the chip.
上記のような構成であれば，ＶDD用メタル層２２，ＶSS
用メタル層２３を広幅化でき，またはこれらメタル層は
基板２６上のどこにでも存在するため，電源を最短距離
でとれ，従って電源ＶDD供給用及び接地ＶSS用メタル層
の配線抵抗，インダクタンスを減少させることができ，
またエレクトロマイグレーションも防止できる。また電
源用メタル層２２，２３を互いに立体化構造で配置し，
第４図の従来例の如く同一平面で引き回す必要がないた
め，チップ面積の縮小化が可能となる。ちなみに１．５
μｍデバイスで１０ｍｍ□チップにおいてチップ面積
は，チップ回りの電源用，接地用のメタル配線領域を削
除するだけで，１５％以上の縮小となる。また一般信号
配線２９，３１を電源用メタル層２２，２３の下に配置
したため，基板２６と一般信号配線２９，３１との間の
配線を行なう際に，逐一電源用メタル層２２，２３を突
き抜ける必要がないため，配線が良好に行なえるもので
ある。With the above structure, the V DD metal layer 22, V SS
Since the metal layer 23 for power supply can be widened, or these metal layers are present anywhere on the substrate 26, the power supply can be taken in the shortest distance, and therefore the wiring resistance and the inductance of the metal layer for power supply V DD supply and ground V SS can be reduced. Can be reduced,
Also, electromigration can be prevented. Also, the power supply metal layers 22 and 23 are arranged in a three-dimensional structure,
Unlike the conventional example shown in FIG. 4, it is not necessary to draw them on the same plane, so that the chip area can be reduced. By the way 1.5
chip area in 10 mm □ chips μm device for the chip around power, only remove the metal interconnection area for grounding, a reduction of 15% or more. Further, since the general signal wirings 29 and 31 are arranged below the power supply metal layers 22 and 23, when the wiring between the substrate 26 and the general signal wirings 29 and 31 is performed, the general power supply metal layers 22 and 23 are penetrated one by one. Good wiring is possible because it is not necessary.
なお本発明は実施例のみに限られず種々の応用が可能で
ある。例えば実施例では電源ＶDD用メタル層を上に，接
地ＶSS用のメタル層を下にしたが，これらの配置関係を
逆にしてもよい。また上記メタル層２２，２３は，第２
図，第３図の如くチップ２１のエッジ部に沿ってややあ
いており，また電源コンタクト用つき抜け孔や，ダミー
的に少々除去した部分がある場合は，チップ上全体を覆
っている面状体とはいい難いが，本発明においてはその
ような場合も含むものである。The present invention is not limited to the embodiments, and various applications are possible. For example, in the embodiment, the metal layer for the power supply V DD is on the top and the metal layer for the ground V SS is on the bottom, but the arrangement relationship of these may be reversed. In addition, the metal layers 22 and 23 are the second
As shown in Fig. 3 and Fig. 3, it is slightly open along the edge part of the chip 21, and if there is a through hole for power contact or a part removed a little like a dummy, the surface condition that covers the entire chip. Although it cannot be called a body, the present invention includes such a case.
［発明の効果］ 以上説明した如く本発明によれは，電源抵抗，インダク
タンスの減少による電圧変動の抑制，ＩＣ微細化にとも
なうエレクトロマイグレーションの防止，チップサイズ
の縮小化等が可能となる。また、多層信号配線層の場
合、上記本発明の構成のように、上層から下層に向けて
層中継する形で電源供給をすると、上層信号配線層から
下層信号配線層側に向けて、各層ごとに、下層の邪魔な
配線層とショートしないように避けながら絶縁膜の孔あ
けをして配線して電源供給できるから、電源供給の配線
が行いやすくなるものである。[Effects of the Invention] As described above, according to the present invention, it is possible to suppress voltage fluctuations due to a decrease in power supply resistance and inductance, prevent electromigration due to IC miniaturization, and reduce chip size. Further, in the case of a multilayer signal wiring layer, when power is supplied in the form of relaying layers from the upper layer to the lower layer as in the configuration of the present invention, each layer is fed from the upper signal wiring layer to the lower signal wiring layer side. In addition, since it is possible to supply power by forming holes in the insulating film and wiring while avoiding short circuit with the lower wiring layer, it is easy to perform power supply wiring.
第１図は本発明の一実施例の断面的構成図，第２図，第
３図は同構成の全体的平面図，第４図は従来装置の平面
図，第５図はその一部断面図である。 ２１……チップ、２２……電源ＶDD用メタル層、２３…
…接地ＶSS用メタル層、２６……半導体基板、２８，３
０，３２，３３……絶縁膜、２９，３１……一般信号用
配線層。FIG. 1 is a sectional view of an embodiment of the present invention, FIGS. 2 and 3 are overall plan views of the same construction, FIG. 4 is a plan view of a conventional apparatus, and FIG. 5 is a partial cross section thereof. It is a figure. 21 ... Chip, 22 ... Metal layer for power supply VDD , 23 ...
... Metal layer for ground V SS , 26 ... Semiconductor substrate, 28, 3
0, 32, 33 ... Insulating film, 29, 31 ... General signal wiring layer.
Claims (1)
この多層信号配線層上に電源用メタル層、接地用メタル
層を互いに別層構造で形成し、前記電源用メタル層、接
地用メタル層は、平面的にみて、前記集積回路領域にわ
たり全面的に設けられかつそれぞれの周縁部全体がチッ
プ周縁部に近接して沿う面状体であり、前記各メタル層
による電源供給は、前記多層信号配線層内の上層から下
層を介して前記半導体基板の半導体層に供給される構成
としたことを特徴とする半導体集積回路装置。1. A multi-layer signal wiring layer is formed on a semiconductor substrate,
A power supply metal layer and a grounding metal layer are formed on the multi-layer signal wiring layer in separate layer structures, and the power supply metal layer and the grounding metal layer are entirely covered over the integrated circuit region in plan view. Power supply by each of the metal layers is a planar body that is provided and extends along the entire periphery of each of the semiconductor layers of the semiconductor substrate via the upper layer to the lower layer in the multilayer signal wiring layer. A semiconductor integrated circuit device having a structure of being supplied to layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63285685A JPH0620068B2 (en) | 1988-11-14 | 1988-11-14 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63285685A JPH0620068B2 (en) | 1988-11-14 | 1988-11-14 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02132835A JPH02132835A (en) | 1990-05-22 |
| JPH0620068B2 true JPH0620068B2 (en) | 1994-03-16 |
Family
ID=17694722
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63285685A Expired - Lifetime JPH0620068B2 (en) | 1988-11-14 | 1988-11-14 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0620068B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08124928A (en) * | 1994-10-21 | 1996-05-17 | Nec Corp | Semiconductor integrated circuit |
| CN115444426B (en) * | 2022-11-09 | 2023-04-28 | 之江实验室 | On-chip electrode integrated wireless myoelectricity SoC system, chip and acquisition device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0244328U (en) * | 1988-09-21 | 1990-03-27 |
-
1988
- 1988-11-14 JP JP63285685A patent/JPH0620068B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02132835A (en) | 1990-05-22 |
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