JPH0620073B2 - Method for manufacturing heterojunction bipolar transistor - Google Patents

Description

The present invention relates to a method for manufacturing a heterojunction bipolar transistor.

[Prior art] Heterojunction bipolar transistor (hereinafter referred to as HBT)
In addition to the inherently large current drive capability of a bipolar transistor, has a main feature such as a reduction in parasitic elements made possible by the use of a semiconductor heterojunction and a reduction in the base transit time of minority carriers. By the way, HBT
In order to bring out the great potential of the above, reduction of extrinsic parasitic elements caused by the limit of microfabrication technology is a major issue.

Miniaturizing the electrodes of the HBT and the distance between the electrodes is
Self-aligned process technology is well known as a manufacturing process technology for reducing external base resistance and external base-collector capacitance. An example of the conventional self-alignment technique capable of forming the base electrode and the ion-implanted region in a self-aligned manner with respect to the emitter electrode by utilizing the pattern inversion process will be described with reference to FIG.

First, as shown in FIG. 6 (a), a semi-insulating GaAs substrate 14 is used.
A collector contact layer 13, a collector layer 7, a base layer 6, an emitter layer 5 and an emitter cap layer 4 are formed on the upper surface by a molecular beam epitaxial (MBE) method, and then SiO ₂ 2
To form a dummy emitter. This dummy emitter will later replace the emitter electrode.

Next, as shown in FIG. 6B, the emitter cap layer 4 and the emitter layer 5 are etched using SiO ₂ 2 as a mask to form an emitter mesa 20. Next, Mg ions are implanted as a base impurity using SiO ₂ 2 as a mask to form a P-type impurity implantation region 15 to reduce the external base resistance. Further, the base electrode 10 is formed on the entire surface.

Next, as shown in FIG. 6 (c), after covering the non-SiO ₂ 2 top with photoresist, and the base electrode 10 on the SiO ₂ 2 Si
O _{2 and} 2 are sequentially removed, and the emitter electrode 9 is formed on the exposed emitter cap layer 4. Next, this emitter electrode 9
Then, the base electrode 10 is removed by an ion milling method, and the P-type impurity implantation region 15 and the collector layer 7 thereunder are removed by a wet etching method. Next, the collector electrode 12 is formed on the exposed collector contact layer 13 by vapor deposition.

[Problems to be solved by the invention]

However, in the conventional method for manufacturing a heterojunction bipolar transistor as described above, in order to obtain a fine emitter (collector) intrinsic region width, an emitter mesa (collector mesa) having a width equal to a desired intrinsic region width is finely formed from the semiconductor substrate. Since it needs to be processed, it requires a high technique for finely processing the semiconductor layer, and has a drawback that the yield is deteriorated.

[Means for solving problems]

A method of manufacturing a heterojunction bipolar transistor according to the present invention comprises a step of forming an ion implantation mask for defining an intrinsic region of an emitter (collector) on an emitter layer (collector layer) formed on a semiconductor substrate, and the mask. Ion implantation is carried out at least once in a region excluding the intrinsic region by using a mask, and a side wall of the mask is formed with a sidewall, and the emitter layer (collector layer) is etched using the mask including the sidewall to form an emitter mesa ( Forming a collector mesa).

[Work]

According to the manufacturing method of the present invention, the width of the emitter mesa (collector mesa) can be made larger than the value required as the effective intrinsic region width of the emitter (collector), so that the process of processing the emitter mesa (collector mesa) is easy and the yield is good. Can be done with. Further, since the mesa etching mask can be formed by adding a sidewall to the ion implantation mask, it can be used as an etching mask without forming a new mask.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

1 (a) to 1 (d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the manufacturing method according to the present invention. First, as shown in Fig. 1 (a), a semi-absolute GaAs substrate 1
Collector contact layer 1 made of n ^-- GaAs on top of 4
3, a collector layer 7 made of n ⁻ -GaAs, a base layer 6 made of P ⁺ -GaAs, an emitter layer 5 made of n-Al _0.25 Ga _0.75 As, and an emitter cap layer 4 made of n ⁺ -GaAs were sequentially grown. After that, an ion implantation mask 30 composed of the silicon dioxide (SiO ₂ ) film 2 and the gold (Au) thin film 1 is formed on the surface thereof.

Next, as shown in FIG. 1 (b), by implanting a proton, the emitter cap layer 4 and the emitter layer 5 except the region covered by the ion implantation mask 30 are semi-insulated regions 3
To

Next, as shown in FIG. 1 (c), an ion implantation mask 30
After growing the SiO ₂ film on the entire surface including the semi-insulating region 3 while leaving, by anisotropic etching, SiO ₂
The side wall 8 is formed on the side surface of the ion implantation mask 30 composed of the Au film 1 and the SiO ₂ film. Using the combination of the SiO ₂ side wall 8 and the ion implantation mask 30 as an etching mask, the emitter cap layer 4 and the emitter layer 5 are sequentially anisotropically etched to have a wider width than the non-ion implantation region. The emitter mesa 20A is formed.

Next, as shown in FIG. 1 (d), Au used as a mask
After removing the film 1, the SiO ₂ film 2 and the SiO ₂ side wall 8, thin films of titanium, platinum and gold are sequentially deposited, and the emitter electrode 9 and the base electrode 10 are formed by non-alloy contact. Even if the base electrode 10 comes into contact with the side surface of the emitter mesa, the surface of the emitter mesa 20A is semi-insulated by the proton injection, so that the base electrode 10 and the emitter are not electrically short-circuited. Next, the base electrode 10, the base layer 6 and the collector layer 7 in the collector electrode forming portion are removed to form the collector electrode 12.

Further, in the embodiment shown in FIG. 2, protons are further injected into the collector layer 7 to reduce the external base-collector capacitance.

Further, in the embodiment shown in FIG. 3, in order to reduce the external base resistance, Mg ions are further implanted as base impurities to form the P-type impurity implantation region 15. In the embodiment of FIG. 3, since the electrons pass only a narrow width determined by the width of the ion implantation mask over the entire electron transporting path from the emitter to the base to the collector, the intrinsic region of the HBT is Is effectively smaller than the emitter mesa, and since the ion-implanted regions 3 and 15 are formed in self-alignment with the intrinsic region of the emitter, the high frequency characteristics of the HBT are remarkable. Can be improved.

In the embodiment shown in FIG. 4, the emitter cap layer 4
A is made of n ⁺ -Al _0.25 Ga _0.75 As having the same wide band gap as the emitter layer 5. As a result, magnesium ions instead of protons are deeply implanted until they reach the base layer as ions for deactivating the outside of the emitter mesa, and the external base region and the outside region of the emitter mesa are integrated to reduce the number of ion implantation steps. ing. The built-in potential of the pn junction formed in the emitter mesa is larger than the built-in potential of the pn junction between the emitter and the base because the semiconductors that are joined together have a wide band gap, and therefore the normal operating bias region of the HBT. Then, the P-type region formed outside the emitter mesa is an inactive region.

The ion implantation mask and the emitter mesa etching mask do not have to have the shapes and materials shown in the above-described embodiments, but each of them functions as a mask, and the width of the emitter mesa etching mask is the ion implantation mask. Any shape may be adopted as long as it has a width larger than the original width of the mask by the thickness of the side wall, and the material of the mask is not limited.

Therefore, as shown in FIG. 5 (a), the SiO ₂ film 2 serving as a mask is formed.
In addition to A, a SiO ₂ film having a thickness that allows the permeation of ions may remain in a region to be ion-implanted. And the fifth
As shown in FIG. 5 (b), after the ion implantation, the Au film 1 is selectively removed, a SiO ₂ film is grown on the entire surface, and anisotropic etching is performed to obtain the structure shown in FIG. 5 (c). The SiO ₂ sidewall 8A may be formed to form a mask for emitter mesa etching.

Although anisotropic etching is used for the mesa etching in the above embodiment, the mesa width may be made smaller than that of the mesa etching mask by using isotropic etching partially or wholly in the mesa etching. Although the emitter electrode and the base electrode are formed at the same time, they may be formed of different electrode materials by a pattern inversion method or the like. Further, in the above embodiment, the method of manufacturing the emitter-top type HBT is taken as an example, but it goes without saying that the scope of application of the present invention extends to the method of manufacturing the collector-top type HBT as well.

〔The invention's effect〕

As described above, according to the manufacturing method of the HBT of the present invention, when the emitter mesa (collector mesa) of the emitter (collector) / top heterojunction bipolar transistor is formed, it depends on the high technology for finely processing the semiconductor material. Since it is possible to form an effective intrinsic region narrower than the mesa width inside the mesa, a heterojunction bipolar transistor having a higher yield and higher performance than that obtained by using a conventional mesa forming technique can be obtained.

Further, the size of the non-operating region of the mesa is evenly divided to the left and right of the intrinsic region by the side wall of the ion implantation mask, and the width can be delicately controlled by the thickness of the side wall. Therefore, the mesa is determined by one exposure mask that defines the ion implantation mask, and can be minimized without waste.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention, FIGS. 2 to 4 are sectional views of essential parts showing an embodiment of an ion implantation region, and FIG. 5 is an ion implantation mask. And a cross-sectional view showing an embodiment of a mesa etching mask,
FIG. 6 is a sectional view of a semiconductor chip for explaining a conventional method for manufacturing a heterojunction bipolar transistor. 1 ... Au film, 2, 2A ... SiO ₂ film, 3 ... Semi-insulating region, 4, 4A ... Emitter cap layer, 5 ... Emitter layer, 6 ... Base layer, 7 ... Collector layer, 8,8A ...
... SiO ₂ side wall, 9 ... emitter electrode, 10 ... base electrode, 12 ... collector electrode, 13 ... collector contact layer, 14 ... GaAs substrate, 15 ... P-type impurity implantation region, 16 ... n ⁺ -Al _0.25 Ga _0.75 As, 20 ... Emitter mesa, 30 ... Ion implantation mask.

Claims (1)

[Claims] 1. A step of forming an ion implantation mask for defining an intrinsic region of an emitter (collector) on an emitter layer (collector layer) formed on a semiconductor substrate, and a region excluding the intrinsic region using the mask. Forming a side wall on the side surface of the mask after performing ion implantation at least once, and forming an emitter mesa (collector mesa) by etching the emitter layer (collector layer) using the mask including the side wall. A method of manufacturing a heterojunction bipolar transistor, comprising: