JPH0620100B2 - Adjustment method of semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for adjusting a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit in which the polarity of a voltage applied to an adjustment terminal for cutting a fuse is adjusted when adjusting with a fuse. The present invention relates to a method for adjusting a semiconductor integrated circuit, which is determined in consideration of the breakdown voltage of a MOS transistor that constitutes the.

[Conventional technology]

Conventionally, in order to accurately realize a reference voltage in a semiconductor integrated circuit, a plurality of sets of high resistance elements and fuses are prepared, a voltage is selectively applied to the fuses from an adjustment terminal, and the fuses are blown by a transient high temperature. Therefore, the method of adjusting the semiconductor integrated circuit has been general. This adjusting method includes, for example, a high resistance element in which the first terminal is connected to a positive power source,
The second terminal of the high resistance element is connected to the first terminal of the fuse and the adjustment terminal for applying the adjustment voltage, and the second terminal of the fuse is grounded. With such a configuration, the connection point between the second terminal of the high resistance element and the first terminal of the fuse before the fuse is cut is because the resistance value of the fuse is smaller than that of the high resistance element. , Judged to be at a logic low level.

On the other hand, after the fuse is blown in the adjusting circuit realized by such a high resistance element and the fuse, the connection point is pulled up to the voltage value of the positive power source through the high resistance element. Therefore, the connection point is judged to be at the logic high level.

An example of such a high resistance element connected to the positive power source side is a positive power source whose source terminal is grounded, whose gate terminal is connected to an arbitrary DC voltage value, and whose drain terminal is connected to a fuse. It is often realized by a channel MOS transistor. As an example in which the high resistance element is connected to the ground side, an N-channel MOS transistor in which the source terminal is connected to the ground, the gate terminal is connected to an arbitrary DC voltage value, and the drain terminal is connected to the fuse is used. It is common.

[Problems to be solved by the invention]

In the above-mentioned conventional preparation method, the voltage value applied to the adjustment terminal is limited due to the decrease in the gate length of the MOS transistor and the accompanying decrease in the source-drain breakdown voltage of the MOS transistor, which is accompanied by the decrease in the power supply voltage. Occurs.

For example, when a high resistance element is realized by a P-channel MOS transistor for the positive power supply voltage, it is difficult to set the voltage value that can be applied to the adjustment terminal to a voltage value of the positive power supply or more in order to avoid abnormal operation such as latch-up. Is.

On the other hand, the fuse cutting voltage needs to have a value with a sufficient margin when the power of the semiconductor integrated circuit is turned on and off, and for example, needs to be maintained at about 5V to 10V.

As described above, in consideration of the reduction of the power supply voltage accompanying the miniaturization of the gate length of the MOS transistor and the securing of the fuse cutting voltage, there is a problem that the conventional semiconductor integrated circuit adjustment method cannot adjust or the adjustment yield decreases. .

[Means for solving problems]

According to a method for adjusting a semiconductor integrated circuit of the present invention, a first terminal of a current source element formed of a MOS transistor is connected to a first power source, and a second terminal of the current source element is connected to an adjustment terminal and a first terminal of a fuse. The second terminal of the fuse is connected to a second power source, and when the voltage value of the second power source is smaller than the voltage value of the first power source, the voltage value of the second power source is applied to the adjustment terminal. The fuse is blown by applying a voltage smaller than that of the first power supply, and when the voltage value of the second power supply is larger than the voltage value of the first power supply, a voltage larger than the voltage value of the first power supply is applied to the adjustment terminal. It is characterized in that the fuse is cut by doing so.

〔Example〕

 Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an equivalent circuit explanatory diagram of a first embodiment to which a method for adjusting a semiconductor integrated circuit according to the present invention is applied. P-channel MOS transistors 2 and 3 connected to positive power supply terminal 1 form a current mirror circuit, and P-channel MO transistor
A current determined by the threshold voltage of the S transistor 2 and the resistance value of the resistor 4 flows in the P channel MOS transistor 2.
P-channel MOS transistor 3 operates as a current mirror circuit, and if the channel regions of transistors 2 and 3 have the same size, substantially the same current flows.

Since the resistance value of the fuse 6 is at most a few hundred ohms at the maximum, the voltage of the adjustment terminal 5 becomes almost the ground potential. Therefore, the logical input level of the inverter 8 whose input is connected to the adjustment terminal 5 becomes low.

The fuse 6 is blown by applying a voltage lower than the ground potential to the adjustment terminal 5. Then, the adjustment terminal 5 rises to almost the positive power supply voltage because the P-channel MOS transistor 3 is conducting, and the logic input level of the inverter 8 becomes high. In this way, if a voltage equal to or lower than the ground potential (for example, −10 V) is applied to the adjustment terminal 5 to blow the fuse 6, the positive power supply voltage is set to 5 V.
It is necessary to set the drain-source withstand voltage to 15 V or more, and set the gate length L to be thicker in consideration of the drain-source withstand voltage than a normal P-channel MOS transistor, or use the P-channel MOS transistor 3 with the common gate electrode. It is sufficient to use two P-channel MOS transistors that are vertically stacked.

If a positive voltage (for example, 10 V) is applied to the adjustment terminal 5 here, the parasitic diode 7 existing between the P-channel MOS transistor 3 and the positive power supply terminal 1 becomes conductive and the semiconductor integrated circuit latches up or the parasitic diode Due to conduction, the fuse 6 is in a low impedance state, which causes inconvenience such that the fuse 6 cannot be cut. In order to avoid such an inconvenience, it is effective to apply a voltage equal to or lower than the ground potential to the adjusting terminal 5 to blow the fuse 6 as in the first embodiment of the present invention.

FIG. 2 is an equivalent circuit explanatory diagram of a second embodiment to which the method for adjusting a semiconductor integrated circuit according to the present invention is applied. In FIG. 2, the same parts as in FIG. 1 are used with the same numbers.

The difference between FIG. 2 and FIG. 1 is that the fuse 6 has moved from the ground potential to the positive power supply terminal 1 side. Along with this, the connection between the N-channel MOS transistors 12 and 13 forming the current mirror circuit and the resistor 4 which determines the current is changed.

Consider cutting of the fuse 6 as in the first embodiment. A positive voltage (for example, 15 V) is applied to the adjustment terminal 5 with respect to the positive power supply terminal 1 (for example, 5 V), and 10 V is applied to both ends of the fuse 6 to cut the fuse. At this time, N channel MO
Since the drain-source voltage of the S transistor is 15 V, it is necessary to determine the L dimension of the transistor while paying attention to the withstand voltage, or to arrange two N-channel MOS transistors in a vertically stacked structure.

In the circuit of FIG. 2, when the voltage of the adjusting terminal 5 is applied to the ground potential or less and the fuse 6 is blown, the parasitic diode 17 becomes conductive and the semiconductor integrated circuit is latched up. It may be impossible due to the conduction of 17.

The first and second embodiments of the present invention show an example, and any constant current source may be used as the high resistance element.

〔The invention's effect〕

As described above, according to the present invention, as a method of adjusting a semiconductor integrated circuit, by applying a fuse cutting voltage that makes a parasitic diode non-conductive to the adjustment terminal, the semiconductor integrated circuit is not latched up and the fuse is stabilized. There is an effect that the fuse can be cut and a margin is provided so that an unnecessary fuse is not cut when the power is turned on and off.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an equivalent circuit of the first embodiment of the present invention, and FIG.
The figure is an equivalent circuit diagram of the second embodiment. 1 ... Positive power supply terminal, 2, 3 ... P-channel MOS transistor, 4 ... Resistance, 5 ... Adjustment terminal, 6 ... Fuse, 7, 17 ... Parasitic diode, 8 ... Inverter,
12, 13 ... N-channel MOS transistors.

Claims (1)

[Claims] 1. A first terminal of a current source element formed of a MOS transistor is connected to a first power source, and a second terminal of the current source element is connected.
The terminal of the fuse is connected to the adjustment terminal and the first terminal of the fuse, and the second terminal of the fuse is connected to the second power supply,
When the voltage value of the second power source is smaller than the voltage value of the first power source, the fuse is blown by applying a voltage smaller than the voltage value of the second power source to the adjustment terminal,
When the voltage value of the second power source is larger than the voltage value of the power source, the fuse is blown by applying a voltage higher than the voltage value of the first power source to the adjustment terminal. Adjustment method.