JPH0620129B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline of the Invention] The present invention relates to a MES-FET (a field effect transistor having a metal-semiconductor structure utilizing a Schottky barrier) and an M.
The present invention has the characteristics of an IS-FET (insulating gate type field effect transistor having a metal-insulator-semiconductor structure), and a DLC-FET (depletion region control type field effect transistor, which will be omitted in the present invention hereinafter). Referred to as DIS-FET).

In the present invention, the conventional MIS-FET simply miniaturizes the size of the element, but the pattern is scaled by the short channel effect which causes a leak current that unintentionally flows between the source and the drain in the off state. The semiconductor device has a speed equal to or higher than that of a MIS-FET having a limit that cannot be downsized (miniaturization), that is, a channel length of 0.1 to 1 μ, and has an effect not seen in the past.

The present invention has, as its basic features, low-voltage operation (0.1 to 2 V) and bulk mobility (μ _e -15).
00cm ² V / sec, μ _e ~ 500 cm ² V / sec) is used, and it is 3 more than the conventional MIS-FET whose surface mobility is dominant.
~ 6 times faster with the same pattern and scale
The depletion layer barrier is controlled by the work function of the gate electrode or the impurity level, the complementary type can be manufactured on the same substrate as compared with the MES-FET, and the use of silicon nitride for the insulating film provides higher reliability than the MES-FET. Characteristics, heat resistance, and the fact that it is a self-aligned type and the characteristics of conventional MIS-FETs can be used as they are,
Channel length is 0 because bulk majority carriers are used.
It can be set to 1 μm, leakage of subthreshold current is extremely small, known LSI technology and CAD technology can be applied to system design as they are, and heat resistance in the DIS-FET region allows multi-layer wiring. In particular, it can be applied to non-volatile RAM.

It has an extremely large effect that it can provide all of the many features desired by the IC, LSI, and VLSI industries up to now.

[Conventional technology]

Conventionally, a MES-FET is known as a transistor having a structure relatively similar to that of the present invention. This is shown in FIG. 1 as a vertical sectional view. The substrate semiconductor (1) is produced by the ion implantation method of light doping with the region (2) of the opposite conductivity type and the source (5) rather than the drain (6). Furthermore, a Schottky barrier of platinum (3) is created for this semiconductor region (2). This Schottky barrier forms a depletion layer in the semiconductor region to control the current flowing from the source to the drain.

[Problems of conventional technology]

However, in this structure, platinum is not directly silicon semiconductor (2)
Therefore, there is manufacturing variation. Furthermore, in the past, P
Cannot be channel type. In addition, it has no heat resistance. Electrode (3)
Since the source (5) and the drain (6) are easily short-circuited, there are many drawbacks such as the need to provide a void (60).

The present invention proposes a DIS-FET that attempts to eliminate the above-mentioned drawbacks while making the best use of the characteristics of MESFET such as low voltage operation and bulk mobility. The details will be described below.

[Embodiment 1] FIG. 2 shows an embodiment of a vertical sectional view of the present invention.

In the drawing, a semiconductor such as silicon (crystal orientation (100) P ⁻
The (ρ ≧ 10 Ωcm or more) type was used as the substrate (1). Further, this upper surface is selectively masked with silicon nitride or the like, and 0.5 to 2 μm at 800 to 1000 ° C. in a known high pressure (about 10 to 15 atmospheres).
A field insulator (7) was formed by selective oxidation to a thickness of m. Furthermore, a P-type region (10) of 0.3 to 1 μm is formed on this substrate.
Was formed by ion implantation, and a semiconductor region (2) was formed on the upper surface to a thickness of 50 to 3000Å, especially 100 to 500Å by the second ion implantation. This semiconductor region (2) forms a depletion layer, and the depletion layer must be light-doped to the extent that it can be easily spread to the lower surface, that is, the junction surface of (2)-(10) by the potential of the electrode. The impurity concentration was controlled to 10 ^{14 to} 3 × 10 ¹⁶ cm ^-3 . In addition, the source (5) and drain (6) are implanted by the third ion implantation to produce 10 ¹⁷ ~
It was prepared at a concentration of 10 ¹⁹ cm ^-3 . Between the pair of impurity regions
The distance was 0.1 to 1 μm. Source (5), Drain (6)
Is manufactured in the semiconductor region (2) and the lower side thereof in a normally-off state with a channel length shortened to 0.1 to 1 μm, for example, involuntary leakage between the source and drain of the order of 10 ⁻⁹ to 10 ⁻¹² Å The production and order of the semiconductor layer (10) for preventing the occurrence of the short channel effect that a current flows may be changed.

In this example, after the surface of this semiconductor layer was sufficiently cleaned, a silicon nitride film was formed on the upper surface to a thickness of 2 to 100 Å. The following two were used for the production of this silicon nitride. That is, the plasma nitriding method can be used. In the plasma nitriding method, the semiconductor is immersed in an atmosphere having a pressure of 0.1 to 10 torr, and the atmosphere is added to a mixed gas of ammonia (NH ₃ ) or nitrogen (N ₂ ) and hydrogen (H ₂ ) to add 5 to the gas. It was induced plasma at ~500MH _z for example 13.56MH _z. The surface of a semiconductor is nitrided by chemically activating a reactive nitride gas. It is possible to obtain a film thickness of 2 to 30Å at a temperature of the semiconductor substrate of humidity to 300 ° C and a film thickness of 20 to 200Å at 300 to 800 ° C.

The present invention uses such a silicon nitride film, and even if it is thin enough to pass the tunnel current of the nitride film, it is substantially MIS-F.
A major feature is that it can act as a DIS-FET as a modification of ET.

The film formed by such plasma nitriding method is Si ₃ N
_The silicon nitride film has a structure of No. ₄ , but when natural oxide is present on the semiconductor surface, it has a structure of SiO _x N _y .

A nitride film may be formed by implanting nitrogen near the surface of the semiconductor by an ion implantation method instead of the plasma nitriding method.

Further, instead of such an insulating film, a semi-insulating film can be used. The semi-insulating film is mixed on the surface of the semiconductor at a pressure of 0.001 to 1 torr at a ratio of SiH ₄ / NH ₃ / H ₂ = 1 / 0.5 to 10/0 to 50, and vapor phase growth is performed on the surface to be formed on the semiconductor. (500-800 ° C). 2-1 by plasma vapor phase method (room temperature to 500 ° C)
It may be formed to a film thickness of 00Å. In such a case Si ₃ N _4-x
(0.5 <x <4), and a semi-insulating film was formed.

In the present invention, the interface state density of such an insulating film is 3 × 10 ¹⁰ cm ⁻² or less, particularly 1 × 10 ¹⁰ cm ⁻² or less, and the drift of V _TH due to the interface charge is 0.1 V or less and particularly 0.01 V or less. It is very important to be. When the interface level is large, the bending of the energy band generated in the substrate semiconductor by this level exceeds that by the electrode, and C / DIS
It becomes difficult to make a -FET (complementary DIS-FET) configuration and the like.

In the present embodiment, the semiconductor or semi-insulating film (8) is doped with boron as a next step at 10 ¹⁸ cm ^-3 or more by a low pressure gas phase method or a plasma gas phase method, and 0.03 to 0.
An electrode (9) was obtained by forming it to a thickness of 3 μm, especially 0.1 μm.

In this embodiment, the electrode (9) is P
Made into a mold. Then, in the semiconductor region (2) directly below the electrode, the depletion layer (11) (DEPLATION
LAYER) occurs. Since the lower surface of this depletion layer reaches the lower side (bottom surface of the semiconductor region), it is important to create a normally-off state.

In this embodiment, since the insulating or semi-insulating film (8) is made of silicon nitride, the boron in the electrode does not reach the upper surface of the semiconductor region (8) due to the extremely excellent masking action against the impurities. Furthermore, since the impurities do not enter the silicon nitride, the electric conduction in the film is only the leak current due to the tunnel current or the floor node Heim current due to the thin film thickness.
The current value did not fluctuate.

Since the insulating or semi-insulating film (8) has a thin thickness of 2 to 200 Å, especially 30 to 80 Å, the work function potential of the gate electrode could be directly applied to the semiconductor region for the first time. This is another feature of the present invention.

In particular, the insulating or semi-insulating film (8) has a thickness of 2 to 200 Å, especially 30 to 80 Å because of the relationship shown in FIG. In particular, in the N-channel DIS-FET in which the thickness of the gate insulating film is changed and the semiconductor electrode is a P ⁺ type, the impurity concentration of the channel formation region of the substrate is 5 × N ⁻ .
In the case of 10 ¹⁵ cm ⁻³ , there is a difference of 0.8 V between the Fermi level of the gate electrode and the Fermi level of the substrate. The energy band on the semiconductor surface is bent to eliminate this difference,
Try to eliminate the difference between each other. As a result, the difference with the semiconductor surface inside the semiconductor is as large as 0.8V. However, if an insulating film is interposed between the gate electrode and the semiconductor surface, a potential drop occurs in this dielectric portion as the thickness increases,
As a result, the bending of the energy band on the surface of the semiconductor is reduced. This relationship is shown in FIG.

That is, from the relationship of this thickness, it is necessary to bend the energy band on the surface of the semiconductor within a range that is practically acceptable.
If it is set to Å or less, especially 80 Å or less, a difference of 0.3 V or more can be made. However, if the thickness is too thin, a tunnel current will flow too much between the gate electrode and the substrate, so it was found that the tunnel current should be 30 Å or more, which is a range in which no tunnel current flows. It is clear that this thickness can be achieved only when the interface state density is 3 × 10 ¹⁰ cm ⁻² or less in the present invention and the influence of this order is sufficiently small.

In this embodiment, if there is a pinhole in the film (8), the impurity of the electrode diffuses to the upper part of the semiconductor region through the hole, and a PN junction is formed there. In this case, a locally created so-called junction type FET (JUNCTION TYPE FET or J
FET) is possible. Therefore, locality is generated in the expansion of the depletion layer, and the frequency characteristic is deteriorated. However, in the case of the structure of the present invention, even if there is such a pinhole, it is
Another feature is that it does not completely deny the operation of the FET.

In this example, after that, the electrode leads (15) and (16) were made to the source (5) and the drain (6) by making ohmic contact with the semiconductor or metal of the same conductivity type at the electrode portion.

FIGS. 2 (B) and 2 (C) are energy band diagrams of AA ′ in (A).

In Fig. 2 (B), (10 ') corresponds to the semiconductor substrate (1) or (10) in (A) and (2') corresponds to the semiconductor region (2).
The energy band widths (8 ') corresponding to the insulating or semi-insulating film (8) and (9') corresponding to the electrode (9) are shown respectively. (11 ') is a depletion layer. Due to this depletion layer, the band is convex upward, and this DIS-FET is an N channel, and electrons cannot pass from the source to the drain.

However, as shown in FIG. 2 (C), the electrode (9) has a voltage of 0.1 to 2V, for example.
The voltage of 0.3V, which is much lower than that of IG-FET (voltage of 2 to 20V of insulated gate field effect transistor), the energy band becomes (2 ') by applying such a low positive voltage. The current can flow through the portion (12) when the portion of (12) is lowered. That is, since the depletion layer is a normally-off type MIS type device in which electric conduction is controlled, the semiconductor device of the present invention can be used as a DIS-FET (DEPLETION LAYER CONTROLLE).
D METAL (SEMICONDUCTOR) -INSULATION-SEMICONDUCTOR
TYPE FIELD EFFCT TRANSISTOR).

This electron is a bulk carrier, and the mobility of the surface-conducting IG-FET is μ _e ≈ 300 to 500 cm ² V / sec, while the mobility is 3 to 5 times that of μ _e ≈ 1300 to 1500 cm ² V / sec. Have. The use of this bulk mobility is an extremely important feature of the present invention.

As a feature of the present invention, since the P-type semiconductor region having a higher concentration than that of the P ⁻ type substrate is formed below the N-type region forming the channel, it is possible to prevent short channel leak from occurring between the source and the drain. did it. Therefore, the channel length can be reduced to 0.1 to 1 μm, which is 1 μm or less. As the gate electrode, a P-type semiconductor electrode was used in the N-channel DIS-FET. Similar effects can be expected even if platinum, tungsten, gold, molybdenum, tantalum, titanium, chromium, nickel, or an alloy or mixture thereof (for example, nichrome, molybdenum silicide, tungsten silicide) is used.

In the present invention, the conventional MES-FET cannot be used with platinum as an electrode, but conversely, a metal having a small work function or N is used.
^{This is possible because a +} type semiconductor is also provided with an insulating or semi-insulating film interposed between the electrode and the semiconductor region. In this case, a P-channel type DIS-FET can be formed. In such a case, the metal is required to be a metal having a work function smaller than 4 eV, such as aluminum, magnesium, beryllium, or value. These are summarized in the table below.

In the present invention, when a transparent electrode is added to the electrode, a photosensitive semiconductor device can be obtained. That is, when the light radiated through the conductive transparent electrode through this electrode generates an electron-hole pair in the semiconductor region therebelow, this electron is N
It is also a great feature of the present invention that an extremely high speed photocell can be formed by reaching the drain in the channel.

[Embodiment 2] FIGS. 3A and 3B show another embodiment of the present invention.

In the drawing (A), a field insulator (7) is provided on the N-type semiconductor by a selective oxidation method or the like, and the semiconductor region (2) is 50-3000 Å especially in the P ⁻ type by the first ion implantation method.
Formed to a thickness of 500-800 Å. After that, a silicon nitride film having a thickness of 2 to 200 Å is formed on these surfaces in the same manner as in Example 1, and then an opening between the source (5) and the drain (6) is opened.
Amorphous or polycrystalline non-single-crystal semiconductor silicon is formed on the entire upper surface thereof. Furthermore, this semiconductor film (0.03 ~
0.3 μm) is selectively oxidized to remove the electrodes and leads,
Converts to silicon oxide. In this selective oxidation, even if oxygen is ion-implanted into the portion to be oxidized, a silicon nitride film having a masking action is formed on the electrode and lead portions,
You may oxidize by oxidizing gas, such as steam. A second field insulator (14) is thus formed. After that, a P ⁺ type impurity such as boron is added to the source (5) drain (6) and each lead (15) (16) to a concentration of 10 ¹⁷ to 10 ²¹ cm ^-3 to form a P ⁺ semiconductor. Then, phosphorus is selectively added to the electrode (9) at a concentration of 10 ¹⁸ to 10 ²² cm ^-3 . This impurity is sufficiently diffused at a temperature of 500 to 1000 ° C, especially 600 to 700 ° C, and the electrodes (9), leads (15) and (16) are thin 0.05.
The thickness may be about 0.1 μm. After that, in order to selectively increase the conductivity on these electrodes and leads, metal (19) (19 ') was formed in a multi-layer structure to a thickness of 0.1 to 0.5 .mu.m. This metal may be a refractory metal such as tungsten or molybdenum, or a metal such as aluminum or titanium.

In order to perform multiple wiring on this upper surface, the PIQ
It is sufficient to form a polyamide-based organic coating such as the above, form the electrodes and contact holes thereof, and further form the second wiring on the upper surface thereof.

This embodiment is a P-channel type DIS-FET, but the source (5) drain (6) and the electrode (9) are formed by one mask, and the source (5) drain (6) and each electrode, The features of the leads (15) and (16) are that they are made of the same main component material and that complete ohmic contact is achieved from the same material, and that the electrodes and leads are also selectively oxidized.

Of course, instead of this electrode (9), Table 1 in Example 1 was used.
Needless to say, a material corresponding to the P-channel DIS-FET of 1 may be used.

FIG. 3 (B) is a modification of part of the manufacturing process of FIG. 3 (A). FIG. 3 (B) shows an N-channel type DIS-FET, but a second semiconductor region (12) is formed inside the semiconductor region (13) formed at the same time as the semiconductor region (2) in (A).
Are provided by the ion implantation method.

Also, B of the source (5) and drain (6) in FIG. 3 (A)
The same impurities are added to the electrode of the electrode (9) in (B) at the same time. Further, at the same time as phosphorus is added to the electrode (9) in (A), the same impurities are added to the source (5) and drain (6) and their electrodes and leads (15) and (16) in (B). By doing this, Fig. 3 (A) and
(B) P-channel DIS-FE on the same semiconductor substrate (1)
The T (FIG. 3A) and the N-channel DIS-FET (B) can be integrally formed at the same time.

As described above, since the conventional MES-FET uses the Schottky structure electrode, only the N-channel type can be formed, but a complementary DIS-FET (C / DIS-FET or C / DIS) can be formed. It was This C / DIS-
The FETs may of course be connected in series or in parallel depending on the circuit application.

The other manufacturing method of FIG. 3 (B) is the same as that of FIG. 3 (A).

In the above semiconductor device, when V = 0.5, td of 0.1 to 0.5 nsec can be obtained, and extremely high speed operation is possible.

[Embodiment 3] This embodiment is shown in FIG. 4, which is a symbolization of the structure shown in FIGS. 2 to 3 and further the application thereof.

FIG. 4 (A) shows one DIS-FET (40), but the source (45), drain (46), semiconductor region (47), electrode
(49) is provided corresponding to the source (5), drain (6), semiconductor region (2) and electrode (9) in FIG. 2 (A).

(B) is FIG. 3A in the second embodiment, that is, P channel D
The IS-FET is shown in (42), and the N-channel DIS-FET is shown in (40) in FIG. 3 (B). Input (4
2), the output (44) is shown and the electrodes are shown at (48) and (49) respectively.

FIG. 4 (C) shows a P-channel and N-channel DIS-FET.
Are connected in parallel and are provided to increase the switching speed of the signal from (45) to (46). It is a transmission circuit.

FIG. 4 (D) is applied to a 1Tr / bit type memory comprising one DIS-FET (40) and a capacitor (47) connected in series with it.

Fig. 4 (E) is the depletion type DIS- of Fig. 4 (C).
Set the load of FET to (47), the enhancement type DIS-
The FET driver is shown at (40), and the output is taken out from (44) as an inverter for the input (42).

FIG. 4 (F) shows a non-volatile memory.

A floating electrode (49 ') and a control electrode (49) are provided.

FIG. 4 (G) is shown in Table 1 of Example 1, which is an N-channel type DIS-FET and the electrodes are formed of ITO. The irradiation light (60) causes the source (45) to drain ( Four
A current is allowed to flow in 6), and a DIS-FET for a photosensor is formed by bulk diffusion of electron-hole pairs generated by light irradiation to the drain.

As is apparent from the above description, the present invention has a known structure M
It is similar to IS-FETs or MES-FETs and may give the feeling of combining them. However, the present invention has been made in order to bring out only the respective advantages, and the gate electrode is a MIS-FET.
Similarly to the above, the channel region was formed in the same manner as the MES-FET. The thickness of the insulating film or the semi-insulating film is 2 to 200 Å, especially 30 to 80 Å, so that the MIS-FET has a leak and a low voltage less than the threshold voltage (V _th ). Voltage (3 to 1V), _Vth lower limit is 0.8 to 1V
Therefore, it was not possible to make V _G and V _E below 2 V in reality. However, the present invention provides such V _th
Work function or (electron affinity) that the electrode has
+ (Fermi level) could be given essentially uniquely. For this reason, the operating voltage can be made extremely small to 0.1 to 2 V and the scaling can be performed accordingly, and since there is no short channel effect, the channel length can be reduced to 0.1 to 1 μm. .

For this reason, it is a very industrially important semiconductor device that can produce td≈0.01 to 0.5 ns.

In the above description, silicon nitride is used for the insulating or semi-insulating film, but silicon oxide or silicon carbide may be used in place of silicon nitride. Also, the semiconductor is not limited to silicon,
It goes without saying that it may be a III-V compound semiconductor such as germanium, silicon carbide, GaAlAs or GaP, or a II-VI compound semiconductor such as CdS.

It is preferable that the electrode is a semiconductor and has the same main component as that of the substrate for ease of manufacturing. However, it goes without saying that another semiconductor or a semiconductor having a wide energy band width to which oxygen or nitrogen is added to further increase the depletion layer may be used.
In particular, the semiconductor region is a silicon single crystal, and the electrode has an energy band width of 5 to 50 mol% of oxygen or nitrogen or 0.01 to 3 mol% of P ⁺ or N ⁺ type impurities. 1.5-2.0 eV instead of 1.0 eV
Therefore, the depletion layer can be further widened, and therefore the practical use voltage can be increased to 0.5 to 4V rather than 0.1 to 2V.

When a metal is used as the electrode in the present invention, all the metals shown in Table 1 can be applied to all the examples. It goes without saying that the manufacturing method of Example 1 can be applied to Examples 2 to 3 as well.

Example 3 showed a combination of two DIS-FETs. However, combining a plurality of these basic configurations to make a memory system of 1 Mbit or the like or a logic system having 10 ⁵ to 10 ¹⁹ gates is considered as a natural application by applying the integrated circuit technology to the present invention.

[Brief description of drawings]

It is a longitudinal cross-sectional view of the conventional MFS-FET of FIG. FIG. 2 is a longitudinal sectional view (A) of the DIS-FET of the present invention, and energy band diagrams (B) (C) showing it. FIG. 3 is a vertical sectional view of another embodiment of the present invention. FIG. 4 shows a circuit diagram of the DIS-FET of the present invention and a connection diagram of its application circuit. FIG. 5 is a diagram showing the difference in Fermi level between the substrate surface and the inside of the semiconductor with respect to the thickness of the gate insulating film.

Claims (4)

[Claims] 1. A semiconductor substrate having a P-type conductivity is formed on a semiconductor substrate having a conductivity type of 0.
An impurity region which forms a pair of N-type source and drain and is separated by 1 to 1 μm, and a region capable of forming a channel of the same conductivity type as the impurity region provided between the regions are provided. By forming a gate insulating film having an interface state density of 3 × 10 ¹⁰ cm ⁻² or less with a thickness of 30 to 80 Å above and a P-type semiconductor serving as a gate electrode on the gate insulating film, A threshold voltage is set according to the affinity and the Fermi level, and a depletion layer is formed in a region where the N-type channel can be formed by the gate electrode and the P-type semiconductor substrate under the condition that no voltage is applied to the gate electrode. At least, the pair of impurity regions are normally off, and a positive voltage is applied to the gate electrode, so that the interface between the semiconductor substrate and the gate insulating film is removed. Is a semiconductor device characterized by occupying a current is supplied between the pair of impurity regions by a channel formed inside the semiconductor. 2. A semiconductor substrate having a P-type conductivity is formed on a substrate having a conductivity type of 0.
An impurity region which forms a pair of N-type source and drain and is separated by 1 to 1 μm, and a region capable of forming a channel of the same conductivity type as the impurity region provided between the regions are provided. An electron affinity is obtained by forming a gate insulating film having an interface state density of 3 × 10 ¹⁰ cm ^-2 or less with a thickness of 30 to 80 Å above and a transparent conductive film as a gate electrode on the gate insulating film. And a threshold voltage is set by the Fermi level, and a depletion layer is formed in a region where the N-type channel can be formed by the gate electrode and the P-type semiconductor substrate in a state where no voltage is applied to the gate electrode. By setting a normally-off state between the pair of impurity regions and applying a positive voltage to the gate electrode, the semiconductor substrate and the gate insulating film are separated from each other. To occupy a current is supplied between the pair of impurity regions of a semiconductor inside a channel formed Te wherein a. 3. A semiconductor substrate having an N type conductivity is formed on a semiconductor substrate having a conductivity type of 0.
An impurity region that forms a pair of P-type source and drain and is spaced apart by 1 to 1 μm, and a region capable of forming a channel of the same conductivity type as the impurity region provided between the regions are provided. By forming a gate insulating film having an interface state density of 3 × 10 ¹⁰ cm ⁻² or less with a thickness of 30 to 80 Å above and an N-type semiconductor as a gate electrode on the gate insulating film, A threshold voltage is set according to the affinity and the Fermi level, and a depletion layer is formed in a region where the N-type channel can be formed by the gate electrode and the N-type semiconductor substrate in a state where no voltage is applied to the gate electrode. At least, the pair of impurity regions are normally off, and a negative voltage is applied to the gate electrode, so that the interface between the semiconductor substrate and the gate insulating film is removed. Is a semiconductor device characterized by occupying a current is supplied between the pair of impurity regions by a channel formed inside the semiconductor. 4. A semiconductor substrate having N-type conductivity is formed on a semiconductor substrate having a conductivity type of 0.
An impurity region that forms a pair of P-type source and drain and is spaced apart by 1 to 1 μm, and a region capable of forming a channel of the same conductivity type as the impurity region provided between the regions are provided. An electron affinity is obtained by forming a gate insulating film having an interface state density of 3 × 10 ¹⁰ cm ^-2 or less with a thickness of 30 to 80 Å above and a transparent conductive film as a gate electrode on the gate insulating film. And a threshold voltage is set according to the Fermi level, and a depletion layer is formed in a region where the N-type channel can be formed by the gate electrode and the N-type semiconductor substrate in a state where no voltage is applied to the gate electrode. By setting a normally-off state between the pair of impurity regions and applying a negative voltage to the gate electrode, the semiconductor substrate and the gate insulating film are separated from each other. To occupy a current is supplied between the pair of impurity regions of a semiconductor inside a channel formed Te wherein a.