JPH0620149B2 - Method of manufacturing thin film solar cell - Google Patents
Method of manufacturing thin film solar cellInfo
- Publication number
- JPH0620149B2 JPH0620149B2 JP60060824A JP6082485A JPH0620149B2 JP H0620149 B2 JPH0620149 B2 JP H0620149B2 JP 60060824 A JP60060824 A JP 60060824A JP 6082485 A JP6082485 A JP 6082485A JP H0620149 B2 JPH0620149 B2 JP H0620149B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode layer
- solar cell
- film solar
- amorphous silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/20—Electrodes
- H10F77/206—Electrodes for devices having potential barriers
- H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
- H10F77/215—Geometries of grid contacts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/10—Semiconductor bodies
- H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
- H10F77/147—Shapes of bodies
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Photovoltaic Devices (AREA)
Description
【発明の詳細な説明】 [利用分野] 本発明は非晶質シリコン層を光起電力層とする薄膜太陽
電池の製造方法に関する。更に詳細には絶縁性基板上に
積層された下部電極層/非晶質シリコン層/上部電極層
の下部電極層に電流取り出し用電極を接続させる薄膜太
陽電池の製造方法に関する。TECHNICAL FIELD The present invention relates to a method for manufacturing a thin film solar cell using an amorphous silicon layer as a photovoltaic layer. More specifically, it relates to a method for manufacturing a thin film solar cell in which a current extraction electrode is connected to a lower electrode layer of a lower electrode layer / amorphous silicon layer / upper electrode layer laminated on an insulating substrate.
[従来技術] 非晶質シリコン半導体膜はシランガス等のグロー放電分
解法によって低い基板温度で、広い面積に均一に堆積で
き、基板もガラス,高分子フイルム,セラミック板,金
属フォイル等の各種基板が選択できる為、太陽電池用半
導体膜として広く研究されている。[Prior Art] An amorphous silicon semiconductor film can be uniformly deposited on a wide area at a low substrate temperature by a glow discharge decomposition method using silane gas or the like, and various substrates such as glass, polymer film, ceramic plate and metal foil can be used. Since it can be selected, it has been widely studied as a semiconductor film for solar cells.
非晶質シリコン太陽電池の基本構造としては上記各種基
板上に設けられた金属電極層/非晶質シリコン半導体層
/透明電極層の積層構造が用いられている。As a basic structure of an amorphous silicon solar cell, a laminated structure of a metal electrode layer / amorphous silicon semiconductor layer / transparent electrode layer provided on the above various substrates is used.
非晶質シリコン層堆積の特徴を生かし特開昭59-34668号
公報に開示されたロールツーロール方式やJapan Joarn
al of Applied Physics誌21巻3号 413ページ(198
2)に掲載されている3室分離形成法などを用いて金属
電極層を設けた大面積の長尺基板上に非晶質シリコン層
を堆積することは容易である。Taking advantage of the characteristics of amorphous silicon layer deposition, the roll-to-roll method disclosed in Japanese Patent Laid-Open No. 59-34668 and Japan Joarn
al of Applied Physics, Volume 21, Issue 3, Page 413 (198
It is easy to deposit an amorphous silicon layer on a large-area long substrate provided with a metal electrode layer by using the three-chamber separation forming method described in 2).
又、もう一方の電流取り出し電極の透明電極層を大面積
に設ける事も容易である。しかしながら太陽電池として
上記積層体を働かす為には金属電極層と透明電極層とに
リード端子を取り付ける事が必要である。さらに、実用
化に必要な数十V以上の出力電圧を得る為には、上記大
面積基板上に設けた太陽電池をレーザスクライブ法等で
分割しその後隣接し合う金属電極層と透明電極層とを直
列接続する事が必要である。かかる場合最下層である金
属電極層を露出させる事が必須の要件となる。この方法
として 非晶質シリコン層堆積時に金属マスクを用いる方
法、 非晶質シリコン層堆積後、湿式あるいは乾式のエッ
チング法を用いシリコン層を除去する方法、 非晶質シリコン層堆積後、レーザ照射によってシリ
コン層のみを選択的に溶融,蒸発させて除去する方法 などが用いられてきた。It is also easy to provide the transparent electrode layer of the other current extraction electrode in a large area. However, it is necessary to attach lead terminals to the metal electrode layer and the transparent electrode layer in order to operate the above-mentioned laminated body as a solar cell. Further, in order to obtain an output voltage of several tens of volts or more required for practical use, the solar cell provided on the large-area substrate is divided by a laser scribing method or the like, and then the adjacent metal electrode layer and transparent electrode layer are formed. It is necessary to connect in series. In such a case, exposing the lowermost metal electrode layer is an essential requirement. This method uses a metal mask when depositing the amorphous silicon layer, removes the silicon layer using a wet or dry etching method after depositing the amorphous silicon layer, and uses laser irradiation after depositing the amorphous silicon layer. Methods such as selectively melting and vaporizing only the silicon layer to remove it have been used.
これらの方法の中で、の方式は長尺、大面積のロール
ツーロール方式に適さないばかりか3室分離形成法にお
いても、非晶質シリコン堆積時の加熱過程において、基
板とマスクの熱膨張率の違いによる密着性の悪化の為、
非晶質シリコン成分の回り込みが生じ良好なパターンが
得られず且つ、電気的に良好な金属層表面を露出させる
ことがむつかしい。Among these methods, the method is not suitable for the roll-to-roll method of a long area and a large area, and even in the three-chamber separation formation method, the thermal expansion of the substrate and the mask during the heating process at the time of depositing the amorphous silicon. Due to the deterioration of adhesion due to the difference in rate,
It is difficult to expose the surface of the metal layer where an amorphous silicon component wraps around and a good pattern cannot be obtained and which is electrically good.
の方式はレジスト塗付とエッチングの組み合わせによ
って可能であるが、レジスト塗付,露光,洗浄,エッチ
ング等の多数の工程が必要であり、安価に大量に太陽電
池を製造するには適さない。又の方式においてはシリ
コン層溶融に必要な高温発生の為、高融点金属を用いた
金属電極層においても損傷が生じ電気的に良好な金属層
表面を露出させる事が出来ないばかりか、Alのごとき
低融点金属ではシリコン層のみを選択的に除去する事も
出来ないのが実状である。Although this method is possible by combining resist coating and etching, it requires a number of steps such as resist coating, exposure, cleaning, and etching, and is not suitable for manufacturing a large number of solar cells at low cost. In the other method, since the high temperature necessary for melting the silicon layer is generated, the metal electrode layer using the high melting point metal is damaged and the electrically good metal layer surface cannot be exposed. In reality, it is not possible to selectively remove only the silicon layer with a low melting point metal.
[発明の目的] 本発明は、上記現状に鑑みなされたもので、大面積基板
上でのリード端子取り出し又は、分離されたセルの直列
接続を可能にする為の電流取り出し用電極を下部の電極
面に簡単に接続できる薄膜太陽電池の製造方法を提供す
ることを目的とするものである。[Object of the Invention] The present invention has been made in view of the above situation, and a current extraction electrode for allowing lead terminals to be taken out on a large-area substrate or series connection of separated cells to be a lower electrode. It is an object of the present invention to provide a method for manufacturing a thin film solar cell that can be easily connected to a surface.
[発明の構成及び作用] 上述の目的は以下の本発明により達成される。すなわ
ち、本発明は、電気絶縁性の基体上に下部電極層,非晶
質シリコン層からなる光起電力層,上部電極層を順次積
層した薄膜太陽電池の下部電極へ上部から電流取り出し
用電極を接続するに際し、光起電力層上の一部に上部電
極層と電気的に絶縁された領域を形成しておき、該領域
において機械加工により上部から下部電極層に達するV
字状断面の溝若しくは穴を設け、該溝若しくは穴に導電
性樹脂を充填して下部電極層に電気接続した導電性樹脂
からなる電流取り出し電極を設けることを特徴とする薄
膜太陽電池の製造方法である。[Structure and Action of the Invention] The above-mentioned object is achieved by the present invention described below. That is, the present invention provides a lower electrode of a thin film solar cell in which a lower electrode layer, a photovoltaic layer made of an amorphous silicon layer, and an upper electrode layer are sequentially laminated on an electrically insulating substrate, and an electrode for current extraction is provided from above to the lower electrode. At the time of connection, a region electrically insulated from the upper electrode layer is formed on a part of the photovoltaic layer, and V reaches the lower electrode layer from the upper part by machining in the region.
A method for manufacturing a thin-film solar cell, characterized in that a groove or hole having a V-shaped cross section is provided, and the current extraction electrode made of a conductive resin electrically filled in the groove or hole and electrically connected to the lower electrode layer is provided. Is.
上述の本発明は、機械加工により、光起電力層上の一部
に形成された上部電極層と電気的に絶縁された領域にお
いて、下部電極層の光起電力層、場合により上部電極層
を穿設して下部電極層に達するV字状断面の溝あるいは
穴を設け、該溝あるいは穴に導電性樹脂を埋め込み電流
取り出し用電極とするものであり、前述した特定のパタ
ーン化等が不要で、且つ簡単に機械加工と、スクリーン
印刷等の組合せで所望の電気接続が形成でき、非常に生
産性が良く且つ歩留りも良い製造プロセスを実現するも
のである。The present invention described above, in the region electrically insulated from the upper electrode layer formed in a part on the photovoltaic layer by machining, the photovoltaic layer of the lower electrode layer, and in some cases the upper electrode layer A groove or hole having a V-shaped cross section is formed by drilling to reach the lower electrode layer, and a conductive resin is embedded in the groove or hole to serve as an electrode for current extraction, and the above-described specific patterning is unnecessary. In addition, a desired electrical connection can be easily formed by a combination of machining and screen printing, and a manufacturing process with extremely high productivity and high yield is realized.
以下本発明の詳細を具体的に説明する。The details of the present invention will be specifically described below.
第1図は、本発明の対象となる薄膜太陽電池の一例の側
断面図である。FIG. 1 is a side sectional view of an example of a thin-film solar cell which is the subject of the present invention.
図において、は電気絶縁性の基板,は下部電極層の
金属電極層,は起電力層の非晶質シリコン層,は上
部電極層の透明電極層であり、周知の非晶質シリコン薄
膜太陽電池が示してある。なお、本発明は、図示のもの
に限定されず、下部電極層を透明電極層とし上部電極層
を金属電極層としたもの、あるいは上下の両電極層を透
明電極層としたものにも適用できる。In the figure, is an electrically insulating substrate, is a metal electrode layer of a lower electrode layer, is an amorphous silicon layer of an electromotive force layer, is a transparent electrode layer of an upper electrode layer, and is a well-known amorphous silicon thin film solar cell. Is shown. The present invention is not limited to what is shown in the drawings, and can be applied to a transparent electrode layer for the lower electrode layer and a metal electrode layer for the upper electrode layer, or a transparent electrode layer for both upper and lower electrode layers. .
ところで、本発明の電気絶縁性の基板としては電気絶
縁材からなる全ての基板が適用でき、具体的には高分子
フイルム,セラミック板、あるいは絶縁性層を表面に設
けたフォイル等が使用出来るが、好ましくはロールツー
ロール法によって構成層を順次長尺の走行する基板上に
堆積出来、大量生産に適した高分子フイルムが使用され
る。高分子フイルムとしては、非晶質シリコン堆積に必
要な耐熱性を有する高分子フイルムならどれでも良い
が、好ましくは機械的特性面の優れたポリエチレンテレ
フタレート(PET)フイルム,ポリエチレンナフタレ
ートフイルム,ポリイミドフイルムなどが用いられる。By the way, as the electrically insulating substrate of the present invention, all substrates made of an electrically insulating material can be applied, and specifically, a polymer film, a ceramic plate, or a foil having an insulating layer on its surface can be used. Preferably, a polymer film is used which is capable of sequentially depositing constituent layers on a long running substrate by a roll-to-roll method and is suitable for mass production. As the polymer film, any polymer film having heat resistance necessary for depositing amorphous silicon may be used, but preferably polyethylene terephthalate (PET) film, polyethylene naphthalate film, polyimide film having excellent mechanical properties. Are used.
下部電極層若しくは上部電極層として用いられる金属電
極層としては、Al,Ag,Ti,W,Pt,Ni,
Co,Cr,ニクロム,ステンレスなどの単体金属,合
金金属の単層膜、あるいは多層膜が用いられるが好まし
くはAl,Agを主成分とした電極層が用いられる。
又、これらの金属電極層は、その電気抵抗の低下及び機
械的強度の観点から0.3μm以上の厚みが望ましい。As the metal electrode layer used as the lower electrode layer or the upper electrode layer, Al, Ag, Ti, W, Pt, Ni,
A single layer film of a single metal such as Co, Cr, nichrome, stainless steel, or an alloy metal, or a multi-layer film is used, but an electrode layer containing Al or Ag as a main component is preferably used.
Further, the thickness of these metal electrode layers is preferably 0.3 μm or more from the viewpoint of reduction in electric resistance and mechanical strength.
非晶質シリコン層は、光起電力能を有するものであれ
ば特に限定されないが、具体的には既に公知のシランガ
ス,ジシランガス等のグロー放電分解を用いたプラズマ
CVD法を用いて形成されたpin 形の積層光起電力層等
がある。なお、かかる非晶質シリコン光起電力層として
は、pin /pin ,pin /pin 等の多層タンデム構造はも
ちろんのこと非晶質シリコンゲルマニウム,非晶質シリ
コンカーバイトなどのナローバンドギャップあるいはワ
イドバンドギャップ半導体層を適時用いる事も出来る。The amorphous silicon layer is not particularly limited as long as it has a photovoltaic ability, but specifically, it is a pin formed by the plasma CVD method using glow discharge decomposition of already known silane gas, disilane gas, etc. Shaped photovoltaic layers and the like. The amorphous silicon photovoltaic layer may have a multi-layer tandem structure such as pin / pin or pin / pin, as well as a narrow bandgap or wide bandgap such as amorphous silicon germanium or amorphous silicon carbide. The semiconductor layer can also be used in a timely manner.
上部電極層又は下部電極層に用いられる透明導電層も
特に限定されず、公知のものが全て適用できる。例えば
酸化インジューム,酸化スズ,スズ酸カドニウム等の酸
化物導電体を電子ビーム蒸着あるいはスパッタリング法
によって堆積したもの等が適用できる。更に透明導電性
接着層を介して、前述の金属電極層/非晶質シリコン層
の積層体表面に透明導電膜を接合させた薄膜太陽電池に
も適用できる。The transparent conductive layer used for the upper electrode layer or the lower electrode layer is not particularly limited, and any known material can be used. For example, an oxide conductor such as indium oxide, tin oxide, or cadmium stannate deposited by electron beam evaporation or sputtering can be used. Further, it can be applied to a thin film solar cell in which a transparent conductive film is bonded to the surface of the above-mentioned metal electrode layer / amorphous silicon layer laminate through a transparent conductive adhesive layer.
機械加工としては、V字状断面の溝若しくは穴が形成で
きるものであれば良いが、先の尖った加工部材を用いる
ものが好ましい。かかる加工部材としては、ナイフや針
状体等が利用できる。そして例えばこれら加工部材を非
晶質リンコン層上において機械的に移動ないし殴打させ
る事によって下部電極層に達する溝あるいは穴を形成す
る。この溝又は穴は電気接続の低抗化及び高信頼化面か
ら所定部所の全面に亘って複数個形成することが好まし
い。The machining may be performed as long as a groove or hole having a V-shaped cross section can be formed, but it is preferable to use a pointed processing member. As such a processing member, a knife, a needle-shaped body or the like can be used. Then, for example, by mechanically moving or striking these processed members on the amorphous Rincon layer, a groove or a hole reaching the lower electrode layer is formed. It is preferable to form a plurality of grooves or holes over the entire surface of a predetermined portion in order to reduce the resistance of electrical connection and increase reliability.
加工の際の加工部材の接圧は非晶質シリコン層を除去す
るのに十分でかつ電気絶縁性の基体に到達しない程度が
好ましく、そのつど最適値を選択して行なうことが望ま
しい。The contact pressure of the processing member during processing is preferably sufficient to remove the amorphous silicon layer and does not reach the electrically insulating substrate, and it is desirable to select the optimum value in each case.
例えば、ナイフのごとき先の尖った加工部材で下部金属
電極層上に非晶質シリコン層を積層後加工する場合
は、加工部材を非晶質シリコン層上で機械的に所定接
圧下で繰り返し移動させると、第2図(A)のごとく、
複数条のV字状溝が形成できその溝側面で下部金属電
極層を露出させることができる。次に、該露出金属層
部位からの電流取り出し用電極は、このV次状溝上
に導電性樹脂層をスクリーン印刷法等で設ける事によっ
て第2図(B)のごとく、下部電極に溝を介して電
気接続した状態で形成できる。なかでも、導電性樹脂層
をスクリーン印刷法で設ける方法は、該工程が大気雰囲
気で、しかもマスクレスで行なわれるため本発明主旨の
点からも好ましい。ここで、溝又は穴の形状が前述の通
りV字状断面であるので、これら製造法において良好な
電気接続が得られる。なお、その開口部の幅は電流取り
出し用電極の形成法に応じて適宣選定される 下部金属電極層/非晶質シリコン層/透明電極層堆積後
の場合も同じ方法で下部金属電極層よりの電流取り出し
電極を堆積できる。For example, when processing the amorphous silicon layer on the lower metal electrode layer using a pointed processing member such as a knife after processing, the processing member is mechanically repeatedly moved on the amorphous silicon layer under a predetermined contact pressure. Then, as shown in FIG. 2 (A),
A plurality of V-shaped grooves can be formed and the lower metal electrode layer can be exposed on the side surfaces of the grooves. Next, the electrode for extracting electric current from the exposed metal layer portion is provided with a conductive resin layer on the V-shaped groove by a screen printing method or the like so that the lower electrode is provided with a groove through the groove as shown in FIG. 2 (B). Can be formed in a state of being electrically connected. Among them, the method of providing the conductive resin layer by the screen printing method is preferable from the viewpoint of the present invention because the step is performed in the atmosphere and without a mask. Here, since the shape of the groove or hole is the V-shaped cross section as described above, good electrical connection can be obtained in these manufacturing methods. The width of the opening is appropriately selected according to the method of forming the current extraction electrode. Even after the lower metal electrode layer / amorphous silicon layer / transparent electrode layer is deposited, the same method is used as compared with the lower metal electrode layer. Can be deposited.
[実施例] 基板として、100μm厚のポリエチレンテレフタレー
トフイルム(PET)を用いた。まず該フイルム基板
をマグネトロンスパッタ装置に装着し、10-3torr台のA
r雰囲気中でアルミニウム層(Al) 0.4μm,及びス
テンレス層(SS)100Åを連続して順次堆積し、金属
電極層を長尺フイルム基板1上に設けた。さらにこの
PET/Al/SS堆積体上に非晶質シリコンのpin 型
の光起電力層を特開昭59-34668号公報に開示されてい
るロールツーロール方式によって長尺で大面積に連続的
に堆積した。同一基板上で3個のセルが直列接続された
太陽電池モジュールを形成する為に大面積の上記PET
/Al/SS非晶質シリコン層上第3図黒帯Bで示すよ
うな分割パターンの電気絶縁層をスクリーン印刷し、そ
の後第3図の斜線の領域Sに金属マスクを設け電気ビー
ム蒸着で酸化インジュームの透明導電層を堆積した。
さらに黒帯B上をYAGレーザーで照射するレーザース
クライブ法によって前記分割パターンに沿って1個当た
り24.5m2の面積を有する3個のセルCに分割加工した。[Example] As a substrate, a polyethylene terephthalate film (PET) having a thickness of 100 μm was used. First, the film substrate was attached to a magnetron sputtering apparatus, and an A of 10 -3 torr level was set.
An aluminum layer (Al) 0.4 μm and a stainless layer (SS) 100 Å were successively and successively deposited in an r atmosphere to provide a metal electrode layer on the long film substrate 1. Further, a pin type photovoltaic layer of amorphous silicon is continuously formed on the PET / Al / SS stack by a roll-to-roll method disclosed in Japanese Patent Laid-Open No. 59-34668. Deposited on. The above PET having a large area for forming a solar cell module in which three cells are connected in series on the same substrate.
/ Al / SS Amorphous silicon layer is screen-printed with an electrically insulating layer having a division pattern as shown by a black band B in FIG. 3, and then a metal mask is provided in a shaded area S in FIG. An indium transparent conductive layer was deposited.
Further, by a laser scribing method of irradiating the black belt B with a YAG laser, the cells were divided into three cells C having an area of 24.5 m 2 along the division pattern.
この分解された3個のセルCを、以下のように直列接続
し、集積構造の太陽電池モジュールを得た。すなわち、
第3図、第5図の透明電極層が設けられていない、す
なわち透明電極層と絶縁された領域Sにおいて金属電
極層を露出させる為ステンレス製のナイフを用い、領
域SのセルCの上面に対して垂直に保持した状態で所定
接圧で押圧しつつ繰返し水平方向に移動させることによ
り、金属電極層/非晶質シリコン層を貫通して領域
Sの全面に亘り数100 μm幅のV字状溝Tを均一密度で
形成した。次いで電流取り出し電極Pとして第4図、第
5図に示すパターンの銀ペースト層をスクリーン印刷に
より透明導電層上及び露出した金属電極層上に設
け、セルC間を直列接続した。すなわち本例では電流取
り出し電極PにセルC間の接続と収集電極とを兼用させ
た。The three disassembled cells C were connected in series as follows to obtain a solar cell module having an integrated structure. That is,
A stainless knife is used to expose the metal electrode layer in the region S where the transparent electrode layer shown in FIGS. 3 and 5 is not provided, that is, the region S insulated from the transparent electrode layer. In contrast to this, a V-shaped line having a width of several hundred μm is penetrated through the metal electrode layer / amorphous silicon layer while being vertically pressed and repeatedly moved in the horizontal direction while being pressed with a predetermined contact pressure. The grooves T were formed with a uniform density. Next, a silver paste layer having a pattern shown in FIGS. 4 and 5 was provided as a current extraction electrode P on the transparent conductive layer and the exposed metal electrode layer by screen printing, and the cells C were connected in series. That is, in this example, the current extraction electrode P was used as both the connection between the cells C and the collecting electrode.
この3直列モジュールの性能をAM1( 100mW/c
m2)ソーラシミュレータ光下で測定した結果を表1に示
した。The performance of this 3 series module is AM1 (100mW / c
Table 1 shows the results of measurement under m 2 ) solar simulator light.
比較の為、金属電極層,非晶質シリコン層,透明電極層
をそれぞれ金属マスクを用いて形成した同じ機構の3直
列モジュールのAM1ソーラシミュレータ光下の測定結
果を示した。For comparison, the measurement results under the light of the AM1 solar simulator of the three series modules having the same mechanism in which the metal electrode layer, the amorphous silicon layer, and the transparent electrode layer are formed using the metal mask are shown.
表1の結果は、両者には有意差が見られず本発明の製造
方法によって、低抵抗の金属電極−透明導電層間の直列
が得られる事を示している。 The results in Table 1 show that there is no significant difference between the two and that a low resistance metal electrode-transparent conductive layer in series can be obtained by the manufacturing method of the present invention.
第1図は本発明の対象の薄膜太陽電池の一例の側断面
図,第2図(A),(B)は本発明を説明するための各
ステップでの薄膜太陽電池の側断面図,第3図は実施例
のセルの分割パターンを示す平面図,第4図は実施例の
電流取り出し電極のパターンを示す平面図、第5図は部
分断面を含む実施例の構造の説明図である。 :基板、:金属電極層 :非晶質シリコン層、:透明電極層 :溝、C:セルFIG. 1 is a side sectional view of an example of a thin film solar cell of the present invention, and FIGS. 2 (A) and 2 (B) are side sectional views of the thin film solar cell at each step for explaining the present invention. FIG. 3 is a plan view showing a cell division pattern of the embodiment, FIG. 4 is a plan view showing a pattern of a current extraction electrode of the embodiment, and FIG. 5 is an explanatory view of a structure of the embodiment including a partial cross section. : Substrate ,: metal electrode layer: amorphous silicon layer ,: transparent electrode layer: groove, C: cell
Claims (4)
リコン層からなる光起電力層,上部電極層を順次積層し
た薄膜太陽電池の下部電極層へ上部から電流取り出し用
電極を接続するに際し、光起電力層上の一部に上部電極
層と電気的に絶縁された領域を形成しておき、該領域に
おいて機械加工により上部から下部電極層に達するV字
状断面の溝若しくは穴を設け、該溝若しくは穴に導電性
樹脂を充填して下部電極層に電気接続した導電性樹脂か
らなる電流取り出し電極を設けることを特徴とする薄膜
太陽電池の製造方法。1. A current extracting electrode is connected from above to a lower electrode layer of a thin-film solar cell in which a lower electrode layer, a photovoltaic layer made of an amorphous silicon layer, and an upper electrode layer are sequentially laminated on an electrically insulating substrate. In this case, a region electrically insulated from the upper electrode layer is formed in a part of the photovoltaic layer, and a groove or a hole having a V-shaped cross section which reaches the lower electrode layer from the upper part by machining in the region. And a current extracting electrode made of a conductive resin electrically connected to the lower electrode layer by filling the groove or hole with the conductive resin, and providing the thin film solar cell.
断面の溝又は穴を形成する特許請求の範囲第1項記載の
薄膜太陽電池の製造方法。2. The method for producing a thin film solar cell according to claim 1, wherein a groove or hole having a V-shaped cross section is formed by machining with a pointed processing member.
て複数個配設した特許請求の範囲第1項若しくは第2項
記載の薄膜太陽電池の製造方法。3. The method for manufacturing a thin-film solar cell according to claim 1, wherein a plurality of the grooves or holes are provided over the entire surface of the region.
法により導電性樹脂を印刷して設ける特許請求の範囲第
1項,第2項若しくは第3項記載の薄膜太陽電池の製造
方法。4. The method for manufacturing a thin film solar cell according to claim 1, 2, or 3, wherein the current extraction electrode is provided by printing a conductive resin by a screen printing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60060824A JPH0620149B2 (en) | 1985-03-27 | 1985-03-27 | Method of manufacturing thin film solar cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60060824A JPH0620149B2 (en) | 1985-03-27 | 1985-03-27 | Method of manufacturing thin film solar cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61220478A JPS61220478A (en) | 1986-09-30 |
| JPH0620149B2 true JPH0620149B2 (en) | 1994-03-16 |
Family
ID=13153487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60060824A Expired - Fee Related JPH0620149B2 (en) | 1985-03-27 | 1985-03-27 | Method of manufacturing thin film solar cell |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0620149B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4315096A (en) * | 1980-07-25 | 1982-02-09 | Eastman Kodak Company | Integrated array of photovoltaic cells having minimized shorting losses |
-
1985
- 1985-03-27 JP JP60060824A patent/JPH0620149B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61220478A (en) | 1986-09-30 |
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