JPH0620198B2 - Timing generation circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing generation circuit that generates a timing signal for identifying received data.

There are multi-point sampling and single-point sampling in order to distinguish "1" and "0" of the received data. In an asynchronous data terminal, a clock signal faster than the data rate is used. The received data is identified by the multipoint sampling. Further, in the synchronous type data terminal, single point sampling in which the same clock signal as the data rate is used and sampling is performed at the center of one bit of the received data is adopted. In this single-point sampling, a timing signal synchronized with the phase of received data is required.

[Conventional technology]

A data terminal device using a synchronous type HDLC procedure, for example, is connected to a synchronous line terminating device and transmits and receives data based on transmission and reception timing signals from this line terminating device. Further, since the line terminating device in the relatively low speed asynchronous transmission system or the relatively low speed synchronous transmission system which performs multipoint sampling does not have the function of generating the above-mentioned timing signal, the synchronous data terminal device is connected. Therefore, a timing generation circuit is provided when performing data transmission.

FIG. 4 is an explanatory diagram of a transmission system in which a master station 30 and a plurality of slave stations 40 are connected by an asynchronous line and data transmission is performed by a polling method. Reference numerals 31 and 41 denote synchronous data terminal devices, and 32. , 42, 52 are timing generation units, 3
3, 43, 53 are asynchronous line terminators, 34, 3
5,44,45,54,55 are interface parts, 3
6, 46 and 56 are transmission timing signal generation circuits, 37,
47 and 57 are reception timing signal generation circuits, and 51 is a line switching circuit. SD is transmission data, ST is a transmission timing signal, RD is reception data, and RT is a reception timing signal.

In the master station 30 and each slave station 40, since the asynchronous line terminators 33, 43, 53 do not have the function of generating reception timing signals, the timing generators 32, 42, 52 are provided to generate transmission timing signals. Data is transmitted based on the transmission timing signal ST from the circuits 36, 46 and 56, and the reception timing signal RT is generated from the reception data in the reception timing signal generation circuits 37, 47 and 57.
The reception processing of the reception data RD is performed based on the above. Further, another slave station is connected via the line terminating device 53.

A calling signal for sequentially calling a plurality of child stations 40 is transmitted from the parent station 30, and the child station 40 designated by the calling signal controls the line switching circuit 51 to transmit the data terminal device when transmission data exists. 41 is switched and connected to the upstream circuit. Further, the transmission timing signal ST from the transmission timing signal generation circuit 46 is applied to the data terminal device 41 via the interface section 44, and the transmission data SD is transmitted in accordance with the transmission timing signal ST.

The reception timing signal generation circuit 37 of the master station 30 generates a reception timing signal RT from the response signal transmitted from each slave station 40 via the uplink, and the reception timing signal RT is generated via the interface section 34. The signal RT and the reception data RD are transferred to the data terminal device 31.
The reception timing signal generation circuit 47 of the slave station 40 generates the reception timing signal RT from the signal transmitted from the master station 30 through the downlink, and reproduces and relays data in the interface section 44. At the same time, the reception timing signal RT and the reproduced data RD are transferred to the data terminal device 41. Further, the reception timing signal generation circuit 57 generates a reception timing signal from the signal transmitted from the lower child station via the uplink, and reproduces and relays the data in the interface section 54.

FIG. 5 is an explanatory diagram of a format of a signal transmitted between the master station and the slave station. (A) is a call signal transmitted from the master station 30 to the slave station 40, and (B) is the master station 30. Slave station 4 to receive
0 indicates a response signal from 0, and F is “0111111”, for example.
0 "flag, A is address information, C is control information, I is data, and FCS is a frame check sequence.

From the master station 30, a call signal designating the slave station 40 by the address information A is transmitted, and the flag F is used as a fill-in signal. When the slave station 40 is designated by the address information A of the calling signal, the slave station 40 is sandwiched by a plurality of leading flag groups F and one trailing flag F, and the address information A, the control information C, and the data I. And a frame check sequence FCS. And
When there is no response signal from each slave station 40, all marks (all "1") are displayed.

Since the master station 30 sends at least a signal that changes between "0" and "1" like the flag F, the generation of the timing signal is relatively easy.

However, the received signal from the slave station 40 in the master station 30 is
Since a plurality of flags F are added to the beginning of the response signal after the continuous "1", it is necessary to generate a timing signal based on this flag F and identify the subsequent address information A and the like.

FIG. 6 shows a block diagram of a conventional example for generating a timing signal from the above-mentioned response signal and the like. In the figure, 61
Is a flip-flop, 62 is a rising detection circuit, 63 is a falling detection circuit, 64 is an OR circuit, 65 and 66 are AND circuits, 67 and 68 are integrating circuits, 69 and 70 are comparing circuits, 7
1 is a variable frequency dividing circuit, 72 is a basic clock generator, 73 is an input terminal, 74 is a data output terminal, and 75 is a timing signal output terminal.

The received data is transferred from the input terminal 73 to the flip-flop 61.
Data terminal D and rising and falling detection circuits 62, 6
3, the basic clock signal of the basic clock generator 72 is frequency-divided by the variable frequency dividing circuit 71 and output as a timing signal, which is output from the output terminal 75 and added to the clock terminal CK of the flip-flop 61. To be This timing signal is controlled so as to be applied to the clock terminal CK of the flip-flop 61 at the central position of the data.

FIG. 7 is a diagram for explaining the operation of the conventional example, and (1) to (14) are the sixth.
The waveforms of an example of signals (1) to (14) having the same reference numerals in each part of the figure are shown. The received data (1) applied to the input terminal 73 is applied to the rising edge detection circuit 62 and the falling edge detection circuit 63, and the rising edge detection signal (2) and the falling edge detection signal (3) are combined with the OR circuit 64.
And becomes the edge detection signal (4). Variable frequency divider 7
The delayed phase signal (5) and the advanced phase signal (6) from 1 are the delayed phase of the pulse width of 1/4 bit and the 1/4 bit from the rising of the timing signal (13) output from the output terminal 75. It shows the lead phase of the pulse width of minute and is added to the AND circuits 65 and 66.

For example, a rising edge detection signal at time t1, t2, t3
When (2) is output within the pulse width of the delay phase signal (5), the AND circuit 65 outputs the delay phase detection signal (7) to the integrating circuit 67.
Added to. The integrating circuit 67 integrates the delayed phase detection signal (7) and adds the integrated output signal (9) to the comparison circuit 69. For example, at time 2, when the integrated output signal (9) exceeds a certain threshold value, The phase delay correction signal (1) becomes "1" and becomes "0" when it becomes less than the threshold value. While the phase delay correction signal (11) is "1", the frequency division ratio in the variable frequency dividing circuit 71 is controlled and the phase of the timing signal (13) is delayed.

When the falling detection signal (3) at times t5, t6, and t7 is output within the pulse width of the advance phase signal (6), the AND circuit 66 outputs the advance phase detection signal (8) and integrates it. Applied to circuit 68, the integrated output signal (10) is applied to comparison circuit 70. For example, at time t6, when the integrated output signal (10) exceeds a certain threshold value, the phase advance correction signal (12) becomes "1".
And becomes "0" when it becomes less than or equal to the threshold value. While the phase advance correction signal (12) is "1", the frequency division ratio in the variable frequency dividing circuit 71 is controlled and the phase of the timing signal (13) advances.

Therefore, the phase-controlled timing signal (13) is applied to the clock terminal CK of the flip-flop 61, and the received signal (1) applied to the data terminal D thereof is reproduced from the terminal Q to the output terminal 74 by the reproduced data signal ( It is output as 14).

[Problems to be Solved by the Invention]

The above-described conventional timing generation circuit integrates the phase delay detection signal (7) or the phase advance detection signal (8), and determines whether the integrated output signal (9) or (10) is equal to or more than a certain threshold value. Since the phase of the timing signal is controlled by the above, a certain amount of time is required until the timing signal phase-synchronized with the received data (1) is generated. Therefore, like the response signal shown in FIG. 5B, it is impossible to immediately generate the timing signal of the optimum phase by the flag F after all "1". Therefore, a method of repeatedly transmitting a plurality of flags F is adopted.

An object of the present invention is to forcibly optimize the phase of a timing signal by detecting a change point after a mark or space continuously for a predetermined number of bits or more, and to speed up synchronization pull-in. is there.

[Means for Solving the Problem] The timing generation circuit of the present invention will be described with reference to FIG. 1. The change point detection unit 1 outputs a detection signal which detects a rising edge and a falling edge of received data. This change point detection unit 1
A phase discriminating unit 2 for outputting a discriminating signal for discriminating the phase lag / advance of the timing signal based on the detection signal, the phase lag signal and the phase lead signal with respect to the timing signal,
The frequency division ratio of the basic clock signal is controlled according to the discrimination signal from the phase discrimination unit 2 to finely adjust the phase of the timing signal, and the forced synchronization correction signal is used to force the 1/2 bit position of the received data. The variable frequency dividing circuit 3 that outputs the first timing signal, and the received data is a mark or space continuously for a predetermined number of bits or more, and the change point detection unit 1
When a falling or rising detection signal is applied, the forced synchronization control unit 4 outputs a forced synchronization signal, and when the forced synchronization signal from the forced synchronization control unit 4 is within a predetermined phase range of the timing signal, the variable It is provided with a forced synchronization determination unit 5 that outputs a forced synchronization correction signal to be applied to the frequency dividing circuit 3.

[Action]

The phase discriminating unit 2 discriminates the relationship between the phases of the rising edge detecting signal and the falling edge detecting signal by the change point detecting section 1 and the phase of the timing signal to be output, and determines whether the timing signal is the lagging phase or the leading phase. Is determined and the determination signal corresponding thereto is applied to the variable frequency dividing circuit 3 to control the frequency division ratio of the variable frequency dividing circuit 3 to finely adjust the phase of the timing signal.

Further, when a space arrives after a mark having a predetermined number of bits or more, such as an all mark, or when a mark arrives after a space having a predetermined number of bits, the compulsory synchronization control unit 4 outputs a compulsory synchronization signal. Only when this forced synchronization signal is within the predetermined phase range of the timing signal, that is,
Only within a certain range before and after the rise of the timing signal,
A forcible synchronization correction signal is added to the variable frequency dividing circuit 3, and forcible control is performed so that the first timing signal is output from the forcible synchronization correction signal to the 1/2 bit position. Thereby,
A timing signal is output at approximately the center of the received data, and the received data can be immediately reproduced.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, 11 is D
Flip-flop, 12 is a rising detection circuit, 13 is a falling detection circuit, 14 is an OR circuit, 15 and 16 are AND circuits, 17 and 18 are JK type flip-flops, 19
Is a forced synchronization control circuit, 20, 21, 22 are AND circuits,
Reference numeral 23 is an OR circuit, 24 is a variable frequency dividing circuit, and 25 is a basic clock generator. The rising edge detection circuit 12 and the falling edge detection circuit 13 form a change point detection unit 1, the AND circuits 15 and 16 and the flip-flops 17 and 18 form a phase determination unit 2, and the forced synchronization control circuit 19 and the AND circuit. 20 configures the forced synchronization control unit 4, and the AND circuits 21 and 22 and the OR circuit 23 configure the forced synchronization determination unit 5.
Is configured.

This embodiment shows a case where forced synchronization is performed by detecting a change to a space ("0") after a series of six marks ("1"). Therefore, the forced synchronization control circuit 19
Counts up “1” of the received data a and outputs “0”
A counter for clearing is provided, and when six or more pieces of the reception data a of "1" are continuously input, the forced synchronization detection signal k is output. Then, the AND circuit 20 outputs the forced synchronization signal 1 at the timing of the falling detection signal c.

Also, since the delay phase signal e and the lead phase signal f having a pulse width in the range of 1/4 bit before and after the rise of the timing signal o are added to the AND circuits 21 and 22 from the variable frequency dividing circuit 24, the forced synchronization signal is generated. When l is within the range of the pulse width of the delayed phase signal e or the advanced phase signal f, the OR circuit 23
The forcible synchronization correction signal m is applied to the variable frequency dividing circuit 24 via the forcible synchronization.

Further, the rising detection signal b from the rising detection circuit 12 and the falling detection signal c from the falling detection circuit 13 become an edge detection signal d via the OR circuit 14, and the delayed phase signal e
The AND circuit 15 applies the phase lag detection signal g to the J terminal of the flip-flop 17 within the pulse width of, and the AND circuit 16 outputs the phase advance detection signal h during the pulse width of the lead phase signal f. Pin 18 J terminal. Further, the carry signal n from the variable frequency dividing circuit 24 is added to the K terminals of the flip-flops 17 and 18,
When the phase delay detection signal g is added to the timing of the carry signal n, the phase delay correction signal i is changed to the variable frequency dividing circuit 2
In addition to 4, the fine adjustment is performed so as to delay the phase of the timing signal. Further, when the phase advance detection signal h is added to the timing of the carry signal n, the phase advance correction signal j is added to the variable frequency dividing circuit 24, and fine adjustment is performed so as to advance the phase of the timing signal.

FIG. 3 is a diagram for explaining the operation of the embodiment of the present invention, in which (a) to (p)
Shows an example of the signals a to p of each part in FIG. 2, and when the received data a is shown in (a), the rising detection signal b and the falling detection signal c are shown in (b) and (c), respectively. Will be things. Therefore, the edge detection signal d from the OR circuit 14 is as shown in (d).

Further, the phase delay signal e and the phase advance signal f have a pulse width of 1/4 before and after the rising phase of the timing signal o of (o) as shown in (e) and (f). Further, for example, at time T1 when six "1" s of the received data a are continuously counted by the counter (not shown) of the forced synchronization control circuit 19,
The forced synchronization detection signal k becomes "1" as shown in (k),
When the received data a becomes "0" at time T2, the fall detection signal c is output as shown in (c) and the counter of the forced synchronization control circuit 19 is cleared, so that the forced synchronization detection signal k is also output. It becomes "0".

At this time, since the fall detection signal c is output in the period of "1" immediately before the fall of the forced synchronization detection signal k to "0", the AND circuit 20 outputs the forced synchronization signal l as shown by (1). Is output. By outputting the forced synchronization signal l within the pulse width of the delay phase signal e, for example, the forced synchronization correction signal m is transmitted via the AND circuit 21 and the OR circuit 23.
As shown in (o), the timing signal o output from the variable frequency divider 24 is output as shown in (m), and the timing signal o is forcibly forced to the time T.
It is controlled to rise at the timing of 3. That is, it becomes a timing signal that rises to a 1/2 bit state from the timing of the forced synchronization correction signal m, and thereafter becomes a timing signal o of a bit period.

Therefore, as shown in the response signal of FIG. 5B, when data from the designated slave station arrives after all "1" s are continuous, the timing signal o synchronized with the data immediately.
Can be output. Therefore, it is possible to correctly identify the received data even if the received data has one flag F added to the head.

When the edge detection signal d is output within the pulse width of the delay phase signal e at time T4, the phase delay detection signal g becomes
As shown in (g), J of flip-flop 17 is output.
The phase delay correction signal i applied to the Q terminal of the flip-flop 17 becomes "1" as shown in (i).
Further, as shown in (n), the carry signal n from the variable frequency dividing circuit 24 is output at the falling timing of the timing signal o, so that the phase delay correction signal i from the Q terminal of the flip-flop 17 is timed. It becomes "0" at T5. The frequency division correction signal i controls the frequency division ratio of the variable frequency division circuit 24, and the phase of the timing signal o is finely adjusted to be delayed.

When the edge detection signal d is output within the pulse width of the lead phase signal f at time T6, the phase lead detection signal h becomes
It is output as shown in (h) and added to the J terminal of the flip-flop 18, and the phase advance correction signal j from the Q terminal of the flip-flop 18 becomes "1" as shown in (j), and the next time It becomes "0" by the carry signal n of T7.
The phase advance correction signal j controls the frequency division ratio of the variable frequency divider circuit 24, and is finely adjusted so that the phase of the timing signal o advances.

Since the timing signal o controlled as described above is applied to the clock terminal CK of the flip-flop 11, the received data a applied to the data terminal D of the flip-flop 11 is reproduced data p shown in (p) from the Q terminal. Is output. That is, the timing signal having a predetermined phase relationship can be immediately output upon detection of the trailing edge to the space after the continuous mark.

The present invention is not limited to the above-described embodiments, and the gate circuits and the like of each unit may have other logical configurations. Although the case where the predetermined number of consecutive bits is 6 is shown, it is of course possible to use other values in consideration of the bit configuration of the flag F and the like.

〔The invention's effect〕

As described above, the present invention provides the forced synchronization control unit 4 and the forced synchronization determination unit 5 in the timing generation circuit that outputs the timing signal by dividing the basic clock signal by the variable frequency dividing circuit 3. , The reception data is a mark or a space continuously for a predetermined number of bits or more, and when the falling point or the rising edge of the reception data is detected by the change point detection unit 1, a forced synchronization signal is output, and this forced synchronization signal is a timing signal. When within the predetermined phase range, the forced synchronization correction signal is added to the variable frequency dividing circuit 3 and forced control is performed so that the first timing signal is output at the 1/2 bit position. Therefore, it is possible to immediately generate a timing signal that enables single-point sampling, and thus it is possible to generate a timing signal that is synchronized with the received data at high speed.

Also, a synchronization flag or response signal that becomes "1" continuously for a predetermined number of bits or more is detected, and when a rising edge detection signal is added, a forced synchronization signal is output, and further, this forced synchronization signal is timed. When the signal is in a predetermined phase range, the variable frequency divider circuit 3 is forcedly synchronized by adding a forcible synchronization correction signal, so that the phase change of the timing signal due to the forcible synchronization is predetermined without being affected by noise. Since it can be limited within the range, there is an advantage that the timing signals can be synchronized at high speed and stably.

[Brief description of drawings]

1 is an explanatory view of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is an operation explanatory view of the embodiment of the present invention,
FIG. 4 is an explanatory diagram of a transmission system, FIG. 5 is an explanatory diagram of a transmission format, FIG. 6 is a block diagram of a conventional example, and FIG. 7 is an operation explanatory diagram of a conventional example. Reference numeral 1 is a change point detection unit, 2 is a phase determination unit, 3 is a variable frequency dividing circuit, 4 is a forced synchronization control unit, and 5 is a forced synchronization determination unit.

Claims (1)

[Claims] 1. A change point detecting section (1) for outputting a detection signal detecting rising and falling of received data, a detection signal of the changing point detecting section (1), and a phase delay signal with respect to a timing signal. A phase discrimination unit (2) that outputs a discrimination signal that discriminates the phase advance of the timing signal based on the phase advance signal, and frequency division of the basic clock signal according to the discrimination signal from the phase discrimination unit (2). A variable frequency dividing circuit (3) for controlling the ratio to finely adjust the phase of the timing signal and forcibly outputting the first timing signal to the 1/2 bit position of the received data by the forced synchronization correction signal. And a mark (or space) of the received data is detected to be continuous for a predetermined number of bits or more, and when a falling (or rising) detection signal is added from the change point detection unit (1), a forced synchronization signal The forced synchronization control unit (4) for outputting, and the forced synchronization correction signal when the forced synchronization signal from the forced synchronization control unit (4) is within a predetermined phase range of the timing signal. And a forced synchronization determination unit (5) added to the timing generation circuit.