JPH0620275B2 - Solid-state imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device suitable for use in a color video camera or the like, and more particularly, to a signal charge of two lines simultaneously by a plurality of charge transfer elements. The present invention relates to a two-line simultaneous read-out solid-state imaging device for horizontal transfer.

[Background of the Invention]

Conventionally, a large number of photoelectric conversion elements arranged two-dimensionally in the horizontal and vertical directions on the light receiving surface and signal charges are simultaneously transferred from these photoelectric conversion elements during the vertical blanking period, and one stage is provided for each horizontal blanking period. A plurality of charge transfer elements for transferring these signal charges in the vertical direction and a row of photoelectric conversion elements in the horizontal direction are used as lines, and the signal charges are supplied line by line from these charge transfer elements and are simultaneously supplied in the horizontal direction. 2. Description of the Related Art There is known a solid-state imaging device that includes two charge transfer elements that transfer data charges to two lines and simultaneously reads out signal charges for each two lines. In this case, a CCD is usually used as the charge transfer element, and the photoelectric conversion element is a photodiode. Less than,
A charge transfer device that transfers signal charges in the horizontal direction is provided with a horizontal CC.
D, a charge transfer element that transfers signal charges in the vertical direction will be referred to as a vertical CCD.

In such a solid-state image pickup device, a color signal can be obtained by providing a predetermined color filter for each photoelectric conversion element and providing each with a predetermined spectral sensitivity. An example thereof is disclosed in Japanese Patent Laid-Open No. 59-169278, and means for visually reducing smear, which is a phenomenon peculiar to a solid-state imaging device, is provided.

However, in such a two-line simultaneous readout solid-state imaging device, since two horizontal CCDs are used, there is a problem that color flickering occurs and color reproducibility is deteriorated.
Hereinafter, such a problem will be described with reference to FIG.

In the figure, photoelectric conversion elements 1 each provided with a predetermined color filter are two-dimensionally arranged in the horizontal direction (horizontal direction in the drawing) and the vertical direction (also vertical direction). Here, A, B, C and D respectively represent different color filters. When the row of the photoelectric conversion elements 1 in the horizontal direction is called a line, as shown in the figure, the photoelectric conversion element 1 provided with the color filter A and the photoelectric conversion element 1 provided with the color filter C are provided in odd-numbered lines. Are alternately arranged, and in the even-numbered lines, the photoelectric conversion elements 1 provided with the color filters B and the photoelectric conversion elements 1 provided with the color filters D are alternately arranged.

When the signal charges are read from the photoelectric conversion elements 1 arranged in this way, the signal charges of the line 1 are simultaneously transferred to the horizontal CCD 4 and the signal charges of the line 2 are simultaneously transferred to the horizontal CCD 5 within the horizontal blanking period. Then, the signal charges of the horizontal CCDs 4 and 5 are sequentially transferred in the horizontal direction within the next horizontal scanning period.

Next, similar signal charges are read out for the lines 3 and 4, and thereafter, signal charges are read out for every two lines in the same manner. And the line (n
-1) and the reading of the signal charges of the line n are completed, the reading of the signal charges in one field is completed.

Therefore, in this field, the signal output from the horizontal CCD 4 to the output terminal 6 is composed of the signal charges read from the odd-numbered lines, and the color filters A, B, and
When the signal charges of the photoelectric conversion element 1 provided with C and D are expressed as A, B, C, and D charges, respectively, it is a signal in which A charges and C charges are alternately arranged. The signal output from the horizontal CCD 5 to the output terminal 6 is a signal in which B charges and C charges read from the even-numbered lines are alternately arranged. Here, assuming that the signals consisting of A, B, C, and D charges are A, B, C, and D signals, respectively, an (A + C) signal in which the A signal and the C signal are mixed is obtained at the output terminal 6. At the output terminal 7, a (B + D) signal in which the B signal and the D signal are mixed is obtained.

These signals are supplied to a processing circuit (not shown) so that A,
After the B, C and D signals are separated, predetermined signals are added together to generate a luminance signal and a primary color signal (or a color difference signal).

In the next field, the combination of two lines simultaneously transferred in the horizontal direction by the horizontal CCDs 4 and 5 can be changed. That is, first, the signal charge of the line 1 is sent to the horizontal CCD 5 and transferred in the horizontal direction. As a result, the output terminal 7
A signal (A + C) is obtained at. In the next horizontal period (= horizontal retrace period + horizontal scanning period), the signal charge of line 2 is transferred to the horizontal CCD 4 and the signal charge of line 3 is transferred to the horizontal CCD 5 at the same time. Thereafter, in the same manner, two lines are horizontally transferred by the horizontal CCDs 4 and 5.

As a result, the (B + D) signal is obtained at the output terminal 6,
An (A + C) signal is obtained at the output terminal 7.

Therefore, according to such a signal charge reading operation, for example, when an (A + C) signal is obtained at the output terminal 6 and a (B + D) signal is obtained at the output terminal 7 with odd fields, in the even field, conversely, (B + D) is obtained at the output terminal 6. ) Signal is obtained,
The (A + C) signal is obtained at the output terminal 7, and the signal due to the signal charge of the photoelectric conversion element 1 having the spectral sensitivity different for each field is obtained at the output terminals 6 and 7.

On the other hand, for example, as disclosed in Japanese Patent Laid-Open No. 59-169281, the output units 10 and 11 of the horizontal CCDs 4 and 5 are disclosed.
Generally, a source follower circuit is used for
The signal charges transferred at D4 and D5 are converted into voltages. By the way, in such a source follower circuit, due to factors in the semiconductor manufacturing process (for example, mask shift, non-uniformity of semiconductor substrate, etc.), the capacitance of its input portion, the threshold voltage (V _T ) of the MOS transistor used for it, and The conductance (g _m ) varies, and as a result, the output units 10, 11 of the horizontal CCDs 4, 5 are
There will be a difference in gain.

Therefore, as described above, the horizontal CCD 4 with an odd field
(A + C) signal is obtained from the output unit 10 of the horizontal CCD 5 to the output terminal 6 and the (B + D) signal is obtained from the output unit 11 of the horizontal CCD 5 to the output terminal 7 of the horizontal CCD 5. The (B + D) signal is output from the output section 10 to the output terminal 6, and the (A + D) signal is output from the output section 11 of the horizontal CCD 5 to the output terminal 7 (A +
When the signal C) is obtained, the signals A, B, C and D alternately pass through the output units 10 and 11 having different gains for the respective fields. For this purpose, the output units 10, 1
If the gain of 1 is α and β, respectively, these A, B, C,
For example, the signal amount of an R (red) signal generated from the D signal is βR with an even field, where αR is an odd field.
And will be different for each field.

This also applies to other generated primary color signals or color difference signals. As a result, the color reproducibility differs for each field, so-called color flickering occurs, and the image quality of the reproduced image deteriorates.

[Object of the Invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a solid-state image pickup device which solves the above-mentioned problems of the prior art and eliminates color flickers due to a gain difference between horizontal CCD output units and can improve the image quality of a reproduced image. .

[Outline of Invention]

In order to achieve this object, the present invention is characterized in that the signal charges of the photoelectric conversion elements having the same spectral sensitivity are always transferred in the same horizontal CCD in each field.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a solid-state image pickup device according to the present invention, in which 1 is a photodiode, 2 is a MOS switch, 3 is a vertical CCD, 4 and 5 are horizontal CCDs, 6 and 7 are output terminals, 8, 9 are transfer gates, 10 and 11 are output sections, 1
2 to 19 are input terminals.

In the figure, the photodiode 1 is horizontally and vertically 2
They are arranged in a dimension and are each provided with a color filter as shown in FIG. A MOS switch 2 is connected to each photodiode 1. A vertical CCD 3 is arranged for each column of photodiodes 1 in the vertical direction. The every other stage S _VA vertical CCD 3, MOS switch 2 of the same photodiode 1 column is connected. The MOS switches 2 on every other line are controlled by the "H" (high level) transfer pulse φ _PA from the input terminal 12, and the other MOS switches 2 on every other line are H "from the input terminal 13. is by connexion controls the transfer pulses phi _PB of. Furthermore, in the every stage S _VA of MOS switch 2 of each vertical CCD3 is connected, clock phi _VA of "L" from the input terminal 14 (low) but, MOS switch 2 is the connection which do not other every stage S _VB, clock phi _VB of "H" from the input terminal 15 is supplied respectively at the same time.

The final stage S _VA of each vertical CCD 3 is connected via the transfer gate 9 to every other stage S _HA of the horizontal CCD 5, and each of these stages S _HA is connected via the transfer gate 8 to one of the horizontal CCDs 4. It is connected to every other stage _S'HA . The transfer gate 9 is supplied with the “H” transfer pulse φ _TB from the input terminal 16, and the transfer gate 8 is supplied with the “H” transfer pulse φ _TA from the input terminal 17. Also, every other stage S of the horizontal CCD4,5 _'HA, the S _HA, the clock phi _HA of "L" from the input terminal 18 is supplied, the other alternate stage S' _HB, S _HB
Is supplied with the clock φ _HB of “H” from the input terminal 19.

Here, it is assumed that each photodiode 1 is provided with color filters A, B, C, D so as to have the arrangement shown in FIG. 11, and each photodiode 1 is provided for each position and for each provided color filter. When distinguished, it is shown as in FIG. In FIG. 2, A _ij is the j-th photodiode on the line i provided with the color filter A, and will be referred to as B _{(i + 1) j} , C _{i (j + 1)} and D _{(i + 1 )} below. _{) (j + 1)} is the same. Also, the signal charge generated in the photodiode 1 is
For simplification of description, the same reference numeral such as A _ij will be used.

Next, the operation of this embodiment will be described with reference to FIGS.

In one field (here, an odd field), the transfer pulse φ _PA of “H” is supplied from the input terminal 12 in the vertical blanking period and every other line (here, an odd-numbered line). Yes) MOS switch 2 is turned on. As a result, the photodiodes 1 of these lines are
The signal charges are transferred from each to the corresponding stage S _VA of the vertical CCD 3. Looking at the n-th vertical CCD ₃ at time t ₁ associated with such an operation, the state shown in FIG. 4 (a) is obtained.

In addition, the signal charge in the n-th vertical CCD 3 is represented as a representative, and the signal charges in the odd-numbered lines are represented by A _1n , A _3n ,.
The signal charges of the even-numbered lines are set to B _2n , B _4n , B _6n , ...
As described below.

Next, the transfer pulse φ _{PB of} H ″ is supplied from the input terminal 13, and the MOS switches 2 of even-numbered lines are turned on.
As a result, the signal charges of these lines are transferred to every other stage S _VA of the vertical CCD 3. Therefore, at time t ₂ associated with this operation, as shown in FIG. 4 (b), the vertical CCD 3 has the final stages S _VA to A _1n , B _2n , A _3n , ... Signal charge is stage S _VA
Stored in.

At this time, the transfer pulse φ of “H” from the input terminal 16
_TB is supplied, and the transfer gate 9 is in the ON state with low potential.

In this state, the vertical blanking period ends, and the input terminal 14 is supplied with the clock φ _VA of "L" and the input terminal 15 is supplied with the clock φ _VB of "H" in the horizontal blanking period. This allows
Since the potential of the stage S _VA of each vertical CCD 3 rises and the potential of the stage S _VB falls, the A _1n charges of the final stage S _VA are transferred to the stage S _HA of the horizontal CCD 5 via the transfer gate 9, respectively. The signal charges of the other stages S _VA are transferred to the next stage S _VB . Therefore, the A _1n charge of the line 1 is stored in the stage S _HA of the horizontal CCD 5. Next, when the clocks φ _VA and φ _VB disappear, the potential of the stage S _VA falls and the potential of the stage S _VB rises, whereby the signal charge of each stage S _VB is transferred to the next stage S _VA . To be done. At the same time, the transfer pulse φ _TA of “H” is supplied from the input terminal 17, and the clock φ _HA of “L” is supplied from the input terminal 18, whereby the horizontal C
Stage S _'HA of CD4,5, Potenshiyaru of S _HA is increased. In this case, the raised potential of the stage S ′ _HA of the horizontal CCD 4 is configured to be lower than the lowered potential of the transfer gate 8, whereby the line stored in the stage S _{HA of the} horizontal CCD 5 is stored. A _1n charge of ₁ is transferred to the stage S ′ _HA of the horizontal CCD 4 via the transfer gate 8.

When the transfer of the signal charge is completed, the clock φ _HA and the transfer pulse φ _TA are eliminated, the potential of the stage S ′ _HA of the horizontal CCD 4 is lowered and the potential of the transfer gate 8 is raised, and the transfer gates between the horizontal CCDs 4 and 5 are transferred. Isolated by 8. At the same time, the clock φ _VA of “L” is input from the input terminal 14, and the clock φ _{VB of} “H” is input from the input terminal 15.
Are supplied respectively, and the potentiometer of the stage S _VA of each vertical CCD 3 rises and the potentiometer of the stage S _VB descends. As a result, the B _2n charges of the line 2 stored in the final stage S _VA of the vertical CCD 3 are transferred to the stage S _{HA of the} horizontal CCD 5 via the transfer gate 9, and are stored in the other stages S _VA. Signal charges of 3 or less are transferred to the next stage S _VB . When these clocks φ _VA and φ _VB disappear, the stage S of the vertical CCD 3
The potential of _HA drops and the potential of stage S _VB rises, and the signal charge of stage S _VB is transferred to stage S _VA .

In this way, the A _1n charge of the line 1 is stored in the horizontal CCD 4 and the B _2n charge of the next line 2 is stored in the horizontal CCD 5 within the horizontal blanking period. After that, input terminal 16
After the transfer pulse φ _TB of “H” from is disappeared, the potential of the transfer gate 9 rises and turns on, and the horizontal CCD 5
And each vertical CCD 3 are isolated.

The above operation is performed in the horizontal blanking period, as shown in FIG. 4 (c), at time t _3, the n-th stage S _'HA horizontal CCD 4, A _1n stored charge line 1 , N 2nd stage S _HA of the horizontal CCD 5 has B _{2n of} line 2
The charge is stored.

Next, the input terminals 18 and 19 are provided for one horizontal scanning period.
The clocks φ _HA and φ _HB are simultaneously supplied from the device in a predetermined cycle, and the signal charges are sequentially transferred horizontally in stages in the horizontal CCDs 4 and 5. As a result, the (A + C) signal due to the signal charge of line 1 is obtained from the output section 10 to the output terminal 6, and the (B + D) signal due to the signal charge of line 2 is obtained from the output section 11 to the output terminal 7.

Next, in the horizontal blanking period, similarly, A _3n charges on line 3 are transferred to the horizontal CCD 4 and B _4n charges on line 4 are transferred to the horizontal CCD.
5, and each of them is transferred in the horizontal direction during the horizontal scanning period. In this way, the signal charges are read out every two lines, and the (A + C) signal is obtained at the output terminal 6 and the (B + D) signal is obtained at the output terminal 7.

When all the signal charges of the vertical CCD 3 are read and the vertical retrace period of the next even field is entered, a transfer pulse φ _TB of “H” is supplied from the input terminal 16 to turn on the transfer gate 9, and this state is set. Then, the transfer pulse φ _PA of “H” is supplied from the input terminal 12 and the MOS switch 2 of the odd-numbered line is
Turns on. Thus, the odd-numbered signal charges of the photodiode 1 of the line are transferred to the stage S _VA vertical CCD 3. The state at time t ₄ accompanying this operation is shown in FIG.
Shown in (d).

Next, by supplying the clocks φ _VA and φ _VB from the input terminals 14 and 15, as described above, the vertical CCD
A _1n charge on line 1 of the final stage S _VA of 3 is horizontal CC
While being transferred to the stage S _HA of D5, the signal charges on and after line 3 are transferred to the next stage S _VA . In this state, the transfer pulse φ _TA is supplied from the input terminal 17 to turn on the transfer gate 8 and the clock φ _HA is supplied from the input terminal 18, so that the A _1n charges on the line 1 of the horizontal CCD 5 are transferred to the stage S ′ of the horizontal CCD 4. Transferred to _HA . Then, the clocks φ _VA and φ _VB are supplied from the input terminals 14 and 15, whereby the signal charges of the vertical CCD 3 are transferred to the next stage S _VA , respectively. After that, the transfer gate 9 is turned off when the transfer pulse φ _TB from the input terminal 16 disappears.

At time t ₅ after the above operation, as shown in FIG. 4 (e), the A _1n electric charge of the line 3 is stored in the final stage S _VA of the vertical CCD 3, and the odd-numbered lines after the line 5 are stored. The signal charges of the line are stored in every other stage S _VA .

Next, the clocks φ _HA and φ _HB are simultaneously supplied in a predetermined cycle from the input terminals 18 and 19, and the line 1 is fed in the horizontal CCD 4.
A _1n charges of are transferred in the horizontal direction. As a result, the (A + C) signal due to the signal charge of the line 1 is obtained at the output terminal 6.

When the horizontal transfer is completed, the transfer pulse φ _TB is supplied from the input terminal 16 and the transfer gate 9 is turned on. In this state, the transfer pulse φ _PB is supplied from the input terminal 13 to turn on the MOS switches 2 of even-numbered lines. It was but connexion, the even-numbered signal charges of the photodiode 1 of the line are transferred to the stage S _VA empty section of vertical CCD 3.

The state at time t ₆ at this time is shown in FIG. 4 (f). As is clear from the figure, after line 2, the order in the vertical CCD 3 is reversed every two lines.

The above operation is performed within the vertical blanking period. Next, in the horizontal blanking period, the clocks φ _VA and φ _VB are supplied from the input terminals 14 and 15, and the terminal stage S of the vertical CCD 3 is terminated.
With A _3n charge line 3 in _VA is transferred to the stage S _HA horizontal CCD5 through the transfer gate 9, the signal charges of the other lines in the other stages S _VA is transferred to the next stage S _VA. By this, B _{2n of} line 2
Charge is accumulated in the final stage stage S _VA of vertical CCD3.

Next, the transfer pulse φ _TA is supplied from the input terminal 17 to turn on the transfer gate 8, and the clock φ _HA is supplied from the input terminal 18. As a result, the A _3n electric charge of the line 3 stored in the stage S _HA of the horizontal CCD 5 becomes a horizontal CC.
It is transferred to the stage S _'HA of D4. Then, the clocks φ _VA and φ _VB are again supplied from the input terminals 14 and 15, and the B _2n charges of the line 2 stored in the final stage S _VA of the vertical CCD 3 are transferred to the stage S _{HA of the} horizontal CCD 5. . At the same time, other stages of the vertical CCD3 S _VA
Is transferred to the next stage S _VA, and the A _5n charge of the line 5 is stored in the final stage S _VA .

The above operation is carried out within the horizontal blanking period, and the state at time t ₇ accompanying this is as shown in FIG. 4 (g). Then, the clocks φ _HA and φ _HB are sequentially supplied from the input terminals 18 and 19, so that in the horizontal CCD 4,
_{The 3n} charges and the B _2n charges of the line 2 are horizontally transferred to the horizontal CCD 5, respectively. Similarly, the signal charges are transferred in the horizontal direction by the horizontal CCDs 4 and 5 every two lines in each horizontal scanning period.

According to the above operation, even at the even field, the horizontal C
The signal charges of the odd-numbered lines are transferred to the CD 4 and the signal charges of the even-numbered lines are transferred to the horizontal CCD 5, respectively, whereby the (A + C) signal is output to the output terminal 6 and the (B + D) signal is output to the output terminal 7. The signals will be obtained respectively.

Therefore, regardless of whether it is an odd field or an even field, the (A + C) signal is always output from the output unit 10 of the horizontal CCD 4.
The (B + D) signal obtained from the output unit 1 of the horizontal CCD 5
Since the A, B, C, and D signals are always obtained from the fixed output units 10 and 11, even if there is a gain difference between the output units 10 and 11, the odd and even numbers are obtained. There is no difference in the color reproducibility of the color signal between the fields, so that no color flickering occurs.

FIG. 5 is a block diagram showing another embodiment of the solid-state imaging device according to the present invention, in which 12 'is an input terminal, 20 is a transfer gate, and 21 is an input terminal. The same reference numerals are given and duplicate description is omitted.

In this embodiment, the signal charges of all the photodiodes are read out to the vertical CCD at the same time in every vertical retrace period, but when the signal charges are transferred from the vertical CCD to the horizontal CCD at every other field, the signals of two lines are transferred. The sequence of charges is inverted.

The operation of this embodiment will be described below with reference to the timing chart of FIG. 6 and FIG.

Now, at a time t ₁ within a vertical blanking period of a certain field (here, an odd field), the input terminal 1
When transfer pulse φ _P is supplied from 2 ', all MOS
The signal charges of all the photodiodes 1 are transferred to the stage S _VA of corresponding vertical CCD3 switch 2 is turned on. As a result, as shown in FIG. 7 (a), in each vertical CCD 3, signal charges are stored in the order of lines 1, 2, 3, ... From the final stage S _VA to the sequential stages S _VA. To be

After the elapse of the vertical blanking period, first, at time t ₂ , the transfer pulse φ _TB is supplied to the input terminal 16 to turn on the transfer gate 9, and at the same time, the clocks φ _VA and φ _VB are supplied from the input terminals 14 and 15. At this time, the transfer pulse φ _TC of “H” is not supplied from the input terminal 21, and the potential of the transfer gate 20 is higher than that of the transfer gate 9. For this,
The A _1n charges on the line 1 of the final stage S _VA of the vertical CCD 3 are transferred to the transfer gate 9 (FIG. 7 (b)), but are not transferred to the transfer gate 20 and the stage S of the horizontal CCD 5 is transferred.
Transferred to _HA . At the same time, the signal charges of the other lines of the vertical CCD 3 are transferred to the next stage S _VB .

When the clocks φ _VA and φ _VB from the input terminals 14 and 15 disappear, the signal charges after the line 2 of the vertical CCD 3 are further transferred to the next stage S _VA , and at the time t ₃ , the input terminal 17
Turned on and the transfer gate 8 is supplied with transfer pulses phi _TA from by clock phi _HA is supplied from the input terminal 18, as shown in FIG. 7 (c), stored in stage S _HA horizontal CCD5 A _1n charge on line 1 was horizontal CC
Transferred to stage S and _{HA of} D4.

Next, at time t ₄ , the transfer pulse φ _{TB is} input again from the input terminal 16.
Is supplied to turn on the transfer gate 9, and the input terminal 1
Clocks φ _VA and φ _VB are supplied from 4 and 15. As a result, as shown in FIG. 7 (d), the B _2n charge of the line 2 in the final stage S _VA of the vertical CCD 3 is transferred to the transfer gate 9, but the transfer pulse φ _TC from the input terminal 21. Is not supplied to the horizontal CCD 5
_Is transferred to stage S _HA . Along with this, vertical CC
At D3, the signal charges after line 3 are transferred to the next stage S _VB.
However, when the transfer pulse φ _TB from the input terminal 16 and the clocks φ _VA and φ _VB from the input terminals 14 and 15 disappear (time t ₅ ), these signal charges are further transferred to the next stage S _VA . To be done. As a result, as shown in FIG. 7 (e), the A _1n charges on the line 1 are transferred to the horizontal CCD 4 in the horizontal C
CD5 B _2n charge line 2 is respectively stored in the, in each vertical CCD 3, lines 3, 4, 5 sequential stages S _VA from the final stage, the signal charge is stored in the order of ....

The series of operations shown in FIGS. 7 (b) to 7 (e) are performed within the horizontal retrace line period, and in the next horizontal scanning period, the input terminal 1
Horizontal CCD from the clocks φ _HA and φ _HB from 8 and 19
At 4, the A _1n charges of the line 1 are transferred in the horizontal direction, and at the horizontal CCD 5, the B _2n charges of the line 2 are transferred in the horizontal direction. The operation in the horizontal period is simultaneously performed on the signal charges of two lines, whereby the (A + C) signal by the signal charges of the odd-numbered lines is obtained at the output terminal 6, and the even-numbered signal is output at the output terminal 7. A (B + D) signal is obtained by the signal charge of the line.

Next, the operation in the even field will be described.

Also in this case, in the vertical blanking period, the signal charge of all the photodiodes 1 is transferred to the corresponding stage S _VA of the vertical CCD 3 by the transfer pulse φ _P from the input terminal 12 ′ (time t ₆ ). Figure 7 (f)). Then, within the same vertical blanking period, the A _1n charges of the line 1 stored in the final stage S _VA of the vertical CCD 3 are transferred to the stage S ′ _HA of the horizontal CCD 4 in the same manner as the above operation in the odd field. (Time t ₇ ; FIG. 7 (g)). Thereafter, the clocks φ _HA and φ _HB are sequentially supplied from the input terminals 18 and 19, and the A _1n charges of the line 1 are horizontally transferred by the horizontal CCD 4.

The above operation is performed within the vertical blanking period, and when this vertical blanking period ends, the next operation is performed during the horizontal blanking period.

As shown in FIG. 7 (g), the transfer pulse φ _TC of “H” is supplied from the input terminal 21 while the B _2n charge of the line 2 is stored in the final stage S _VA of the vertical CCD 3. As a result, the transfer gate 20 is held in the low potential state. In this state, transfer pulse φ from input terminal 16
_TB is supplied and the potential of the transfer gate 9 is lowered. Along with this, the clock φ from the input terminals 14 and 15
_VA and φ _VB are supplied, and the final stage S of the vertical CCD 3
The B _2n charge on line 2 at _VA is stored in transfer gate 9. Further, in the vertical CCD 3, the signal charges of the other lines are transferred to the next stage S _VA, and the A _3n charges of the line 3 are stored in the final stage S _VA . Next, the transfer pulse φ _TB from the input terminal 16 is eliminated and the transfer gate 9 is removed.
The potentiometer of rises and the input terminal 18
The clock φ _HA is supplied from this, and the potential of the stage S _HA of the horizontal CCD 5 rises. As a result, the B _2n charges of the line 2 stored in the transfer gate 9 are transferred to the horizontal CCD.
It is transferred to the transfer gate 20 and stored instead of the stage S _HA of stage 5.

Next, the transfer pulse φ _TB is supplied from the input terminal 16 to lower the potential of the transfer gate 9, and the “L” clock φ _VA is supplied from the input terminal 14 to supply the vertical CC.
Potenshiyaru of stage S _VA of D3 is increased. At this time, since the clock φ _VB of “H” is not supplied from the input terminal 15, the potential of the stage S _VB of the vertical CCD 3 is high, and therefore the transfer is possible only at the final stage S _VA of the vertical CCD 3. After that, the A _3n charge of the line 3 is stored in the transfer gate 9.

Based on the above, the resulting state at time t ₈ is shown in FIG. 7 (h).

When the transfer pulse φ _TB disappears from the input terminal 16 and the potential of the transfer gate 9 rises, at this time, since there is no clock φ _HA from the input terminal 18 and the potential of the stage S _HA of the horizontal CCD 5 is low, The A _3n charge of a certain line 3 is transferred to the stage S _{HA of the} horizontal CCD 5. Then, the transfer pulse φ _TA is supplied from the input terminal 17, the transfer gate 8 is turned on, and the clock φ _HA is supplied from the input terminal 18, so that the stage S _HA of the horizontal CCD 5 is located as described above. Line 3 A _3n
Charge is transferred to the stage S _'HA horizontal CCD 4.

The state at time t ₉ by such operation is shown in FIG. 7 (i).

Next, the transfer pulse φ _TC from the input terminal 21 disappears and the potential of the transfer gate 20 rises. Then, the transfer pulse φ _TB is supplied from the input terminal 16 to transfer the transfer gate φ _TC.
The potency of is reduced. Therefore, the transfer gate 2
The B _2n charge on line 2 at 0 is transferred to transfer gate 9. Then, as the transfer pulse φ _TB from the input terminal 16 disappears, the potential of the transfer gate 9 rises,
Further, at this time, since the clock φ _HA is not supplied from the input terminal 18, the potential of the stage S _HA of the horizontal CCD 5 is low, so that the B _2n charge of the line 2 is transferred from the transfer gate 9 to these stages S _HA. .

Along with this, the clock φ _VA from the input terminals 14 and 15
φ _VB is supplied, and the signal charges after the line 4 on the stage S _{VA of the} vertical CCD 3 are transferred to the next stage S _VA ,
The B _4n charge of line 4 is stored in the final stage S _VA .

The state at time t ₁₀ resulting from such an operation is shown in FIG. 7 (j).

The operations shown in FIGS. 7 (h) to 7 (j) are performed in the horizontal blanking period, and during the next horizontal scanning period, the A _3n charges of the line 3 are supplied to the horizontal CCD 4 and the B _2n charges of the line 2 are supplied to the horizontal CCD 5, respectively. It is transferred horizontally.

Similarly, every four horizontal blanking periods, the lines 4 and 5, the lines 6 and 7, ... And the two lines are inverted in the arrangement order of the signal charges shown in FIGS. 7 (h) to 7 (j). Be done. This allows
The horizontal CCD 4 obtains an (A + C) signal based on the signal charges of the odd-numbered lines, and the horizontal CCD 5 obtains a (B + D) signal based on the signal charges of the even-numbered lines.

From the above description of the operation, at odd and even fields, the (A + C) signal is obtained at the output terminal 6 and the (B + C) signal is obtained at the output terminal 7. Therefore, also in this embodiment, the same effect as that of the embodiment shown in FIG. 1 can be obtained.

FIG. 8 is a constitutional view showing still another embodiment of the solid-state imaging device according to the present invention, in which 22 and 23 are input terminals,
The parts corresponding to those in FIG. 5 are designated by the same reference numerals.

The embodiment shown in FIG. 5 has a horizontal CCD 5 and a vertical gate 3.
, And a transfer gate is added between the two lines, and the order of signal charges to the horizontal CCD is reversed between two lines to be transferred in the horizontal direction at the same time. In this embodiment shown in FIG. Is performed by a horizontal CCD.

In FIG. 8, the horizontal CCDs 4 and 5 are driven by four types of H ″ clocks φ _HA , φ _HB , φ _HC , and φ _HD . In each horizontal CCD 4 and 5, every four stages are arranged. different clock supplied to the stage S _'HA, S _HA
Clock φ _HA is in the, stage S _'HB, the clock φ _HB in the S _HB, stage S' _HC, the clock φ _HC in the S _HC,
Clocks φ _HD are supplied to the stages S ′ _HD and S _HD , respectively. Further, the horizontal CCD 4 is arranged two stages away from the horizontal CCD 5 in the signal charge transfer direction. Therefore, if the signal charges are transferred from each vertical CCD 3 to the stage S _{HA of the} horizontal CCD 5, Signal charge transfer from the CCD 5 to the horizontal CCD 4 is performed from the stage S _HA to which the clock φ _{HA of the} horizontal CCD 5 is supplied.
The clock φ _HC is supplied to the stage S ′ _HC .

In FIG. 8, the transfer gates 8 and 9 shown in FIGS. 1 and 5 are omitted for the sake of simplicity.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG. 9 and FIG.

First, in the vertical blanking period of one field period (here, an odd field period), the transfer pulse φ _P from the input terminal 12 ′ is the same as in the embodiment shown in FIG.
Thus, the signal charges of all the photodiodes 1 are transferred to the corresponding stage S _VA of the vertical CCD 3 (time t ₁₎ .
Fig. 10 (a)). Then, during the horizontal blanking period after the vertical blanking period has elapsed, the clock of "H" is supplied from the input terminals 18 and 22 to cause the stage S'of the horizontal CCDs 4 and 5 to operate.
The potentials of _HC and S _HA decrease, and along with this, the clocks φ _VA and φ _VB are supplied from the input terminals 14 and 15,
Line 1 A on the final stage S _VA of the vertical CCD 3
_1n charge is transferred to the horizontal CC via the stage S _{HA of the} horizontal CCD 5.
It is transferred to the stage S _'HC of the D4. Also a vertical CCD
The signal charge of the other stage S _VA of 3 is transferred to the next stage S _VA, and the B _2n charge of the line 2 is stored in the final stage S _VA .

The state at time t ₂ associated with this operation is shown in FIG. 10 (b).

Next, the clock φ _HA is supplied only from the input terminal 18,
The potential of the stage S _HA of the horizontal CCD 5 is lowered. Along with this, the clock φ from the input terminals 14 and 15
_VA and φ _VB are supplied, and the final stage S of the vertical CCD 3
The B _2n charge on line 2 at _VA is transferred to the stage S _{HA of the} horizontal CCD 5. Further, the signal charges of the other stages S _VA vertical CCD3 is transferred to the next stage S _VA, A _3n charge line 3 to the stage S _VA final stage is stored.

The state at time t ₃ associated with this operation is shown in FIG. 10 (c).

Next, the clock φ _HD is supplied only from the input terminal 23.
As a result, the stage S _'HD of horizontal CCD4,5, S _HD
Of the horizontal CCD, the horizontal CCDs 4, 5
'Since the Potenshiyaru of _HC, S _HA high, in the horizontal CCD 4, the stage S' of the stage S line 1 in _HC
A _1n electric charge of is transferred to the next stage S ′ _HD , and the horizontal C
In CD5, B _{2n of} line 2 on stage S _HA
The charges are transferred back to the previous stage S _HD . Then, the clock φ _HC is supplied only to the input terminal 22. For this, the stage S horizontal CCD4,5 _'HC, Potenshiyaru of S _HC decreases, this time, the stages S' _HD,
Since the potential of S _HD is high, the signal charges of the lines 1 and 2 on the respective stages S ′ _HD and S _HD are transferred back to the stages S ′ _HC and S _HC immediately before it.

As a result, at time _{t 4} when such operation is performed, as shown in FIG. 10 (d), A _1n charge line 1 to the stage S _'HC horizontal CCD4 is, the line to the stage S _HC horizontal CCD5 Two B _2n charges are stored respectively.

The series of operations shown in FIGS. 10 (b) to 10 (d) are performed during the horizontal blanking period, and during the next horizontal scanning period, the input terminal 2
Clocks φ _HD , φ _HA ,
φ _HB and φ _HC are repeatedly supplied, and the signal charge of line 1 is horizontally transferred by the horizontal CCD 4 and the signal charge of line 2 is horizontally transferred by the horizontal CCD 5.

The above-described operation in the horizontal period is performed for every two lines, lines 3 and 4, lines 5 and 6, ...
From CD4, the signal charge of the odd-numbered line (A +
C) signal and (B + C) signal due to the signal charges of even-numbered lines are obtained from the horizontal CCD 5.

Next, the operation in the other field period (that is, even field) will be described.

In this case as well, the signal charges of all the photodiodes 1 are simultaneously read out to the corresponding vertical CCDs ₃ during the vertical blanking period (time t _5, FIG. 10 (e)), but in this vertical blanking period as well. The following operations are performed.

First, from the input terminals 18 and 22, the clocks φ _HA and φ _{HC, respectively.}
Is supplied, and the clock φ is input from the input terminals 14 and 15.
By supplying _VA and φ _VB , the A _1n charges of the line 1 are transferred to the step S ′ _HC of the horizontal CCD 4 in the same manner as in the case of the odd field, and the state shown in FIG. 10 (b) is obtained. The same state is reached (time t ₆ ; FIG. 10 (f)). Then, in the order of the input terminals 23, 18, 19, 22, the clock φ
_HD , φ _HA , φ _HB , φ _HC are repeatedly supplied, and horizontal CCD
At 4, the signal charges on the line 1 are horizontally transferred and discharged.

The above operation is performed during the vertical blanking period, whereby the final stage S _VA of the vertical CCD 3 is connected to B _{2n of} line 2.
The electric charge is stored.

In the horizontal blanking period after the vertical blanking period has elapsed, the following operation is performed.

First, the clock φ _HA is supplied to the input terminal 18, and the clocks φ _VA and φ _VB are also supplied to the input terminals 14 and 15, so that the B _2n charge of the line 2 in the final stage S _VA of the vertical CCD 3 is supplied. It is transferred to the stage S _{HA of the} horizontal CCD 5.

The state at time t ₇ associated with this operation is shown in FIG.

Next, the clock φ _HD is supplied only from the input terminal 23,
The B _2n charge of the line 2 on the stage S _{HA of the} horizontal CCD 5 is transferred back to the immediately preceding stage S _HD , and further, the clock φ _HC is supplied only to the input terminal 22, and the stage S _HD is supplied to this stage S _HD.
B _2n charge on line 2 in _HD is the stage S immediately before
It is transferred back to the _HC .

The state at time t ₈ associated with such an operation is shown in FIG. 10 (b).

Next, the clocks φ _HA and φ _HC are supplied from the input terminals 18 and 22, and the clock φ _HA and φ _HC are supplied from the input terminals 14 and 15.
_VA and φ _VB are supplied, and the final stage S of the vertical CCD 3
The A _3n charge on line 3 at _VA is supplied to the stage S ′ _HC of the horizontal CCD 4.

The state at time t ₉ associated with such an operation is shown in FIG. 10 (i).

The above operation is performed within the horizontal blanking period, and the horizontal CCD 4
The A _3n charge of line 3 is stored in stage S ′ _HC ,
The B _2n charges of the line 2 are stored in the stage S _HC in the horizontal CCD 5, and the respective signal charges are transferred in the horizontal direction in the next horizontal scanning period.

The operation in the horizontal period described above is performed every two lines in the order of lines 4 and 5, lines 6 and 7, .... As a result, similarly to the odd field period, the output terminal 6 obtains the (A + C) signal due to the signal charges of the odd-numbered lines, and the output terminal 7 receives the signal charge (B + C) of the even-numbered lines (B +).
C) A signal will be obtained.

Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments. For example, the types of color filters installed in photodiodes and their arrangement are
Any color video signal may be obtained, and the number of horizontal CCDs may be three or more.

〔The invention's effect〕

As described above, according to the present invention, even if the combination of the two lines for which the signal charges are transferred in the horizontal CCD is different for each field, the signal charges from the photoelectric conversion elements having the same spectral sensitivity are always provided in each horizontal CCD. Therefore, the influence of the gain difference of the output part of the horizontal CCD can be avoided, the color reproducibility is equalized for each field, no color flickering occurs, and the image quality of the reproduced image is significantly improved. The effect is obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a solid-state image pickup device according to the present invention, FIG. 2 is a schematic diagram showing an arrangement example of color filters, and FIG.
FIG. 4 is a timing chart of pulses supplied to each input terminal of FIG. 1, FIG. 4 is an operation explanatory diagram showing a transfer order of signal charges in FIG. 1, and FIG. 5 is another solid-state image pickup device according to the present invention. FIG. 6 is a timing chart of pulses supplied to each input terminal of FIG. 5, FIG. 7 is an operation explanatory diagram showing a transfer order of signal charges in FIG. 5, and FIG. FIG. 9 is a block diagram showing still another embodiment of the solid-state image pickup device according to the present invention, FIG. 9 is a timing chart of pulses supplied from each input terminal of FIG. 8, and FIG. 10 is a signal charge in FIG. FIG. 11 is an operation explanatory diagram showing the transfer order of the above, and FIG. 11 is an operation explanatory diagram of the conventional solid-state imaging device. 1 ... Photoelectric conversion element, 2 ... Vertical charge transfer element,
4, 5 ... Horizontal charge transfer device, 6, 7 ... Output terminal, 8, 9 ... Transfer gate, 10, 11 ... Output section, 2
0: Transfer gate.

Front page continuation (72) Inventor Masaru Noda, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Home Appliances Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-59-169278 (JP, A)

Claims (1)

[Claims] 1. A plurality of photoelectric conversion elements which are two-dimensionally arranged in the horizontal and vertical directions and generate signal charges by receiving light, and a row of the photoelectric conversion elements in the horizontal direction is used as a line, and each photoelectric conversion element has a line. Two photoelectric transfer elements for transferring signal charges in the horizontal direction are provided, and the spectral sensitivities of the photoelectric conversion elements are different between every other line and every other line. In a solid-state imaging device in which signal charges are simultaneously transferred by separate charge transfer elements, and the combination of two lines to which the signal charges are transferred by the charge transfer elements is made different for each field, one of the fields is The charge transfer elements supply the signal charges to the charge transfer elements so that the charge transfer elements transfer the signal charges on the other alternating lines and the other charge transfer elements transfer the signal charges on the other alternating lines. Means for providing a solid-state imaging device is characterized in that the same a charge transfer device for transferring signal charges from the photoelectric conversion elements of the same spectral sensitivity.