JPH0620277B2 - Charge coupled device signal processing circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a signal processing circuit of a charge coupled device.

(Prior Art) Noise sources of a charge coupled device (hereinafter referred to as CCD) include fixed pattern noise, shot noise due to signal current and dark current, reset noise, output amplifier noise, and the like. In particular, in recent CCD solid-state image pickup devices, the chip size tends to be reduced and the number of pixels tends to be increased. Therefore, it is strongly desired to reduce the noise by coping with the reduction in the signal amount.

Among the above noises, a correlated double sampling (hereinafter referred to as CDS) circuit is known as a signal processing circuit of a CCD that reduces reset noise and a reduction component of output amplifier noise (AIE Journal). Of solid state circuit [IEEE Journal of Soli
d-State Circuits] Volume SC-9, No. 1, pp. 1-13, February 1974). As shown in FIG. 3, this CDS circuit includes a buffer amplifier 102 connected to an output terminal of a CCD 101, a clamp circuit 106 including a coupling capacitor 103, a switch 104 and a DC voltage source 105, and a signal to the next stage. Buffer amplifier 107 for transmission, switch 108, and hold capacitor 1
And a sample-hold circuit 110 including an output amplifier 111. The operation of the CDS circuit will be described with reference to the timing chart shown in FIG. First, from time t _{41 to} t ₄₂ , the switch 1 of the clamp circuit 106
Since the clamp pulse φ _C applied to 04 is turned on, the feedthrough level 1 of the CCD output signal is clamped to the potential V _C of the DC voltage source 105. Next, from time t _{43 to} t ₄₄ , the clamp pulse φ _C is turned off, and the sample pulse φ _S applied to the switch 108 of the sample hold circuit 110 is turned on instead, so that C
CD output signal level 1 is hold capacitor 10
9 is transmitted / held, and is output to the outside via the output amplifier 111. Since the clamp pulse φ _C is turned on again from time t _{45 to} t ₄₆ , the field through level 2 of the CCD output signal is clamped to the potential V _C. Next, since the sample pulse φ _S is turned on again from time t _{47 to} t ₄₈ , the hold capacitor 109, which has held the signal level 1 from time t _{44 to} t ₄₇ , is replaced with the signal level 2 instead.
Holds, and the same operation is repeated thereafter. According to the above operation, in the CDS circuit, even if the potentials of the field through level 1 and the field through level 2 are different, this potential difference is not output to the outside, and the potential difference between the field relay level 1 and the signal level 1 or the field through level. Only accurate output signal information of the CCD represented by the potential difference between level 2 and signal level 2 is output. In other words, by using the present CDS circuit, the low frequency components of the reset noise and the output amplifier noise, which are the causes of the variation in the field through level, are significantly reduced.

Next, recently, as with the CDS circuit, an integrated correlation double sampling (hereinafter referred to as IDS) circuit has been reported as a signal processing circuit of a CCD that reduces reset noise and output amplifier noise (the Institute of Communication Engineers of Japan. , 1341, 5-15
8 pages, 1985). This IDS circuit has a resistor 121 (126) and a sample switch 122 as shown in FIG.
(127) and the hold capacitor 123 (128) and the reset consisting switch 124 and (129) integrator 12
5 (130), switches 131 (134, 137) and hold capacitors 132 (135, 138). It is composed of a sample hold circuit 133 (136, 139) and a differential amplifier 140. Here, the CCD 141
The output from is simultaneously applied to the integrating circuits 125 and 130 via the buffer amplifier 142. In addition, the integration circuit 1
The outputs of 25 are buffer amplifiers 143, 144, 145.
, And is sequentially connected to the sample hold circuits 133 and 136 , and is applied to the negative terminal of the differential amplifier 140. On the other hand, the output of the integrating circuit 130 is the buffer amplifier 1
Connected to the sample hold circuit 139 via 46 and 147, and applied to the plan terminal of the differential amplifier 140.
The operation of the present IDS circuit will be described with reference to the timing chart shown in FIG. First, from time t _{61 to} t ₆₂ , the integrating circuit 1
Since the sample pulse φ _FS applied to the 25 sample switches 122 is turned on, the hold capacitor 123 is charged with electric charges according to the field through level of the CCD output signal. The charging rate at this time depends on the time constant C ₁ R ₁ of the series connection of the resistor 121 (resistance value R1) and the hold capacitor 123 (capacity C ₁ ). That is, the charging rate becomes faster as the time constant C ₁ R ₁ becomes smaller. Next, from time t _{63 to} t ₆₅ , the sample pulse φ _FS is turned off, and instead the sample pulse φ _S1 applied to the switch 131 of the sample hold circuit 133 is turned on, so that between time t _{61 and} t ₆₂ . Information on the field through level of the CCD integrated by the hold capacitor 123 is transmitted and held in the hold capacitor 132. Next, from time t _{67 to} t ₆₈ , the sample pulse φ _S2 applied to the switch 134 of the sample hold circuit 136 is turned on, so that the information of the field through level held in the hold capacitor 132 is transmitted to the hold capacitor 135.・ Retained. By the way, the integration circuit 125
The electric charge held in the hold capacitor 123 of
At time t _{65 to} t ₆₇ , the reset pulse φ _FR applied to the reset switch 124 is turned on to be charged. This is to prepare for the integration operation in the next cycle. On the other hand, from time t _{64 to} t ₆₆ , the sample pulse φ _SS applied to the sample switch 127 of the integrating circuit 130 is turned on, so that the hold capacitor 128 has CCP.
The electric charge according to the signal level of the output signal is charged. The charging rate at this time is the time constant C ₂ R of the series connection of the resistor 126 (resistance value R ₂ ) and the hold capacitor 128 (capacity C ₂ ).
Depends on ₂ . This time constant C ₂ R ₂ is generally selected to be equal to the time constant C ₁ R ₁ of the integrating circuit 125 . Then at time t
₆₇ ~t the ₆₈ sample pulse phi _SS is turned off, because the sample pulse phi _S2 which is applied to the switch 137 of the sample-and-hold circuit 139 is turned on instead, the hold capacitor 128 between time t ₆₄ ~t ₆₆ Information on the integrated CCD signal level is stored in the hold capacitor 13
8 is transmitted and held. That is, from the time t _{67 to the} time t ₆₈ , the hold capacitor 1 is turned on from the time t ₇₀ of the next cycle.
Information on the field through level of the CCD is held in 35, and information on the signal level of the CCD is kept held in the hold capacitor 138. Therefore, the differential amplifier 14
From 0, the potential difference between the field through level and the signal level is output. The charge held in the hold capacitor 128 of the integrating circuit 130 is discharged when the reset pulse φ _SR applied to the reset switch 129 is turned on at times t _{68 to} t ₆₉ . According to the above operation, in the IDS circuit, not only the low frequency components of the reset noise and the output amplifier noise, which are the causes of the variation of the field through level, can be significantly reduced, but also the high frequency component of the output amplifier noise is removed by the integrating circuit. Therefore, these high frequency components are less likely to be returned to the reduction due to the sampling operation, and further noise reduction is possible.

(Problems to be Solved by the Invention) As described above, two conventional signal processing circuits for reducing the noise of the CCD, the CDS circuit and the IDS circuit, have been described. In the former case, reset noise and low-frequency components of output amplifier noise are Although it can be reduced, it has a drawback that the high frequency component of the output amplifier noise is folded back to the low frequency band by the clamp operation and the sampling operation. In the latter case, although the above-mentioned drawbacks are almost eliminated, it is difficult to apply it to mass-produced products due to the large number of drive pulses and the large number of adjustment points due to the complicated circuit.

The present invention eliminates the above-mentioned conventional drawbacks, and an object of the present invention is to provide a new signal processing circuit of a CCD having a large noise reduction effect.

(Means for Solving the Problems) According to the present invention, the field through level of the output signal is connected to the output part of the charge coupled device, the output signal from the charge coupled device is band-limited, and the field through level of the output signal is set to a constant potential. And a soft clamp circuit part for clamping to the soft clamp circuit part, and an integration circuit part connected to the output part of the soft clamp circuit part for integrating the signal level of the output signal over a fixed period, and an integration part connected to the output part of the integration circuit part. A signal processing circuit for a charge-coupled device, which comprises a sample-hold circuit section for sampling the signal level after completion and an output amplifier connected to an output section of the sample-hold circuit section.

(Operation) Since the field through level of the CCD output signal is clamped to a constant potential in the soft clamp circuit section, the low frequency components of the reset noise and the output amplifier noise can be removed. Further, since the band is limited before clamping, it is possible to reduce the aliasing of the output amplifier noise high frequency component to the low frequency range due to the clamp operation. Furthermore, in the integrating circuit section, C
Since the output amplifier noise high frequency component weighted by the signal level of the CD output signal is removed, aliasing of the output amplifier noise high frequency component to the low frequency due to the sampling operation can be reduced. As a result, according to the signal processing circuit of the present invention, the noise reduction of the CCD can be achieved and the circuit configuration is simple.

(Example) Hereinafter, the Example of this invention is described using drawing.
FIG. 1 shows an embodiment of a signal processing circuit of a CCD according to the present invention.
Yes, resistor 1, coupling capacitor 2, switch 3
And a soft clamp circuit composed of a DC voltage source 45
, Resistor 6, sample switch 7, hold capacitor
8 and reset switch 910
And switch 11 and hold capacitor 12
Sample hold circuitThirteenAnd the buffer amplifiers 14 and 1
5, 16 and an output amplifier 17. here
The output from CCD 18 is buffered to each stage.
Soft clamp circuit via pumps 14, 15 and 16
5, Integrator circuit10, Sample and hold circuitThirteen, Output
Pump17Are connected in this order.

The operation of this embodiment will be described with reference to the timing chart shown in FIG. First, from time t _{1 to} t ₂ , the clamp pulse φ _C applied to the switch 3 of the soft clamp circuit 5 is
Is turned on, the field through level of the CCD output signal is clamped to the potential V _C of the DC voltage source.
However, at this time, the clamping speed is resistance 1 (resistance value R)
And the hold capacitor 2 (capacitance C) are connected in series depending on the time constant CR. That is, when the time constant CR is reduced, the clamping speed increases, but the high frequency component of noise included in the output signal of the CCD cannot be removed, and the aliasing noise component to the low frequency due to the clamp operation increases. On the contrary, when the time constant CR is increased, the aliasing noise component to the low frequency band is reduced, but the clamp speed is reduced and the clamp cannot be applied. Therefore, the time constant CR must be selected so that the aliasing noise component is minimized within the range where the clamp is normally applied.

Next, from time t _{3 to} t ₄ , the clamp pulse φ _C is turned off and the sample pulse φ _S1 applied to the sample switch of the integrating circuit 10 is turned on instead, so that the hold capacitor 8 receives the CCD output signal of the CCD output signal. The electric charge according to the signal level is charged. However, the charging speed at this time is the resistance 6 (resistance value R ') and the hold capacitor 8 (capacity C').
Of the series connection of C'R '. That is, if the time constant C'R 'is reduced, the charging speed increases,
Although the signal voltage level charged in the hold capacitor 8 increases, the high frequency component of noise included in the output signal of the CCD cannot be removed, and the aliasing noise component to the low frequency due to the sampling operation also increases. On the contrary, if the time constant CR is increased, the aliasing noise component to the low frequency band is reduced, but the charging speed is reduced, and the signal voltage level charged in the hold capacitor 8 is also reduced. Therefore, the time constant CR should be chosen to maximize the signal to noise ratio.

Next, from time t _{5 to} t ₆ , the sample pulse φ _S1 is turned off,
Instead, the sample pulse φ _S2 applied to the switch 11 of the sample hold circuit 3 is turned on,
C integrated by the hold capacitor 8 between times t _{3 and} t ₄
The information on the CD signal level is transmitted to the hold capacitor 12 and held at a constant potential until time t ₇ in the next cycle. Therefore, only the normal output signal information of the CCD is output from the output amplifier 17. Incidentally charges held in the hold capacitor 8 of the integrating circuit 10, the time t ₆ ~t ₇
Is applied to the reset switch 9. It is discharged when the reset pulse φ _SR is turned on. This is to prepare for the integration operation in the next cycle.

(Effects of the Invention) As described above, according to the signal processing circuit of the CCD of the present invention, not only the low frequency components of the reset noise and the output amplifier noise of the CCD noise are significantly reduced, but also the output amplifier Since the high frequency component of noise is often returned to the low frequency range by the clamp operation or the sampling operation, it is possible to significantly reduce the noise. Furthermore, since the number of drive pulses used is relatively small and the circuit configuration is simple, there are few adjustment points and it is easy to apply to mass-produced products.

[Brief description of drawings]

FIG. 1 is a signal processing circuit diagram according to the present invention, FIG. 2 is a timing chart for explaining the operation of the signal processing circuit according to the present invention, and FIG. 3 is a conventional correlated double sampling (CD
S) circuit diagram, FIG. 4 is a timing chart for explaining the operation of the CDS circuit, FIG. 5 is a circuit diagram of a conventional integrated correlation double sampling (IDS) circuit, and FIG. 6 is a diagram for explaining the operation of the IDS circuit. 2 is a timing chart of. In the figure, 5 is a soft clamp circuit, 106 is a clamp, 10 , 1
25 , 130 are integrating circuits, 13 , 110 , 133 , 13
6 , 139 are sample and hold circuits, 14 to 16, 10
2, 107, 143-147 are buffer amplifiers, 17,
111 is an output amplifier, and 140 is a differential amplifier.

Claims (1)

[Claims] 1. A soft clamp circuit section connected to an output section of a charge-coupled device, for band-limiting an output signal from the charge-coupled element, and then clamping a feedthrough level of the output signal to a constant potential, and a soft clamp circuit section. An integrating circuit section connected to the output section of the clamp circuit section for integrating the signal level of the output signal over a certain period, and a sample hold connected to the output section of the integrating circuit section for sampling the signal level after completion of the integration. A signal processing circuit for a charge-coupled device, comprising a circuit section and an output amplifier connected to an output section of the sample hold circuit section.