JPH0621920A - Error detection method for multi-block transmission frame - Google Patents

Abstract

(57) [Abstract] [Purpose] To simplify the error checking means in the data transmission of the transmission frame 1 composed of a plurality of blocks 2-1 to 2-3 and to speed up the processing. [Structure] The cyclic code CRC (CRC1 to CRC3) provided for each of the data blocks 2-1 to 2-3 is performed at the beginning of the transmission frame 1 without performing the encoder initialization at the beginning of each block as in the conventional case. Keep the data of each block 3-
Every time 1, 3-2, 3-3 are input, the arithmetic operation is output and added to the block data 3 to generate the transmission frame 1. Similarly, with respect to the decoder, while the initialization is performed at the beginning of the transmission frame 1, the CRC calculation is sequentially performed for each reception of each of the blocks 2-1, 2-2, 2-3, and the error check is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting an error in a transmission frame composed of a plurality of data blocks by using an error detection code. In the drawings below, the same reference numerals indicate the same or corresponding parts.

[0002]

2. Description of the Related Art FIG. 3 is an explanatory diagram of a conventional error detecting method in this type of data transmission. In the figure, 1 is a transmission frame and 2 (2-1 to 2-3) are data blocks (blocks #
1 to # 3 or first block to third block),
3 (3-1 to 3-3) are the data blocks 2-1 respectively.
2 to 3 (data # 1 to # 2 for convenience, respectively)
Also, CRC1 to CRC3 are CRCs (cyclic redundancy check: cyclic codes) as error detection codes that also configure the data blocks 2-1 to 2-3, respectively.

Conventionally, error detection is performed independently for each block 2. An error detection mechanism using CRC that is generally used is composed of an encoder and a decoder that perform an operation using a shift register. That is, the thick solid lines corresponding to (1) to (3) in FIG. 3 indicate the range of valid data corresponding to CRC1 to CRC3, respectively, and the upward arrows indicate the initialization points of the encoder and the decoder, respectively.

FIGS. 4 (A) and 4 (B) show the operation procedure of the above-mentioned transmission source encoder and transmission destination decoder, respectively.
The reference numeral S15 indicates the step in FIG.
The reference sign of S25 indicates the step of FIG. Explaining the figure, the transmission source first inputs the block data 3-1 to the encoder with the initial value set (S11, S12), calculates the CRC from this data 3-1 (S13), and calculates the calculated CRC. It is added to the data 3-1 of the block 2-1 (S14), and the above operation is repeated for all the remaining data blocks 2-2 and 2-3 (S15 → S11).
Up to S15), the transmission frame 1 is created.

At the transmission destination, an initial value is set in the decoder (S21), and the block 2 of the transmission frame 1 is first set in this.
Enter 1. And this input data (that is, data 3
CRC is calculated from the data obtained by adding CRC1 to -1) (S23), and if the result of this CRC calculation reaches a certain fixed value (S24, branch Y), the received data is regarded as correct, and otherwise. (S24, branch N), it is determined that the received data is incorrect. While the data received here is correct, all the remaining data blocks 2-
Repeat for 2 and 2-3 (S25 → S21 to S2
5), and the error check of the received transmission frame 1 is finished.

[0006]

Therefore, when the transmission frame 1 is divided into a plurality of blocks, it is necessary to initialize the encoder or the decoder for each block in one transmission frame, and the data is required. Must be coded or decoded without delay, and in data transmission, which tends to be faster, the delay and the enlargement of the device due to the initialization of the error detection mechanism pose a problem.

Therefore, an object of the present invention is to provide an error detection method for a multi-block transmission frame which can simplify the error detection mechanism of the device without deteriorating the performance of the conventional error detection.

[0008]

In order to solve the above-mentioned problems, the error detection method of the present invention uses a block data (3) of a transmission frame (1 etc.) composed of a plurality of data blocks (2 etc.). A cyclic code (CRC) is added to each data block and error detection is performed for each data block, and a cyclic code whose effective range is the contents of the frame from the beginning of the transmission frame to each corresponding data block is added. It should be added to each block data.

[0009]

The operation start position (initialization position) of the CRC provided in each data block is made common and placed at the beginning of the transmission frame. The effective range of the CRC is from the initialized position to the position where the CRC is set. Since only the beginning position of the transmission frame is initialized, the CRC set for each block at the transmission source becomes the effective range from the beginning of the transmission frame to each block at the transmission destination, and error detection is performed in block units. Become.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is an explanatory diagram of an error checking method as an embodiment of the present invention and corresponds to FIG.
4B is a flow chart showing the operating procedure of the encoder and the decoder, respectively, and corresponds to FIGS. 4A and 4B.

1 and 2 are different from FIGS. 3 and 4 in that the initial setting of the encoder and the decoder is performed only at the beginning of the transmission frame 1. Next, FIG. 2 will be described with reference to FIG. In FIG. 2A, the transmission source sets an initial value in the encoder in advance (S11), and the first block 2-
CRC (CRC1) is generated from the data 3-1 of 1 (S
12, S13), and the first block data 3-1 is added (S14) (FIG. 1). In the next second block 2-2, the state of the first block is continued without initializing the encoder (that is, with the data of CRC1 left in the encoder).
Encode. Therefore, the data 3-1 of the first block 2-1 and the data 3-2 of the second block 2-2 are input from the outside to generate a CRC (CRC2) (S1).
2 to S14) (FIG. 1).

Similarly, for the remaining third block 2-3, by repeating the procedure of steps S12 to S14, a valid CRC (CRC
1 to CRC3) are added to form a transmission frame 1. 2B, at the transmission destination, the initial value is set to the decoder (S21), and the first block 2-1 is inspected (S22 to S24) (FIG. 1), the second block. 2-2 continuously inspects the state of the first block without initializing the decoder (S25 → S22 to S24) (FIG. 1).
). By successively continuing in this manner, error detection is performed for each block.

[0013]

According to the present invention, a method is adopted in which the error detection start position of a transmission frame is not divided into blocks, but is placed at the beginning of the transmission frame in common for each block, and each applicable block is set as an effective range. Therefore, the mechanism related to the initialization in the second block and thereafter can be omitted, the device can be simplified, and the data transmission can be speeded up.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an error detection method as an embodiment of the present invention.

FIG. 2 is a flowchart showing the operating procedure of the encoder and the decoder.

FIG. 3 is a conventional explanatory diagram corresponding to FIG.

FIG. 4 is a conventional flowchart corresponding to FIG.

[Explanation of symbols]

 1 Transmission Frame 2 (2-1 to 2-3) Data Block 3 (3-1 to 3-3) Data CRC (CRC1 to CRC3) Cyclic Code

Claims (1)

[Claims] 1. A method of adding a cyclic code to each block data of a transmission frame composed of a plurality of data blocks to detect an error in each of the data blocks, wherein each corresponding data from the beginning of the transmission frame An error detection method for a multi-block transmission frame, characterized in that a cyclic code whose effective range is the contents of a frame up to a block is added to each block data.