JPH0622232B2 - Method for flattening wiring interlayer film of semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to planarizing a wiring interlayer insulating film.

[Conventional technology]

11 to 15 are views for explaining some of the conventional planarizing methods for the interlayer insulating film.

As shown in FIG. 11, one method is to stack an interlayer film 108 thickly on a semiconductor substrate 106 having a step due to a lower semiconductor element or wiring 107, and then apply a coating film 109 as shown in FIG. This is a method in which a thick coating is applied to the entire surface, and the entire surface is etched under the condition that the etching rates of the insulating film and the coating film are equal to each other to obtain the shape shown in FIG.

Further, as one method, as shown in FIG. 14, the coating 110 is applied to the substrate 106 having the same step as the above-mentioned substrate,
A method of utilizing the coating film 110 itself as an interlayer insulating film, and further, as shown in FIG. 15, an interlayer insulating film having a coating film thickness 113 sandwiched between a first insulating film 111 and a second insulating film 112. And the method was adopted.

[Problems to be solved by the invention]

In the method shown in FIGS. 11 to 13, first, the interlayer insulating film must be grown very thick. At this time, however, voids 114 tend to be generated between the patterns in the lower layer, as shown in FIG. If the voids appear on the surface of the substrate after the entire surface is etched, the insulating film in the voids may be etched. 115 It may cause a wiring short circuit in the next wiring process, and the reliability remains even if it remains inside. It was highly likely to cause problems. Further, when the coating film is thin, unevenness is left along with the pattern of the underlying layer, and therefore the coating film must be coated very thick in order to make the surface sufficiently flat after coating. Further, the etching rates of the interlayer insulating film and the coating film must be equal over the entire surface of the wafer, but generally it is difficult to make both the etching rate and the in-plane uniformity of the wafer equal to each other. In addition, the thicker the film thickness, the greater the difference between the area where the etching film thickness is large and the area where the etching film thickness is small, and it is difficult to perform sufficient planarization by this method. Further, according to the method as shown in FIG. 14, the coating film must be thickly coated in order to obtain sufficient flatness, but if it is too thick, problems such as cracks are likely to occur. Further, generally, the coating film is relatively poor in moisture resistance and it is not desirable to form the interlayer film only by coating. Therefore, there is a method as shown in FIG. 15 in which the flatness and the quality of the interlayer film are made compatible by sandwiching the coating film with various oxide film type insulating films. It becomes difficult,
In many cases, residual volatile components or adsorbed gas came out from the exposed coating film on the side surface of the via hole, resulting in poor wiring quality.

[Differences from the Prior Art of the Invention]

In contrast to the conventional method for flattening an interlayer film of a semiconductor device, the present invention performs the entire surface etching in two steps, and the etching condition of the second step is set so that the etching rate of the coating film is slower than that of the Soma insulating film. Since the reduction of the interlayer film can be prevented at a low step, it is not necessary to make the initial interlayer film thickness thicker than necessary, so that voids do not occur between the patterns and the etching speed is high. The difference is that a small step portion formed at the boundary between the coating film and the interlayer film is smoothed by providing a margin for the ratio and reflowing by a heat treatment after completion of etching to obtain good flatness.

[Means for solving problems]

A method of flattening a wiring interlayer film of a semiconductor device according to the present invention comprises a step of growing an interlayer insulating film on a semiconductor substrate having a height difference on the surface due to formation of a semiconductor element, and an intercoat film on the interlayer insulating film. And the step of etching the entire coating film and ending the etching when the highest part of the Soma insulating film appears on the surface, and the condition that the etching rate ratio of the interlayer insulating film to the coating film is greater than 1. Step of etching the entire surface by etching, and ending the etching before the etching reaches the underlying wiring or semiconductor element, a step of removing all the coating film remaining on the surface of the semiconductor substrate, and a step of performing a heat treatment to reflow the interlayer insulating film Includes and.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1 to 6 schematically show cross sections of the semiconductor substrate in the order of processing steps.

First, as shown in FIG. 1, a lower semiconductor element or wiring 10
A CVD method is used to form an oxide film 103 (hereinafter referred to as BPSG) containing phosphorus and boron as impurities on a semiconductor substrate 101 having a step due to 2 (a material that can withstand relatively high temperatures such as tungsten silicate). Due to
A thickness of about one half of the minimum space of the underlying pattern is grown.

Subsequently, as shown in FIG. 2, a photoresist 104 having a viscosity of about 8 cp is coated on the substrate 101 at a rotation speed of about 4000 rotations.

Next, as shown in FIG. 3, the entire surface of the photo resist 104 is etched by O ₂ gas, and the etching is stopped when a part of the BPSG 103 comes out.

Next, as shown in FIG. 4, the entire surface of the semiconductor substrate 101 is etched with CF ₄ gas in the same etching chamber. At this time, by properly selecting the conditions, the BPSG etching rate has good uniformity within the wafer and the BP
The SG / photoresistor selection ratio is set to about 2 and the BPSG 103 is provided on the upper portion of the lower wiring 102.
Stop etching when there is about 0Å left.

Next, as shown in FIG. 5, the photoresist 104 is peeled off.

Next, to the extent that the underlying wiring 102 can withstand and the BPSG1
Heat treatment is carried out to such an extent that 03 will reflow to obtain a shape as shown in FIG.

Example 2 An example of the present invention will be described below with reference to the drawings. 7 to 10 schematically show cross sections of the semiconductor substrate in the second embodiment in the order of processing steps. However, the description of the first embodiment up to FIG.

First, as shown in FIG. 7, organic silica 105 is applied on the substrate 101 on which the BPSG 103 has been grown.

Subsequently, as shown in FIG. 8, the entire surface of the organic silica 105 is etched with CF ₄ gas, and the etching is stopped when the BPSG 103 is partially exposed.

Next, as shown in FIG. 9, the entire surface of the semiconductor substrate 101 is etched with CHF ₃ + O ₂ gas in the same etching chamber. At this time, by properly selecting the conditions, the BPSG etching rate has good uniformity within the wafer so that the BPSG / organic silica selection ratio is about 2, and the BPSG 103 is formed on the lower wiring layer 102 in an amount of about 20%.
Stop the etching when there remains about 00Å.

Next, as shown in FIG. 10, the organic silica 105 is removed by etching with diluted hydrofluoric acid. At this time, BPSG1
Since the etching rate of 03 is sufficiently slower than that of organic silica and the selection ratio can be taken, the reduction of the interlayer film can be almost ignored.
Hereinafter, as in the first embodiment, the shape of FIG. 6 is obtained by heat treatment.

〔The invention's effect〕

As described above, according to the present invention, after the coating film is formed on the interlayer insulating film, the entire surface is etched in two steps, and the etching rate of the coating film is slower than that of the interlayer insulating film in the second step. Since the thickness of the interlayer insulating film does not have to be made thicker than necessary because it prevents the film loss in the low step portion, voids do not occur in the pattern with a narrow interval, and the etching amount for the entire surface etching is relatively small. Therefore, the margin for the uniformity of the etching rate within the wafer increases. Further, since the coating film is not used as an interlayer film by removing it before the heat treatment, no gas is generated from the side surface of the via hole and the wiring quality is not deteriorated. Furthermore, by reflowing the interlayer film by heat treatment, it is possible to eliminate slight irregularities remaining on the surface. From the above, there is an effect that a sufficiently flat and high quality interlayer film can be formed.

[Brief description of drawings]

1 to 6 are longitudinal cross-sectional views in order of the steps for explaining the first embodiment of the present invention. 7 to 10 are longitudinal cross-sectional views in order of the steps for explaining the second embodiment. 11 to 16 are vertical sectional views for explaining some conventional examples. 101 ... semiconductor substrate, 102 ... wiring, 103 ... BPSG,
104 ... Photoresist, 105 ... Organic silica, 1
06 ... Semiconductor substrate, 107 ... Wiring, 108 ... Interlayer insulating film, 109 ... Coating film, 110 ... Coating film, 111 ... First insulating film, 112 ... Second insulating film, 113 ... ... Coating film, 11
4 …… Voids generated in thick insulating film, 115 ……
The area where the insulating film is etched in the void.

Claims (1)

[Claims] 1. A step of growing an insulating film on a semiconductor substrate having a height difference on the surface, a step of applying a coating film on the insulating film, and a total etching of the coating film to obtain the highest part of the insulating film. The step of terminating the etching when it appears on the surface, and etching the entire surface under the condition that the etching rate ratio of the insulating film to the coating film is more than 1 and etching before reaching the underlying wiring or semiconductor element. And a step of removing all of the coating film remaining on the semiconductor substrate, and a step of performing a heat treatment to reflow the insulating film.