JPH0622268B2 - Method for manufacturing multilayer capacitor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a multilayer capacitor which can obtain a large capacity in a small area and is suitable for a memory cell capacitor of a semiconductor memory.

[Conventional technology]

In a large-capacity semiconductor memory, a memory cell called a 1-transistor type memory cell composed of one transistor and one capacitor is widely used. In this memory cell, whether to store the charge in the cell capacitor corresponds to binary information "1" or "0". Therefore, in order to stably store the binary information in the memory cell, it is necessary to increase the cell capacitor value and increase the stored charge amount. Further, the read signal voltage from the one-transistor type memory cell is obtained by dividing the charge stored in the cell capacitor by the capacitor ratio between the cell capacitor and the bit line capacitor, so to obtain a sufficiently large read signal voltage, a large cell capacitor value is required. is necessary.

Therefore, in order to highly integrate a semiconductor memory using a one-transistor type memory cell, a capacitor technology capable of obtaining a large capacitor value in a small area is essential. Conventionally, as such a technology, the 1982 International Electronic Device Conference (1982
International Electron Devices Meeting) Proceedings 806
Page article "A Corrugated Capacitor Cell (CCC)"
For example, there is a groove capacitor proposed in “Megabit Dynamic MOS Memories” and an invention “integrated laminated capacitor” disclosed in Japanese Patent Laid-Open No. 59-132644.

[Problems to be solved by the invention]

However, in the former groove capacitor, (1) there is a limit to the depth of the groove that can be excavated, so there is a limit to the increase in the capacitor value, (2) because one electrode of the capacitor extends inside the substrate. There is a problem that it is easy to collect the leak current generated inside the substrate. Also, the latter multilayer capacitance requires (1) a difficult process of producing good-quality single crystal silicon on the insulator film, and (2) due to junction leakage and junction breakdown voltage due to the presence of a PN junction between the electrodes. There were problems such as limited capacity characteristics.

The object of the present invention is that the capacitor value per unit area can be made sufficiently large due to the laminated structure, the leakage current generated inside the substrate is rarely collected, and the electrodes are isolated by the insulator, so that only the PN junction isolation is achieved. It is an object of the present invention to provide a method for manufacturing a multilayer capacitor which does not suffer from various restrictions.

[Means for solving problems]

In order to achieve the above object, the present invention provides a first conductivity type silicon film, an insulator film, and a second film on one surface of a silicon crystal substrate.
A step of forming a laminated film in which conductive silicon films are sequentially laminated, a step of removing the laminated film while leaving a predetermined shape, and a first conductive type silicon film on the side surface of the silicon film is better than a second conductive type silicon film. A step of forming a thicker silicon oxide film, a step of etching to leave the silicon oxide film on the side surface of the first conductivity type silicon film, and a step of removing the silicon oxide film on the side surface of the second conductivity type silicon film, one side surface of the laminated film And a step of depositing and forming a second conductivity type silicon film on the silicon substrate, and a step of forming a silicon oxide film on the surface of the second conductivity type silicon film by an anodic oxidation method.

〔Example〕

Next, a method for manufacturing the multilayer capacitor of the present invention will be described using examples of the present invention.

FIG. 1 shows a structure of an embodiment of the multilayer capacitor of the present invention, and FIGS. 2 to 5 show an example of a manufacturing process for obtaining the structure of FIG. In FIG. 2, a silicon nitride film 12 is formed on an N-type silicon crystal substrate 11, and P is formed on the silicon nitride film 12.
After forming a laminated film composed of the type polysilicon 13, the insulator film 14, and the Lindove N-type polysilicon 15 with the insulator film 14 in between, a silicon nitride film 16 is formed on the laminated film. , A state in which the silicon nitride film 16 and the above-mentioned laminated film are etched while leaving a predetermined shape.

As the insulator film 14, for example, a laminated film of silicon nitride and silicon oxide is suitable. 800 to 90 in the state shown in FIG.
When oxidation is performed in water vapor at around 0 ° C., a silicon oxide film is formed on the side surface of the P-type polysilicon 13 as shown in FIG.
17, a silicon oxide film 18 thicker than the silicon oxide film 17 is formed on the side surface of the phosphorus-doped polysilicon 15. This is due to the unusually high rate of oxidation of the phosphorus-doped silicon under the above conditions (reference: H. Suuami “Ther
mal Oxidation of Phosphorus-Doped Poly-crystalline
Silicon in Wet Oxygen ”JECS 125-6 (6.'78) P.89
2).

In FIG. 3, etching is performed under the condition that the silicon oxide film 17 is removed by etching and the silicon oxide film 18 is left, and a P-type polysilicon film 19 is deposited so as to contact one side surface of the laminated film and the silicon substrate 11. It becomes like the figure. Here, 18 'is the remaining portion of the etched silicon oxide film 18,
Is a P-type diffusion layer formed of P-type impurities diffused from the P-type polysilicon 19 to the N-type silicon substrate 11.

In FIG. 4, after the silicon oxide film 18 'which is not covered with the P-type polysilicon 19 is removed by etching,
When the silicon substrate 11 is connected to a power source and anodization is performed,
As shown in FIG. 5, silicon oxide films 21 and 22 are formed on the portion of P-type polysilicon 13 electrically connected to the silicon substrate 11.
And are formed. The anodic oxidation is preferably performed while irradiating light with energy of about leV so that a current flows between the P-type diffusion layer 20 and the N-type silicon substrate 11.
A current does not flow into the silicon oxide film 21 unless it is irradiated with light having an energy of about 4 eV or more, so that the current can be selectively flowed only to the silicon portion.

In FIG. 5, by depositing N-type polysilicon 23 on the side surface opposite to the one side surface of the laminated film, a multilayer capacitor structure according to an embodiment of the present invention as shown in FIG. 1 is obtained. In this multilayer capacitor, P-type polysilicon 1
3, a capacitor composed of an insulator film 14 and N-type polysilicon 15 is stacked in three layers. P-type polysilicon 13 has P-type polysilicon 19 and N-type polysilicon 15 has N-type polysilicon 15. Silicon 23 is connected and serves as a lead electrode.
The P-type polysilicon and the N-type polysilicon are completely separated by the insulators 14, 18 'and 21.

The multi-layer capacitor of the present invention is suitable for a memory cell capacitor of a semiconductor memory because it can obtain a large capacity in a small area and prevents leakage between capacitors. FIG. 6 shows an example in which the multilayer capacitor of the present invention is applied to a one-transistor type memory cell. The parts without numbers in the figure are the first
The structure is the same as that of the figure, and an N-type polysilicon gate electrode 24 which constitutes a switching transistor, P-type diffusion regions 25 and 26 which become current-carrying electrodes, a gate oxide film 27 and an interlayer insulating film 2
9. Aluminum wiring 28 is added. In this figure, the gate electrode 24 is connected to the word line, the P-type diffusion region 26 is connected to the bit line, and the aluminum wiring 28 is connected to the power source.

〔The invention's effect〕

Since the method of manufacturing the multilayer capacitor of the present invention utilizes the fact that the impurities diffused in the silicon film increase the oxidation rate of the silicon film, the second conductive film can be selectively used without a step such as difficult alignment. An extraction electrode can be formed from the mold silicon film. Furthermore, since the anodic oxidation method is used, which has the property that the silicon oxide film is formed only on the electrically connected silicon film of the substrate, the side surface of the second conductivity type silicon film can be selectively selected without any complicated alignment process. It is possible to form a silicon oxide film only on. When the anodization method is used, a silicon oxide film is formed on the surface of the silicon film electrically connected to the silicon substrate,
For example, in the example of FIGS. 1 to 5, the insulator film 14 and the silicon oxide film 1
Even if there is a pinhole on the 8 ', it is possible to prevent the leak between the electrodes of the multilayer capacitor.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing the structure of one embodiment of the multilayer capacitor of the present invention, and FIGS. 2 to 5 are an example of a method of manufacturing the multilayer capacitor of the present invention for obtaining the structure of FIG. FIG. 6 is a sectional view showing an example of a one-transistor cell using the multilayer capacitor of the present invention. 11 …… N type silicon crystal substrate, 13 …… P type polysilicon, 14 …… Insulator film, 15 …… N type polysilicon, 16 ……
Silicon nitride, 19 ... P-type polysilicon, 21 ... Silicon oxide film, 23 ... P-type polysilicon.

Claims (1)

[Claims] 1. A step of forming a laminated film in which a silicon film of a first conductivity type, an insulator film, and a silicon film of a second conductivity type are sequentially laminated on one surface of a silicon crystal substrate, the laminated film leaving a predetermined shape. Removing the first conductivity type silicon film on the side surface of the silicon film
Forming a silicon oxide film thicker than the conductive type silicon film, leaving the silicon oxide film on the side surface of the first conductive type silicon film by etching, and removing the silicon oxide film on the side surface of the second conductive type silicon film, It is characterized in that a step of depositing and forming a second conductivity type silicon film on one side of the laminated film and the silicon substrate, and a step of forming a silicon oxide film on the surface of the second conductivity type silicon film by an anodic oxidation method are sequentially performed. Manufacturing method of multilayer capacitor.