JPH0622291B2 - Digital FM demodulator - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital FM demodulation device that can be used when demodulating an FM signal of a television sound multiplex signal.

2. Description of the Related Art Generally, a PLL system and a pulse count system are used as a demodulation system of an FM signal of an analog TV audio multiplex signal. These methods can also be used in FM demodulation digital signal processing.

The problem to be solved by the invention is that such an FM demodulation method becomes complicated in the PLL system because the signal is sampled in the digital limiter which can be easily constructed by analog technology. In order to obtain the / N ratio, a large amount of hardware is required, and in the pulse counting method, the output of the mono-multivibrator 5 triggered by the output of the zero-cross detector 1 as shown in FIG. 3 is a low pass filter (LPF). Although 1-bit output is obtained by filtering at 6, the low-pass filter 6 filters a 1-bit signal, so a large-scale filter is required. Generally, when the pulse count method is to be configured digitally, the clock frequency to be used becomes high because the accuracy of the zero-cross detector 1 is desired to be increased. The 1-bit pulse train output from the mono-multivibrator 5 contains many harmonics of the instantaneous frequency of the FM signal,
For example, in the case of voice multiplexing of a television receiver, the carrier frequency c is 31.5 KHz and the frequency deviation is 10 KHz, but it is overmodulated, and considering the frequency deviation of about 15 KHz, the minimum instantaneous frequency is 31.5 KHz-15 KHz = 16.5
Since it becomes KHz, the second harmonic becomes 33 KHz. Such harmonics must be removed by the LPF 6, but the 1-bit pulse train has large harmonics.
The characteristic of the LPF 6 which secures a reproduction band of 15 KHz and obtains a considerable amount of attenuation at 33 KHz requires an 8th order filter characteristic in order to obtain about 50 dB of attenuation.
Of course, it is difficult to create such a characteristic from the clock frequency of the mono-multivibrator 5, and it is general that the sampling frequency is gradually lowered while repeating the low-pass filter and the resampling. However, even with such a configuration, it is necessary to fully consider that folding back of the harmonics of the pulse train of the mono-multivibrator 5 can be ignored during re-sampling, and the LPF 6 has a complicated configuration. As described above, in the case of the pulse counting method, the output pulse train of the mono multivibrator 5 is 1
Since it is a bit, the pulse train has large harmonics and the LPF 6 has a complicated structure. As described above, in any of the methods, there is a drawback that the hardware becomes large when trying to obtain the necessary S / N ratio and distortion characteristics.

The present invention solves these drawbacks and provides a digital FM demodulation device that can be configured with relatively simple hardware.

Means for Solving the Problems A digital FM demodulator of the present invention has a counter for measuring the period of an FM signal or a half period by counting a clock and a memory for temporarily storing the output of this counter. It is composed of a device, a ROM having an output of the storage device as an address, and a storage device of a plurality of words for storing the output of the ROM.

Operation The digital FM demodulation device of the present invention measures the period by the counter, directly converts this value into the demodulation output by the ROM, sequentially stores the demodulation output in the storage device of at least 2 words, and corrects the stored data. It is controlled and read at time intervals, and can reduce the distortion rate of the FM demodulated signal.

Embodiment A digital FM demodulator according to an embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the zero-cross detector 1 outputs a zero-cross detection output signal as shown in FIG. 2 when the FM signal passes through an AC zero point.

This signal is given to the counter 2 to clear the counter 2, but at the same time it is also connected to the storage device 3,
The storage device 3 stores the value of the counter 2 immediately before the counter 2 is cleared. Since the value stored in the storage device 3 indicates the half cycle of the FM signal counted by the clock, this is given as the address value of the ROM 4. RO
Data for the address is written in advance in M4. For example, the address value is A, the output data is D,
If the carrier of the FM signal is _c and the maximum frequency deviation of the FM signal is _d , the value of the relation D = (/ 2A− _c ) / _d is written in the ROM 4, and the address A
Is given, a value normalized to ± 1 is taken out as a ROM output as a demodulation output. However, this output is, as shown in FIG. 2, the ROM output corresponding to the T ₁ period is D ₁ ,
T ₂ are D _n with respect to T _n so that D ₂ are delay has occurred, the delay time is distorted increases Continued demodulated outputs ROM output because it depends on the period of the FM signal not constant Will end up. In order to eliminate this next point, three storage devices 7a, 7b, 7c are connected in the subsequent stage of the ROM 4, and the write timing to the storage devices is divided by the frequency dividing circuit 10 to divide the zero-cross detection output signal W ₁ , W ₁ . ₂ and W ₃ are created and written into the storage devices 7 a, 7 b and 7 c by this signal, and the read numbers are W ₁ , W ₂ and W ₃ each delayed by T _d at the counter 11 to R ₁ , R ₂ and R _3. Storage device 7a, 7b, 7
three-state buffer 8a connected to the output of c,
Add to the output enable terminals of 8b and 8c. At this time,
If the data written by W ₁ is read by R ₃ , and W ₂ is shifted by R ₁ and W ₃ is shifted by R _2, the demodulation output is delayed by T _d, but it does not depend on the period of the FM signal, so no distortion occurs. .

Here, three storage devices 7a, 7b, 7c are used, but if this number is N, the minimum value of N is determined by the maximum frequency shift _d of the FM signal and the carrier frequency _c , and N is in the range of the following formula. Takes a value.

In the case of N> ( _c + _d ) / ( _c - _d ) TV audio multiplex signal, _d = 10 KHz, _c = 31.
Since it is 468 kHz, N> 1.93, but N = 3 in consideration of overmodulation.

In the embodiment of FIG. 1, the storage devices 7a, 7b, 7c are replaced by R
Although it is arranged on the output side of the OM4, the same effect can be obtained on the input side (address side) of the ROM 4 in a similar way.

As described above, the digital FM demodulation device of the present invention is
It is composed of a storage device for storing the output value of a counter for measuring the period of a signal, a ROM connected to the storage device, and a storage device for a plurality of words connected to the ROM output. Therefore, the demodulation output can be obtained, and the distortion of the demodulation output can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital FM demodulator in one embodiment of the present invention, FIG. 2 is an operation waveform diagram thereof, and FIG. 3 is a block diagram of a conventional pulse count type FM demodulator. 1 ... Zero cross detector, 2 ... Counter, 3 ... Storage device, 4 ... ROM, 5 ... Mono multivibrator, 6 ... Low-pass filter, 7a, 7b, 7c ... Storage device, 8a, 8b, 8c ... three-state buffer, 9 ... storage device, 10 ... divider circuit, 11 ... counter.

Claims (2)

[Claims] 1. A counter that resets and counts another clock signal when a quantized FM signal passes through a zero point, a first storage device that stores a value immediately before this counter resets, and a first storage device. The output value of the storage device is used as an address value, the clock frequency is f, the carrier frequency of the FM signal is fc, the maximum frequency deviation of the FM signal is fd, the output value of the storage device is A, and the output data of the ROM is D. In this case, the ROM in which the data having the relationship of D = (f / 2A-fc) / fd is written and the reset signal when the zero point of the FM signal passes are divided by n (n is an integer of 1 or more). The values of the output data D of the ROM are sequentially stored by n write pulses having different phases, and the stored value of D is stored in the n
A digital FM demodulation device provided with n second storage devices that can sequentially take out the write pulses by delaying the phase of the write pulses for a fixed time. 2. The structure of n storage devices for storing the output data D of the ROM is arranged in the input stage of the ROM, and the address A of the ROM is stored instead of storing the output data D of the ROM. A digital FM demodulator according to claim 1.