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JPH0624192B2 - Dry etching method - Google Patents
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JPH0624192B2 - Dry etching method - Google Patents

Dry etching method

Info

Publication number
JPH0624192B2
JPH0624192B2 JP6925486A JP6925486A JPH0624192B2 JP H0624192 B2 JPH0624192 B2 JP H0624192B2 JP 6925486 A JP6925486 A JP 6925486A JP 6925486 A JP6925486 A JP 6925486A JP H0624192 B2 JPH0624192 B2 JP H0624192B2
Authority
JP
Japan
Prior art keywords
dry etching
insulating film
interlayer insulating
etching method
polyimide resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP6925486A
Other languages
Japanese (ja)
Other versions
JPS62224027A (en
Inventor
誠二 寒川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP6925486A priority Critical patent/JPH0624192B2/en
Publication of JPS62224027A publication Critical patent/JPS62224027A/en
Publication of JPH0624192B2 publication Critical patent/JPH0624192B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

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  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体基板上に多層配線を実現した半導体装
置の製造方法に関し、特に層間膜にSi 含有ポリイミド
樹脂を使用した場合のスルーホール形成方法に関する。
Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device in which multilayer wiring is realized on a semiconductor substrate, and in particular, formation of a through hole when an Si-containing polyimide resin is used for an interlayer film. Regarding the method.

〔従来の技術〕[Conventional technology]

従来、この種のSi 含有ポリイシド樹脂の異方性エッチ
ングを行った例はなく、Si を含まない通常のポリイミ
ド樹脂のエッチングは、Oガスのみで行われている。
Heretofore, there has been no example of anisotropic etching of this type of Si-containing polyside resin, and etching of a normal polyimide resin containing no Si is performed only with O 2 gas.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上述した従来のOガスのみでのポリイミド樹脂のエッ
チング方法で、Si 含有ポリイミド樹脂をエッチングす
るとSi 残渣が残る。
When the Si-containing polyimide resin is etched by the above-described conventional method for etching a polyimide resin using only O 2 gas, an Si residue remains.

また、OにCを含んだフッ素ガスを混合したガスを用
いた場合、反応生成物のスルーホール側壁への再付着、
デポジションなどが起る。
Further, when a gas in which fluorine gas containing C is mixed with O 2 is used, the reaction product is reattached to the side wall of the through hole,
Deposition etc. occurs.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のエッチング条件は、Si 残渣を除去するため、
フッ素ガスを混合し、また、再付着やデポジションをな
くすために、該フッ素系ガスをCを含まないものを選択
し、かつパワー密度を0.6W/cm2以下で行うことを
有している。
The etching condition of the present invention is to remove Si residue,
In order to mix the fluorine gas and to eliminate redeposition and deposition, the fluorine-based gas not containing C is selected, and the power density is set to 0.6 W / cm 2 or less. There is.

〔実施例〕〔Example〕

次に本発明について、図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第1図(a)に示す様に、半導体基板上に形成された酸化
膜2上のAl 配線1の上に未硬化のSi 含有ポリイミド
系樹脂液を塗布し、同図(b)のように、高温熱処理をし
てSi 含有ポリイミドからなる層間絶縁膜3を形成す
る。その後、同図(c)で示すごとく、Ti を3000Å
スパッタし、中間層4を形成する。その後、同図(d)の
ように、上層レジスト5をパターニングし、中間層を、
エッチングする。その後、中間層4とレジスト5をマス
クにO2+SF6 ガス6を用いて、Si 入りポリイミド膜を
エッチングする。この結果、第1図(e)となる。
As shown in FIG. 1 (a), an uncured Si-containing polyimide resin solution is applied on the Al wiring 1 on the oxide film 2 formed on the semiconductor substrate, and as shown in FIG. 1 (b). Then, high temperature heat treatment is performed to form an interlayer insulating film 3 made of Si-containing polyimide. After that, as shown in FIG.
Sputtering is performed to form the intermediate layer 4. After that, as shown in FIG. 3D, the upper layer resist 5 is patterned, and the intermediate layer is
Etching. Then, the Si-containing polyimide film is etched by using O 2 + SF 6 gas 6 with the intermediate layer 4 and the resist 5 as a mask. As a result, FIG. 1 (e) is obtained.

〔発明の効果〕〔The invention's effect〕

以上説明した様に、本発明は、Si 含有ポリイミド樹脂
膜のリアクティブイオンエッチングを、OとCを含ま
ないフッ素ガスを用いて、パワー密度0.6W/cm2
下で行うことで、Si 残渣,再付着,デボジションのな
いエッチングできるという効果がある。
As described above, according to the present invention, the reactive ion etching of the Si-containing polyimide resin film is performed with the fluorine gas containing no O 2 and C at the power density of 0.6 W / cm 2 or less. The effect is that etching can be performed without residue, redeposition, and devolution.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)乃至(e)は本発明の実施例の縦断面図である。 1……Al 配線、2……酸化膜、3……Si 含有ポリイ
ミド樹脂、4……Ti 膜、5……上層レジスト、6……
2+SFガス。
1 (a) to 1 (e) are vertical sectional views of an embodiment of the present invention. 1 ... Al wiring, 2 ... oxide film, 3 ... Si-containing polyimide resin, 4 ... Ti film, 5 ... upper layer resist, 6 ...
O 2 + SF 6 gas.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】配線導電層が形成された半導体基板上に未
硬化のSi 含有ポリイミド系樹脂液を塗布し、高温加熱
処理してポリイミドからなる層間絶縁膜を形成し、この
絶縁膜を選択的にドライエッチングする際に、該層間絶
縁膜上に薄い金属膜(例えばAl,Ti )を形成し、これ
をマスクに該層間絶縁膜を炭素(C)を含まないフッ素系
ガスとOを混合したガスを用いて、エッチングするこ
とを特徴とするドライエッチング方法。
1. An uncured Si-containing polyimide resin solution is applied onto a semiconductor substrate on which a wiring conductive layer is formed and heat-treated at high temperature to form an interlayer insulating film made of polyimide, and this insulating film is selectively formed. During dry etching, a thin metal film (eg, Al, Ti) is formed on the interlayer insulating film, and the interlayer insulating film is mixed with a fluorine-based gas containing no carbon (C) and O 2 using this as a mask. A dry etching method, characterized in that etching is performed by using the above-mentioned gas.
【請求項2】特許請求の範囲第(1)項記載のドライエッ
チング方法において、該層間絶縁膜のリアクティブイオ
ンエッチングをする際に、13,56MHz の高周波を
0.6W/cm2以下のパワー密度で、カソード側に印加
することを特徴とするドライエッチング方法。
2. The dry etching method according to claim 1, wherein a reactive ion etching of the interlayer insulating film is performed by applying a high frequency of 13,56 MHz to a power of 0.6 W / cm 2 or less. A dry etching method characterized in that the density is applied to the cathode side.
JP6925486A 1986-03-26 1986-03-26 Dry etching method Expired - Fee Related JPH0624192B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6925486A JPH0624192B2 (en) 1986-03-26 1986-03-26 Dry etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6925486A JPH0624192B2 (en) 1986-03-26 1986-03-26 Dry etching method

Publications (2)

Publication Number Publication Date
JPS62224027A JPS62224027A (en) 1987-10-02
JPH0624192B2 true JPH0624192B2 (en) 1994-03-30

Family

ID=13397407

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6925486A Expired - Fee Related JPH0624192B2 (en) 1986-03-26 1986-03-26 Dry etching method

Country Status (1)

Country Link
JP (1) JPH0624192B2 (en)

Also Published As

Publication number Publication date
JPS62224027A (en) 1987-10-02

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