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JPH0624228B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents
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JPH0624228B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Method for manufacturing semiconductor integrated circuit device

Info

Publication number
JPH0624228B2
JPH0624228B2 JP61089568A JP8956886A JPH0624228B2 JP H0624228 B2 JPH0624228 B2 JP H0624228B2 JP 61089568 A JP61089568 A JP 61089568A JP 8956886 A JP8956886 A JP 8956886A JP H0624228 B2 JPH0624228 B2 JP H0624228B2
Authority
JP
Japan
Prior art keywords
groove
integrated circuit
circuit device
insulating film
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61089568A
Other languages
Japanese (ja)
Other versions
JPS62245662A (en
Inventor
真一 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61089568A priority Critical patent/JPH0624228B2/en
Publication of JPS62245662A publication Critical patent/JPS62245662A/en
Publication of JPH0624228B2 publication Critical patent/JPH0624228B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B99/00Subject matter not provided for in other groups of this subclass
    • H10B99/10Memory cells having a cross-point geometry

Landscapes

  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、キャパシタを有する半導体集積回路装置の製
造方法に関し、特に微細なキャパシタで大きな蓄積容量
Csを得るためシリコン基板中に深い溝を形成したいわ
ゆる溝形キャパシタを有するメモリ装置の製造方法に関
するものである。
The present invention relates to a method for manufacturing a semiconductor integrated circuit device having a capacitor, and in particular, a deep groove is formed in a silicon substrate in order to obtain a large storage capacitance Cs with a fine capacitor. The present invention relates to a method of manufacturing a memory device having a so-called groove-shaped capacitor.

〔従来の技術〕[Conventional technology]

第2図(a)は、従来の溝形キャパシタ構造の断面を示
し、図中、1はシリコン基板、2は素子間分離用厚いシ
リコン酸化膜、3は溝、4はキャパシタ絶縁膜、5はキ
ャパシタ電極、6はスイッチングトランジスタ、7は不
純物拡散層である。このような溝形キャパシタでは、第
2図(b)の矢印で示すように、溝3上部の角が急峻なた
めキャパシタ絶縁膜4が薄くなっている。
FIG. 2 (a) shows a cross section of a conventional grooved capacitor structure, in which 1 is a silicon substrate, 2 is a thick silicon oxide film for element isolation, 3 is a groove, 4 is a capacitor insulating film, and 5 is a capacitor insulating film. A capacitor electrode, 6 is a switching transistor, and 7 is an impurity diffusion layer. In such a groove type capacitor, as shown by the arrow in FIG. 2 (b), the capacitor insulating film 4 is thin because the corners above the groove 3 are steep.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

従来の半導体集積回路装置は以上のように構成されてい
るので、溝上部の角でキャパシタ絶縁膜が薄くなり、電
界集中が起きやすいこと等から、絶縁破壊強度が低下
し、十分な電荷蓄積保持特性が得られないという欠点が
あった。
Since the conventional semiconductor integrated circuit device is configured as described above, since the capacitor insulating film becomes thin at the upper corners of the groove and electric field concentration is likely to occur, the dielectric breakdown strength is reduced and sufficient charge storage and retention is achieved. There was a drawback that the characteristics could not be obtained.

本発明は上記のような従来のものの欠点に鑑みてなされ
たもので、絶縁膜の耐圧不良を著しく改善し、電荷蓄積
保持特性が十分得られる半導体集積回路装置の製造方法
を得ることを目的とする。
The present invention has been made in view of the above-mentioned drawbacks of the conventional ones, and an object thereof is to obtain a method for manufacturing a semiconductor integrated circuit device in which the withstand voltage defect of an insulating film is remarkably improved and a sufficient charge storage and retention characteristic is obtained. To do.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体集積回路装置の製造方法は、シリ
コン基板に溝を形成した後、斜め上方から上記基板の表
面,溝の縁及びその側面上部に不純物を注入し、その後
基板を酸化し、これにより形成された酸化膜を除去する
ようにしたものである。
A method of manufacturing a semiconductor integrated circuit device according to the present invention comprises forming a groove in a silicon substrate, injecting impurities into the surface of the substrate, an edge of the groove and an upper portion of a side surface thereof from obliquely above, and then oxidizing the substrate. The oxide film formed by is removed.

〔作用〕[Action]

この発明においては、溝を形成したシリコン基板の表
面,及び溝上部に不純物を注入し、その後全面を酸化し
てできた酸化膜を除去するようにしたから、上記溝はそ
の上部の開口部が底部よりも広く、かつ上部の角は丸み
を滞びた形状となる。
In the present invention, the surface of the grooved silicon substrate and the upper portion of the groove are implanted with impurities, and then the oxide film formed by oxidizing the entire surface is removed. It is wider than the bottom and the top corners are rounded.

〔実施例〕〔Example〕

以下、本発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図(a)〜(e)は本発明の一実施例による半導体集積回
路装置の製造方法をその工程順に示し、図において1〜
7は第2図と同一のもので、1aはシリコン基板表面に
形成された不純物層、1bは溝3の側面上部に形成され
た不純物層、4a,4bはそれぞれ不純物層1a,1b
に形成されたシリコン酸化膜である。
1 (a) to 1 (e) show a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps thereof.
7 is the same as FIG. 2, 1a is an impurity layer formed on the surface of the silicon substrate, 1b is an impurity layer formed on the upper side surface of the groove 3, and 4a and 4b are impurity layers 1a and 1b, respectively.
It is a silicon oxide film formed on.

次に製造方法について説明する。Next, the manufacturing method will be described.

まず、シリコン基板1に溝3を形成した後、ウェハを回
転させながらその全面に斜め上方から例えばAr等の不
純物をイオン注入すると(第1図(a))、第1図(b)に示
すように、シリコン基板の表面及び溝の側面上部にそれ
ぞれ不純物層1a,1bが形成される。上記溝の底部
は、イオン注入中、第1図(a)に示すように、溝の上部
に遮ぎられて、注入層が形成されないまま保持される。
First, after forming the groove 3 in the silicon substrate 1, impurities such as Ar are ion-implanted into the entire surface of the wafer while rotating the wafer obliquely from above (FIG. 1 (a)), as shown in FIG. 1 (b). Thus, the impurity layers 1a and 1b are formed on the surface of the silicon substrate and on the upper portions of the side surfaces of the groove, respectively. During ion implantation, the bottom of the groove is blocked by the upper portion of the groove as shown in FIG. 1 (a), and is held without the implantation layer being formed.

次にシリコン基板1を酸素雰囲気中で酸化する。このと
き、上記不純物層1a,1bの領域の酸化速度は、イオ
ンが注入されていない部分に比べ数倍速いため、第1図
(c)に示すように不純物層1a,1bに形成されたシリ
コン酸化膜4a,4bの膜厚はシリコン基板1のイオン
注入されていない部分に形成されたシリコン酸化膜4よ
り厚くなる。
Next, the silicon substrate 1 is oxidized in an oxygen atmosphere. At this time, the oxidation rate of the regions of the impurity layers 1a and 1b is several times faster than that of the portion where no ions are implanted.
As shown in (c), the silicon oxide films 4a and 4b formed on the impurity layers 1a and 1b are thicker than the silicon oxide film 4 formed on the non-ion-implanted portion of the silicon substrate 1.

次いでこの酸化膜4a,4b,4を沸酸系のエッチング
液で除去すると、溝3はその上部の開口部が、底部より
も広く、かつ上部角は丸みを滞びた形状となる(第1図
(d))。
Next, when the oxide films 4a, 4b, 4 are removed by a hydrofluoric acid-based etching solution, the groove 3 has a shape in which the opening at the top is wider than the bottom and the top corner is rounded (first shape). Figure
(d)).

この後、従来と同じ方法で、溝3中にキャパシタ絶縁膜
4,キャパシタ電極5を順次形成して溝形キャパシタ構
造を得る。(第1図(e))。
After that, the capacitor insulating film 4 and the capacitor electrode 5 are sequentially formed in the groove 3 by the same method as the conventional method to obtain a groove type capacitor structure. (Fig. 1 (e)).

このように本実施例ではシリコン基板に溝の形成した
後、ウェハを回転させながら斜め上方から上記基板にイ
オンを注入し、その後基板に酸化膜を形成し、さらにこ
の酸化膜を除去するようにしたので、溝形キャパシタの
急峻な断面形状をなだらかな形状に変えることができ、
絶縁破壊強度の劣化を抑え蓄積電荷保持特性を向上でき
る。
As described above, in this embodiment, after forming the groove in the silicon substrate, ions are implanted into the substrate obliquely from above while rotating the wafer, and then an oxide film is formed on the substrate, and the oxide film is removed. Therefore, it is possible to change the steep cross-sectional shape of the groove type capacitor to a gentle shape,
It is possible to suppress the deterioration of the dielectric breakdown strength and improve the stored charge retention characteristic.

なお、上記実施例では溝形キャパシタについて説明した
が、本発明は溝形分離構造等の基板中に溝を有するデバ
イス全てについて適用できる。また、イオン注入時の不
純物は、半導体基板の酸化特性を変化させるものであれ
ばいかなるものでも良い。
Although the groove type capacitors have been described in the above embodiments, the present invention can be applied to all devices having a groove in a substrate, such as a groove type isolation structure. Further, the impurities at the time of ion implantation may be any impurities as long as they change the oxidation characteristics of the semiconductor substrate.

また、上記実施例では半導体基板の酸化特性を変化させ
るためにイオン注入法を用いたが、これは例えばスパッ
タリング法等のような物理的手段であればどのような方
法を用いてもよい。
Further, in the above embodiment, the ion implantation method is used to change the oxidation characteristic of the semiconductor substrate, but any physical method such as a sputtering method may be used.

また上記実施例では溝部の形成において、酸化膜を成長
させたが、これは窒化膜あるいは他の絶縁膜を成長させ
ても良い。
Further, in the above-mentioned embodiment, the oxide film is grown in the formation of the groove portion, but a nitride film or another insulating film may be grown.

〔発明の効果〕〔The invention's effect〕

以上のように本発明にかかる半導体集積回路装置の製造
方法によれば、シリコン基板に溝を形成した後、斜め上
方から上記基板にイオンを注入し、その後基板に酸化膜
を形成し、さらにこの酸化膜を除去するようにしたの
で、溝形キャパシタの急峻な断面形状をなだらかな形状
に変えることができ、絶縁膜の耐圧不良等を著しく改善
できる効果がある。
As described above, according to the method for manufacturing a semiconductor integrated circuit device of the present invention, after forming a groove in a silicon substrate, ions are implanted into the substrate obliquely from above, and then an oxide film is formed on the substrate. Since the oxide film is removed, the steep sectional shape of the groove type capacitor can be changed to a gentle shape, and there is an effect that the breakdown voltage defect of the insulating film can be remarkably improved.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例による半導体集積回路装置の
製造方法を工程順に示す断面図、第2図は従来装置の構
造を示す断面図である。 図中、1はシリコン基板、1a,1bは不純物層、2は
分離用絶縁膜、3は溝、4はキャパシタ絶縁膜、4a,
4bはシリコン酸化膜、5はキャパシタ電極、6はスイ
ッチングトランジスタ、7は不純物拡散層である。 なお図中同一符号は同一又は相当部分を示す。
FIG. 1 is a sectional view showing a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps, and FIG. 2 is a sectional view showing the structure of a conventional device. In the figure, 1 is a silicon substrate, 1a and 1b are impurity layers, 2 is a separation insulating film, 3 is a groove, 4 is a capacitor insulating film, 4a,
4b is a silicon oxide film, 5 is a capacitor electrode, 6 is a switching transistor, and 7 is an impurity diffusion layer. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】溝形キャパシタ部を有する半導体集積回路
装置の製造方法において、 半導体基板に深い溝を形成する第1の工程と、 上記溝及び基板の表面に斜め上方から不純物を注入し、
不純物注入層を基板表面,溝の縁及びその側面上部にの
み形成する第2の工程と、 その後全面を酸化して不純物注入層の絶縁膜膜厚が該絶
縁膜のそれ以外の部分より厚くなるように絶縁膜を形成
する第3の工程と、 その後、上記絶縁膜を除去する第4の工程とを含むこと
を特徴とする半導体集積回路装置の製造方法。
1. A method of manufacturing a semiconductor integrated circuit device having a groove-shaped capacitor portion, comprising: a first step of forming a deep groove in a semiconductor substrate; and an impurity being obliquely injected into a surface of the groove and the substrate.
The second step of forming the impurity injection layer only on the substrate surface, the edge of the groove and the upper part of the side surface thereof, and then oxidizing the entire surface to make the insulating film thickness of the impurity injection layer thicker than the other portions of the insulating film. A method of manufacturing a semiconductor integrated circuit device, comprising: a third step of forming an insulating film as described above; and a fourth step of removing the insulating film thereafter.
【請求項2】上記半導体基板はシリコンであり、上記絶
縁膜はシリコン酸化膜であることを特徴とする特許請求
の範囲第1項記載の半導体集積回路装置の製造方法。
2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor substrate is silicon and the insulating film is a silicon oxide film.
JP61089568A 1986-04-17 1986-04-17 Method for manufacturing semiconductor integrated circuit device Expired - Lifetime JPH0624228B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61089568A JPH0624228B2 (en) 1986-04-17 1986-04-17 Method for manufacturing semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61089568A JPH0624228B2 (en) 1986-04-17 1986-04-17 Method for manufacturing semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS62245662A JPS62245662A (en) 1987-10-26
JPH0624228B2 true JPH0624228B2 (en) 1994-03-30

Family

ID=13974414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61089568A Expired - Lifetime JPH0624228B2 (en) 1986-04-17 1986-04-17 Method for manufacturing semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0624228B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6469345B2 (en) 2000-01-14 2002-10-22 Denso Corporation Semiconductor device and method for manufacturing the same
US6482701B1 (en) 1999-08-04 2002-11-19 Denso Corporation Integrated gate bipolar transistor and method of manufacturing the same
US6864532B2 (en) 2000-01-14 2005-03-08 Denso Corporation Semiconductor device and method for manufacturing the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0824166B2 (en) * 1986-11-26 1996-03-06 松下電子工業株式会社 Method for manufacturing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6482701B1 (en) 1999-08-04 2002-11-19 Denso Corporation Integrated gate bipolar transistor and method of manufacturing the same
US6469345B2 (en) 2000-01-14 2002-10-22 Denso Corporation Semiconductor device and method for manufacturing the same
US6864532B2 (en) 2000-01-14 2005-03-08 Denso Corporation Semiconductor device and method for manufacturing the same
US7354829B2 (en) 2000-01-14 2008-04-08 Denso Corporation Trench-gate transistor with ono gate dielectric and fabrication process therefor

Also Published As

Publication number Publication date
JPS62245662A (en) 1987-10-26

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