JPH0624299B2 - Operational amplifier circuit - Google Patents
Operational amplifier circuitInfo
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- JPH0624299B2 JPH0624299B2 JP62170180A JP17018087A JPH0624299B2 JP H0624299 B2 JPH0624299 B2 JP H0624299B2 JP 62170180 A JP62170180 A JP 62170180A JP 17018087 A JP17018087 A JP 17018087A JP H0624299 B2 JPH0624299 B2 JP H0624299B2
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- 239000003990 capacitor Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＭＩＳＦＥＴで構成される演算増幅回路に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to an operational amplifier circuit composed of MISFETs.
従来の第２図に示すような演算増幅回路の周波数補償回
路としては、(1)容量と抵抗を直列に出力端子と第２図
中Ａ点との間に接続する方法(2)容量を出力端子２と第
２図中Ｂ点との間に接続する方法(3)第３図に示すよう
に容量Ｃ1を出力端子とゲート接地型のＭＯＳＦＥＴの
ソースとの間に接続し、ゲート接地型のＭＯＳＦＥＴの
ドレインをＡ点に接続して二つの定電流源でゲート接地
型のＭＯＳＦＥＴに電流を流すようにする方法などが知
られている。｛参考文献“ベーシック・モス・オペレー
ショナル・アンプリファイア・デザイン−アン・オーバ
・ビュー”ポール・アール・グレイ・アナログ・インテ
グレイテッド・サーキッツ”（“Basic MOS Operationa
l Amplifier Design-An Over View" Paul R.Gray,Analo
g Integrated Circuits）ｐ２８（１９８０）｝。As a conventional frequency compensation circuit for an operational amplifier circuit as shown in Fig. 2, (1) Method of connecting a capacitor and a resistor in series between the output terminal and point A in Fig. 2 (2) Outputting the capacitor Method of connecting between terminal 2 and point B in FIG. 2 (3) As shown in FIG. 3, connect the capacitor C 1 between the output terminal and the source of the gate-grounded MOSFET, and connect it to the gate-grounded type. There is known a method in which the drain of the MOSFET is connected to the point A so that a current flows through the grounded-type MOSFET by two constant current sources. {Reference "Basic Moss Operational Amplifier Design-Unover View" Paul Earl Gray Analog Integrated Circuits "(" Basic MOS Operationa
l Amplifier Design-An Over View "Paul R. Gray, Analo
g Integrated Circuits) p28 (1980)}.
第２図に示す演算増幅回路は、次のように動作する。Ｍ
１，Ｍ２は入力差動対で、Ｍ９はその定電流源である。
Ｍ１，Ｍ２それぞれのゲート間に入力された信号はＭ
３，Ｍ４，Ｍ１０〜Ｍ１５で構成されるカスコード段で
差動増幅およびシングル変換され、第１と第２のソース
フォロアでレベル・シフトされてＭ５，Ｍ６で反転増幅
されて出力される。このままでは、差動入力対とＭ５，
Ｍ６の出力段の２回、入力信号が反転するので、位相が
１８０°まわってしまう。それを避けるためには、周波
数補償回路を設ける必要があり、先ほど述べた(1)〜(3)
のような周波数補償方法が知られている。The operational amplifier circuit shown in FIG. 2 operates as follows. M
Reference numerals 1 and M2 are input differential pairs, and M9 is a constant current source thereof.
The signal input between the gates of M1 and M2 is M
Differential amplification and single conversion are performed in a cascode stage composed of M3, M4, M10 to M15, level shifting is performed by the first and second source followers, and inverting amplification is performed in M5 and M6 for output. In this state, the differential input pair and M5,
Since the input signal is inverted twice in the output stage of M6, the phase is rotated by 180 °. In order to avoid that, it is necessary to provide a frequency compensation circuit, which was mentioned earlier (1) to (3).
A frequency compensation method such as is known.
従来の技術で述べた(1)〜(3)の方法での問題点を次に述
べる。The problems with the methods (1) to (3) described in the related art will be described below.
(1)の方法では、高周波信号に対して容量はインピーダ
ンスが低くなるので、Ａ点から出力端子２へフィードフ
ォワードのパスができ、Ａ点からソースフォロア，ソー
ス接地トランジスタによって反転出力される信号とキャ
ンセルするようになり、高周波特性が悪化する。In the method of (1), since the impedance of the capacitance becomes low for the high frequency signal, a feedforward path can be made from the point A to the output terminal 2 and the signal which is inverted and output from the point A by the source follower and the source grounded transistor. As a result, the high frequency characteristics are deteriorated.
(2)の方法では、（−）入力端子１′へ印加された信号
に対して十分な補償ができない，カスコード段と容量に
よって生じるゼロ点を打ち消すのに、カスコード段に流
れる電流Ｉ2を差動入力対に流れる電流Ｉ1に比べ数倍以
上大きくする必要があり、カレントミラー回路を構成す
る両方のＭＯＳＦＥＴ列に同じ電流を流すので、Ｉ2＝
４Ｉ1とするならば、Ｉ1＋２×（４Ｉ1）＝９Ｉ1の電流
が差動入力対とカスコード段で消費され消費電流が大き
くなるなどの問題点が存在する。In the method (2), the current I 2 flowing through the cascode stage is adjusted to cancel the zero point caused by the cascode stage and the capacitance, which cannot sufficiently compensate the signal applied to the (−) input terminal 1 ′. It is necessary to increase the current I 1 flowing through the dynamic input pair by several times or more, and the same current is passed through both MOSFET trains forming the current mirror circuit. Therefore, I 2 =
If it is set to 4I 1, there is a problem that the current of I 1 + 2 × (4I 1 ) = 9I 1 is consumed by the differential input pair and the cascode stage, resulting in a large current consumption.
(3)の方法は、(1)と(2)の方法の問題点を解決するため
の方法である。Method (3) is a method for solving the problems of methods (1) and (2).
第３図を見るとわかるように、Ａ点から出力端子へのフ
ィードフォワードのパスはない。また、回路にできるゼ
ロ点を打ち消すためには、周波数補償回路のＭＯＳＦＥ
Ｔ ＭＣ２に大きな電流ＩCを流せばよく、カスコード
段の電流は差動入力対を流れる電流と同程度でよい。従
って、Ｉ2＝Ｉ1とし、ＩC＝４Ｉ1とすると、差動入力
対，カスコード段，周波数補償回路で消費される電流は
Ｉ1＋２×Ｉ1＋４Ｉ1＝７Ｉ1となり先ほど述べた(2)の
方法より小さくて済む。As can be seen from FIG. 3, there is no feedforward path from point A to the output terminal. In addition, in order to cancel the zero point that can be formed in the circuit, the MOSFE of the frequency compensation circuit
A large current I C may be passed through T MC2, and the current in the cascode stage may be about the same as the current flowing through the differential input pair. Therefore, if I 2 = I 1 and I C = 4I 1 , the current consumed by the differential input pair, the cascode stage, and the frequency compensation circuit is I 1 + 2 × I 1 + 4I 1 = 7I 1 , which was described above ( It is smaller than the method of 2).
また(2)の方法と違って、（＋）入力端子１，（−）入
力端子１′の二つの入力端子からの差動信号がシングル
信号へ変換されたＡ点で周波数補償されているので、両
方の入力端子へ印加された信号に対して同等の補償を行
なうことができる。Also, unlike the method of (2), the differential signals from the two input terminals of (+) input terminal 1 and (-) input terminal 1'are frequency-compensated at point A, which is converted to a single signal. , Equal compensation can be provided for signals applied to both input terminals.
以上述べたように、(3)の方法は(1)，(2)に比して優れ
た方法であるが、次のような問題点を持っている。As described above, the method (3) is superior to the methods (1) and (2), but has the following problems.
第２図を見るとわかるように周波数補償回路がない場
合、Ａ点の電圧はカスコード段がカレントミラー回路に
よりバランスしているので、Ａ′の点の電圧とほぼ等し
くなるように決まる。バイアス回路とダイオード接続さ
れたＭＯＳＦＥＴのために、カスコード段のＭＯＳＦＥ
Ｔは飽和領域に安定にバイアスされている。従って、
Ａ′点の電圧は安定しており、Ａ点の電圧も安定してい
る。As can be seen from FIG. 2, when there is no frequency compensation circuit, the voltage at point A is determined to be substantially equal to the voltage at point A'because the cascode stage is balanced by the current mirror circuit. Due to the bias circuit and the diode-connected MOSFET, the MOSFE of the cascode stage
T is stably biased in the saturation region. Therefore,
The voltage at point A'is stable, and the voltage at point A is also stable.
しかし、第３図に示したような周波数補償回路を挿入す
ると、ＭＣ１〜ＭＣ３から成る回路はカスコード段とバ
ランスしていないので、電圧のバイアス条件が変わりＡ
点の電圧がＡ′点の電圧と異なるようになり、カスコー
ド段のバランスがくずれてＭ１０，Ｍ３，Ｍ１２，Ｍ１
４の列とＭ１１，Ｍ４，Ｍ１３，Ｍ１５の列の各トラン
ジスタのバイアス条件が異なるようになり、動作点が不
安定になる。However, if the frequency compensating circuit as shown in FIG. 3 is inserted, the circuit composed of MC1 to MC3 is not balanced with the cascode stage, so that the bias condition of the voltage changes.
The voltage at the point becomes different from the voltage at the point A ', the balance of the cascode stage is lost, and M10, M3, M12, M1
The bias conditions of the transistors of the column 4 and the columns of M11, M4, M13, and M15 are different, and the operating point becomes unstable.
これを避けるためには、周波数補償回路のバイアス回路
を別に設け、ＭＣ３のドレイン電圧がＡ′点の電圧と等
しくなるようにバイアス回路の設計をしなくてはならな
い。このような事は、消費電力の増大と設計の困難さを
増大させる。また、別のバイアス回路で条件を決めてい
るので、プロセス変動によりバランスがくずれることが
あり、動作点の著しい不安定さを招くことになる。In order to avoid this, it is necessary to separately provide a bias circuit of the frequency compensation circuit and design the bias circuit so that the drain voltage of MC3 becomes equal to the voltage at the point A '. Such a thing increases power consumption and design difficulty. Further, since the condition is determined by another bias circuit, the balance may be lost due to the process variation, resulting in remarkable instability of the operating point.
以上述べたように、従来の技術にはいずれも問題点が存
在する。As described above, all the conventional techniques have problems.
本発明の目的は前述した問題点を解決し、高周波特性が
良好で動作点が安定化した周波数補償回路をもった演算
増幅回路を提供することにある。An object of the present invention is to solve the above-mentioned problems and to provide an operational amplifier circuit having a frequency compensating circuit having a good high frequency characteristic and a stable operating point.
本発明の演算増幅回路の構成は、ソースが共通に第１の
定電流源を介して第１の電圧源に接続された第１と第２
のＭＩＳＦＥＴから成る差動入力対と、前記差動入力対
を構成するＭＩＳＦＥＴと同じ導電性のＭＩＳＦＥＴで
構成される２段に縦積みされたカレントミラー回路と前
記カレントミラー回路にそれぞれのドレインが接続され
ゲートが共通にバイアスされソースがそれぞれ第２と第
３の定電流源を介して第２の電圧源に接続された前記第
１と第２のＭＩＳＦＥＴとは反対の導電性の第３と第４
のＭＩＳＦＥＴで構成されるゲート接地型ＭＩＳＦＥＴ
対とから成り、前記第１と第２のＭＩＳＦＥＴのドレイ
ンがそれぞれ前記第３と第４のＭＩＳＦＥＴのソースに
接続されたカスコード段と、前記カスコード段の出力節
点に第１のソースフォロアを介してゲートが接続され、
ドレインが出力端子に接続され、ソースが第２の電圧源
に接続された第５のＭＩＳＦＥＴと、前記カスコード段
の出力節点に前記第１のソースフォロアとは反対の導電
性の第２のソースフォロアを介してゲートが接続され、
ドレインが前記出力端子に接続され、ソースが第１の電
圧源に接続された第６のＭＩＳＦＥＴから成る出力段
と、周波数補償回路とから構成される演算増幅回路にお
いて、前記周波数補償回路が、前記カスコード段の出力
節点に互いに異なる導電性の二つの第７と第８のＭＩＳ
ＦＥＴのドレインが接続され、前記第７と第８のＭＩＳ
ＦＥＴのゲートは共通に前記第３と第４のＭＩＳＦＥＴ
のゲートと接続され、前記第７と第８のＭＩＳＦＥＴの
ソースはそれぞれ第４と第５の定電流源を介してそれぞ
れ前記第１と第２の電圧源に接続され、前記第７と第８
のＭＩＳＦＥＴのいずれか一方のソースと前記出力端子
との間に容量が接続されて構成されることを特徴とす
る。The configuration of the operational amplifier circuit according to the present invention is such that the sources are commonly connected to the first voltage source via the first constant current source.
Each of the drains is connected to the current mirror circuit and the current mirror circuit, which are vertically stacked in two stages and each of which is made up of a differential input pair composed of the MISFET and a MISFET having the same conductivity as the MISFET forming the differential input pair. And the gates are commonly biased and the sources are connected to the second voltage source via the second and third constant current sources, respectively, and the conductive third and third conductive layers opposite to the first and second MISFETs are provided. Four
Grounded MISFET composed of the following MISFETs
A pair of cascode stages in which the drains of the first and second MISFETs are connected to the sources of the third and fourth MISFETs, respectively, and a first source follower at an output node of the cascode stage. The gate is connected,
A fifth MISFET having a drain connected to the output terminal and a source connected to the second voltage source, and a conductive second source follower opposite to the first source follower at the output node of the cascode stage. The gate is connected via
In an operational amplifier circuit including a frequency compensation circuit and an output stage composed of a sixth MISFET having a drain connected to the output terminal and a source connected to the first voltage source, the frequency compensation circuit is characterized in that Two different conductive seventh and eighth MISs are provided at the output nodes of the cascode stage.
The drains of the FETs are connected, and the seventh and eighth MISs are connected.
The gates of the FETs are commonly used for the third and fourth MISFETs.
And the sources of the seventh and eighth MISFETs are connected to the first and second voltage sources via fourth and fifth constant current sources, respectively, and the seventh and eighth
Of the MISFET, and a capacitor is connected between the source and the output terminal.
本発明について図面を参照して説明する。 The present invention will be described with reference to the drawings.
第１図は本発明の典型的な実施例である。FIG. 1 is a typical embodiment of the present invention.
第１図において、Ｍ１〜Ｍ８はそれぞれ特許請求の範囲
で示した第１〜第８のＭＩＳＦＥＴに対応する。Ｍ９は
第１の定電流源、Ｍ１０，Ｍ１１はそれぞれ第２，第３
の定電流源の役割を果たす。Ｍ１２〜Ｍ１５は２段に縦
積みにしたカレントミラー回路を構成する。Ｍ１８〜Ｍ
２０，Ｍ２１〜Ｍ２３はそれぞれ第１，第２のソースフ
ォロアである。Ｍ１６，Ｍ１７はそれぞれ第４，第５の
定電流源の役割を果たす。Ｍ７，Ｍ８，Ｍ１６，Ｍ１７
と容量Ｃ1で周波数補償回路を構成する。この演算増幅
回路の動作は次のように働く。In FIG. 1, M1 to M8 correspond to the first to eighth MISFETs shown in the claims, respectively. M9 is a first constant current source, M10 and M11 are second and third, respectively.
Plays the role of a constant current source. M12 to M15 form a current mirror circuit that is vertically stacked in two stages. M18 ~ M
Reference numerals 20 and M21 to M23 are first and second source followers, respectively. M16 and M17 serve as fourth and fifth constant current sources, respectively. M7, M8, M16, M17
And the capacitance C 1 form a frequency compensation circuit. The operation of this operational amplifier circuit works as follows.
Ｍ１，Ｍ２，Ｍ９で構成される差動入力対に入力された
信号は、Ｍ３，Ｍ４，Ｍ１０〜Ｍ１５で構成されるカス
コード段で差動増幅およびシングル変換され、第１と第
２のソースフォロアでレベルシフトされてＭ５，Ｍ６で
反転増幅され出力される。The signal input to the differential input pair composed of M1, M2, and M9 is differentially amplified and single-converted by the cascode stage composed of M3, M4, M10 to M15, and the first and second source follower It is level-shifted by and is inverted and amplified by M5 and M6 and output.
また、この演算増幅回路の周波数補償は出力端子と図中
Ａ点の間で行なっており、差動入力（＋），（−）いず
れの入力端子からの信号に対しても同等な補償がなされ
る。また、Ａ点から出力端子へのフィードフォワードの
パスは存在しない。したがって、フィードフォワード・
パスのために高周波数で周波数特性が悪化するという問
題が生じない。さらに、周波数補償回路のＭＯＳＦＥＴ
Ｍ８に流れる電流を大きくし、かつ、カスコード段の
電流は差動入力対を流れる電流と同程度にすることによ
り、全体として低消費電力化が図れる。また、この周波
数補償回路の各トランジスタは、カスコード段の各トラ
ンジスタのバイアス条件と同一のバイアス条件になって
いるので、Ａ点の電圧をＡ′点の電圧と等しくでき、プ
ロセス変動などの影響を受けない構成となっており、動
作点の安定化が図られている。Further, the frequency compensation of this operational amplifier circuit is performed between the output terminal and the point A in the figure, and equal compensation is made for the signals from both the differential input (+) and (-) input terminals. It Also, there is no feedforward path from point A to the output terminal. Therefore, feedforward
There is no problem that the frequency characteristic is deteriorated at a high frequency due to the path. Furthermore, MOSFET of frequency compensation circuit
By increasing the current flowing through M8 and making the current in the cascode stage approximately the same as the current flowing through the differential input pair, the overall power consumption can be reduced. Further, since each transistor of this frequency compensation circuit has the same bias condition as that of each transistor of the cascode stage, the voltage at the point A can be made equal to the voltage at the point A ', so that the influence of the process variation or the like can be prevented. It has a structure that does not receive it, and stabilizes the operating point.
以上述べたように本発明によれば、周波数特性が良好
で、低消費電力で安定な動作点を持った演算増幅回路を
提供することができる。As described above, according to the present invention, it is possible to provide an operational amplifier circuit having good frequency characteristics, low power consumption, and a stable operating point.
第１図は本発明の一実施例を示す回路図、第２図は周波
数補償回路を持たない従来の演算増幅回路の回路図、第
３図は周波数補償回路を持つ従来例を示す回路図であ
る。 １，１′……入力端子、２……出力端子。1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional operational amplifier circuit having no frequency compensation circuit, and FIG. 3 is a circuit diagram showing a conventional example having a frequency compensation circuit. is there. 1, 1 '... Input terminal, 2 ... Output terminal.
Claims (1)
１の電圧源に接続された第１と第２のＭＩＳＦＥＴから
成る差動入力対と、前記差動入力対を構成するＭＩＳＦ
ＥＴと同じ導電性のＭＩＳＦＥＴで構成される２段に縦
積みされたカレントミラー回路と、前記カレントミラー
回路にそれぞれのドレインが接続され、ゲートが共通に
バイアスされ、ソースがそれぞれ第２と第３の定電流源
を介して第２の電圧源に接続された前記第１と第２のＭ
ＩＳＦＥＴとは反対の導電性の第３と第４のＭＩＳＦＥ
Ｔで構成されるゲート接地型ＭＩＳＦＥＴ対とから成
り、前記第１と第２のＭＩＳＦＥＴのドレインがそれぞ
れ前記第３と第４のＭＩＳＦＥＴのソースに接続された
カスコード段と、前記カスコード段の出力節点に第１の
ソースフォロアを介してゲートが接続され、ドレインが
出力端子に接続され、ソースが第２の電圧源に接続され
た第５のＭＩＳＦＥＴと、前記カスコード段の出力節点
に前記第１のソースフォロアとは反対の導電性の第２の
ソースフォロアを介してゲートが接続され、ドレインが
前記出力端子に接続され、ソースが第１の電圧源に接続
された第６のＭＩＳＦＥＴから成る出力段と、周波数補
償回路とから構成される演算増幅回路において、前記周
波数補償回路が、前記カスコード段の出力節点に互いに
異なる導電性の二つの第７と第８のＭＩＳＦＥＴのドレ
インが接続され、前記第７と第８のＭＩＳＦＥＴのゲー
トは共通に前記第３と第４のＭＩＳＦＥＴのゲートと接
続され、前記第７と第８のＭＩＳＦＥＴのソースはそれ
ぞれ第４と第５の定電流源を介してそれぞれ前記第１と
第２の電圧源に接続され、前記第７と第８のＭＩＳＦＥ
Ｔのいずれか一方のソースと前記出力端子との間に容量
が接続されて構成されることを特徴とする演算増幅回
路。1. A differential input pair having a first and a second MISFET whose sources are commonly connected to a first voltage source via a first constant current source, and the differential input pair. MISF
A current mirror circuit that is vertically stacked in two stages and is composed of MISFETs having the same conductivity as that of ET, the drains of the current mirror circuits are connected to the current mirror circuit, the gates are commonly biased, and the sources are second and third, respectively. Said first and second M connected to a second voltage source via said constant current source
Third and fourth MISFE of opposite conductivity to ISFET
A grounded MISFET pair composed of T, a cascode stage in which the drains of the first and second MISFETs are connected to the sources of the third and fourth MISFETs, respectively, and an output node of the cascode stage A MISFET having a gate connected through a first source follower, a drain connected to an output terminal and a source connected to a second voltage source; and the first MISFET at the output node of the cascode stage. An output stage comprising a sixth MISFET having a gate connected through a second source follower opposite in conductivity to the source follower, a drain connected to the output terminal, and a source connected to the first voltage source. And a frequency compensating circuit, wherein the frequency compensating circuit has two conductive nodes which are different from each other at an output node of the cascode stage. The drains of the seventh and eighth MISFETs are connected, the gates of the seventh and eighth MISFETs are commonly connected to the gates of the third and fourth MISFETs, and the sources of the seventh and eighth MISFETs are connected. Are respectively connected to the first and second voltage sources via fourth and fifth constant current sources, respectively, and the seventh and eighth MISFE
An operational amplifier circuit comprising a capacitor connected between one of the sources of T and the output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62170180A JPH0624299B2 (en) | 1987-07-07 | 1987-07-07 | Operational amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62170180A JPH0624299B2 (en) | 1987-07-07 | 1987-07-07 | Operational amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6412706A JPS6412706A (en) | 1989-01-17 |
| JPH0624299B2 true JPH0624299B2 (en) | 1994-03-30 |
Family
ID=15900170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62170180A Expired - Lifetime JPH0624299B2 (en) | 1987-07-07 | 1987-07-07 | Operational amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0624299B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4959622A (en) * | 1989-08-31 | 1990-09-25 | Delco Electronics Corporation | Operational amplifier with precise bias current control |
| CN107204748A (en) * | 2017-06-20 | 2017-09-26 | 成都锐成芯微科技股份有限公司 | Operational amplification circuit |
-
1987
- 1987-07-07 JP JP62170180A patent/JPH0624299B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6412706A (en) | 1989-01-17 |
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