JPH0624350B2 - Clock synchronization method - Google Patents

Description

DETAILED DESCRIPTION [Overview] In a clock generation circuit that selects one from a plurality of clock signals and synchronizes the frequency of the own clock signal, the frequency of each clock signal is within a trackable range of the own clock signal. By determining whether or not the input clock signal is within the followable range and performing frequency synchronization of the own clock signal, the synchronization establishment time is shortened and the decrease in frequency accuracy in the establishment process is reduced.

[Industrial application field]

The present invention relates to improvement of a clock synchronization system in a clock generation circuit.

In a communication network in which a plurality of devices are digitally connected to each other, it is necessary to synchronize the frequency of a clock signal which is a reference for the operation of each device. In such a case, the specific device (main device) distributes the clock signal generated in the own device to other devices (slave devices), and each slave device determines the frequency of the clock signal generated in the own device as the clock of the main device. The method of synchronizing with a signal is widely adopted.

In order to improve the reliability of the clock signal supply path, each slave device receives the clock signal not only from the master device but also from one or more slave devices, and the frequency is selected from the received multiple clock signals. A clock signal as a reference for synchronization is selected, and if an abnormality is detected in the selected clock signal, the clock signal is immediately switched to another normal clock signal.

At the time of switching the reference clock signal, the time required to establish frequency synchronization of the own clock signal is shortened as much as possible, and it is desired to realize a means that does not reduce the frequency accuracy of the own clock signal in the synchronization establishment process as much as possible.

[Conventional technology]

FIG. 3 is a diagram showing an example of a conventional clock synchronization system.

In FIG. 3, a plurality of clock signals CLK1 to CLKn supplied from other devices are transmitted to the selection circuit 1 and the disconnection detection circuits 41 to 4n.

The disconnection detection circuits 41 to 4n are respectively connected to the clock signal CL.
K1 to CLKn are monitored and the corresponding clock signal CL
When it is detected that K1 to CLKn are disrupted, the detection signals D1 to Dn are output and transmitted to the selection condition determination unit 5.

The selection condition determination unit 5 notifies the selection circuit 1 of one of the clock signals to which the detection signals D1 to Dn have not been transmitted as a selection target.

The selection circuit 1 selects the clock signal notified from the selection condition determination unit 5 and transmits it as the selected clock signal SCLK to the comparison circuit 2.

If the comparison circuit 2 compares the received frequency fs of the selected clock signal SCLK with the frequency fh of the own clock signal HCLK output by the clock oscillator 3, and determines that the frequency fs is within the range in which the clock oscillator 3 can follow. , Control signal CTL indicating the difference between frequencies fs and fh is transmitted to clock oscillator 3.

The clock oscillator 3 controls the frequency fh to synchronize with the frequency fs based on the received control signal CTL.

If the comparison circuit 2 determines that the frequency fs is outside the trackable range of the clock oscillator 3, it transmits the alarm signal ALM to the selection condition determination unit 5.

Upon receiving the alarm signal ALM, the selection condition determination unit 5 excludes the currently selected clock signal from the selection targets and notifies the selection circuit 1 of other clock signals as the selection targets.

The selection circuit 1 selects the notified clock signal as described above and transmits it to the comparison circuit 2 as the selection clock signal SCLK. The comparison circuit 2 also selects the selection clock signal SCLK and the self clock signal HCLK as described above. If it is impossible to follow the comparison, the alarm signal ALM is selected again and the selection condition determination unit 5
And request selection of another clock signal.

[Problems to be solved by the invention]

As is clear from the above description, in the conventional clock synchronization method, it is determined whether or not the clock oscillator 3 can follow the selected clock signal selected by the selection circuit 1.

Therefore, when the reference clock signal is switched, it takes time until frequency synchronization is established, and the frequency accuracy of the own clock signal in the establishment process may be reduced.

[Means for solving problems]

 FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, reference numeral 100 denotes a clock generating means which is built in the present clock generating circuit and which generates its own clock signal HCLK.

CLK1 to CLKn are clock signals that serve as a reference for frequency synchronization of the own clock signal HCLK generated by the clock generating means 100.

200 is provided according to the present invention, and each clock signal CLK
It is a judging means for judging whether the frequencies 1 to CLKn are within the followable range of the clock generating means 100.

300 is provided according to the present invention, and the frequency of the own clock signal (HCLK) generated by the clock generation means (100) is selected from among the clock signals having the frequencies determined by the determination means (200) to be within the followable range. It is a selection means for selecting a clock signal to be synchronized.

[Action]

The determination means 200 determines a clock signal that the clock generation means 100 can follow and notifies the selection means 300, and the selection means 300 notifies the clock generation means 100 from among the clock signals notified from the determination means 200. Since the clock signal that serves as a reference for synchronizing the own clock signal is selected, the clock generation means 100 can reliably follow the clock signal selected by the selection means 300, the time required for establishing frequency synchronization is shortened, and the self clock in the establishment process is reduced. The accuracy of the clock signal is also improved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing a clock synchronization system according to an embodiment of the present invention. The same reference numerals denote the same objects throughout the drawings.

In FIG. 2, the comparison circuit 2 and the clock oscillator 3 are shown.
In addition to the clock generating means 100 composed of, the selecting circuit 6, the comparing circuit 7, the clock oscillator 8 and the usability judging portion 9 are provided as the judging means 200, and the selecting circuit 1a and the selection condition judging portion 5a are included in the selecting means. It is provided as 300.

The comparison circuit 7 and the clock oscillator 8 have the same performances as the comparison circuit 2 and the clock oscillator 3, respectively.

In FIG. 2, a plurality of clock signals CLK1 to CL
Kn is transmitted to the selection circuit 1a and the selection circuit 6
Is also transmitted.

The availability determination unit 9 sends the clock signal CLK to the selection circuit 6.
1 to CLKn are cyclically selected at regular intervals and transmitted to the comparison circuit 7 as the selected clock signal SCLK1.

The comparison circuit 7 compares the received frequency fs1 of the selected clock signal SCLK1 with the frequency fh1 of the own clock signal HCLK1 generated by the clock oscillator 8 to obtain the frequency f
It is determined whether or not s1 is within the followable range of the clock oscillator 8, and if it is not possible, the alarm signal ALM1 is transmitted to the usability determining unit 9. The clock signal CLK1
Even if CLKn is interrupted, the comparison circuit 7 transmits the alarm signal ALM1.

The availability determination unit 9 receives the alarm signal ALM1 from the comparison circuit 7.
Not transmitted clock signals CLK1 to CLKn
On the other hand, the available signals E1 to En are selected by the selection condition determination unit 5
It is transmitted to a.

The selection condition determination unit 5a selects one of the clock signals CLK1 to CLKn to which the availability signals E1 to En are transmitted from the availability determination unit 9 and selects the selection circuit 1a.
To notify.

The selection circuit 1a selects the clock signal notified from the selection condition determination unit 5a and transmits it as the selected clock signal SCLK0 to the comparison circuit 2.

The comparison circuit 2 uses the selection clock signal SCLK as described above.
The frequency fs0 of 0 and the frequency fh0 of the own clock signal HCLK0 generated by the clock oscillator 3 are compared.
Since it has been determined that the clock oscillator 8 can follow the selected clock signal SCLK0, the selected clock signal SCL is also used by the clock oscillator 3 having the same performance as the clock oscillator 8.
It is possible to follow K0, and the comparison circuit 2 outputs the alarm signal ALM0.
The control signal CTL0 is transmitted to the clock oscillator 3 without outputting, and the frequency fh0 is synchronized with the frequency fs0.

As is apparent from the above description, according to the present embodiment, the selection circuit 6, the comparison circuit 7, the clock oscillator 8, and the usability determination unit 9 determine whether the clock signals CLK1 to CLKn can be followed by the clock oscillator 3. It is determined in advance, and based on the determination result, the selection condition determination unit 5a and the selection circuit 1
Since a selects the selected clock signal SCLK0, the selected clock signal SCLK0 having the frequency fs0 that the clock oscillator 3 can follow is selected, and it is not necessary to reselect the selected clock signal SCLK0, which is necessary for establishing frequency synchronization. The time is shortened, and the possibility that the accuracy of the frequency fh0 of the own clock signal HCLK0 in the establishment process is lowered is reduced.

〔The invention's effect〕

As described above, according to the present invention, in the clock signal generation circuit, the time required for establishing frequency synchronization at the time of switching the selection of the clock signal is shortened, and it is possible to prevent a decrease in frequency accuracy in the establishment process.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a clock synchronization system according to an embodiment of the present invention, and FIG. 3 is a diagram showing an example of a conventional clock synchronization system. In the figure, 1, 1a and 6 are selection circuits, 2 and 7
Is a comparison circuit, 3 and 8 are clock oscillators, 5 and 5
a is a selection condition determination unit, 9 is a usability determination unit, and 41 to 4
n is a disconnection detection circuit, 100 is clock generation means, 200 is determination means, 300 is selection means, ALM, ALM0 and ALM1 are alarm signals, CLK1 to CLKn are clock signals, CTL, CTL0 and CTL1 are control signals, D
1 to Dn are detection signals, E1 to En are usable signals,
HCLK, HCLK0 and HCLK1 are self clock signals, and SCLK, SCLK0 and SCLK1 are selected clock signals.

Claims (1)

[Claims] 1. A self clock signal (HCLK) generated by a clock generating means (100) which selects one of a plurality of clock signals (CLK1 to CLKn) to be received.
In the clock generation circuit for synchronizing the frequencies of (1) and (2), a determination unit (200) that determines in advance whether or not the frequency of each of the clock signals (CLK1 to CLKn) is within the followable range of the own clock signal (HCLK). , The self-clock signal (HC) generated by the clock generation means (100) from among the clock signals having the frequencies determined by the determination means (200) to be within the followable range.
A clock synchronization system, comprising: a selection unit (300) for selecting a clock signal for synchronizing the frequency of LK).