JPH0624373B2 - Communications system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system, and more particularly to a communication system with an improved processing method when a plurality of stations simultaneously transmit.

[Conventional technology]

In a communication system in which a plurality of stations are connected by a common transmission line, various processing methods have been proposed in order to prevent confusion when two or more stations transmit at the same time.

As one example thereof, a start bit is used in a communication system which is an asynchronous system and in which a line signal is "0" when a station transmitting "1" and a station transmitting "0" exist on the transmission line at the same time. There is a system in which the next one bit or several bits are used as a priority code for determining the priority of transmission, and a station with a higher priority continues transmission and a station with a lower priority stops transmission.

In other words, each station is configured to compare its own transmission signal with the line signal, and when the line signal is "0" even though it is transmitting "1", each station is configured to stop transmission and has priority over each station. It is assigned to a priority code, and the priority code is transmitted after the start bit. Then, when two or more stations start transmitting at the same time, the one with "0" following the assigned priority code continues to transmit, and the one with "1" appears to stop transmitting, which is confusing. Is prevented.

[Problems to be solved by the invention]

The processing method using the priority code is based on the premise that the corresponding bits of the priority code can be properly compared.

However, there is a problem that it is difficult to take a timing to properly compare corresponding bits because there is a time lag δ at which each station starts transmission and a transmission delay time d in the transmission line. is there.

Therefore, it is an object of the present invention to provide a communication system capable of suitably determining the timing of such comparison and performing the comparison of corresponding bits without error.

[Means for solving problems]

In the communication system of the present invention, a plurality of stations are connected by a common transmission line, communicate with each other in an asynchronous manner, and a station that transmits "1" and a station that transmits "0" exist simultaneously on the transmission line. In the communication system in which “0” is the line signal when performing, the comparing means for comparing the level of the transmission signal of itself and the level of the received line signal to detect the coincidence or non-coincidence of the levels of both signals, and the line signal Time τ _s after the fall of the start bit and time τ + τ _c (where τ _s
+ 2d <τ _c <τ, where d is the transmission delay time, τ
Is 1 bit time. ) A timing output means for outputting a comparison timing signal later, and a transmission control means for permitting transmission of a transmission signal if the output of the comparison means detects a match when the comparison timing signal is input, and a transmission control means for canceling if a mismatch is detected It is a feature of the configuration that at least one station having at least and is provided.

[Operation] In the communication system of the present invention, the time τ _s and the time τ _c , which are in the relationship of τ _s + 2D <τ _c <τ (d; transmission delay time, τ; 1 bit time), are introduced, and The comparison and the secondary comparison are performed.

Then, the first comparison using the time τ _s prevents the start bit of the station which started transmission with a delay from being compared with the bit of the priority code of the station which has started the transmission, A secondary comparison using τ + τ _c properly compares the bits of the corresponding priority codes.

[Examples] Hereinafter, the present invention will be described in more detail based on the examples shown in the drawings. FIG. 1 is a block diagram of an essential part of one station of a communication system according to an embodiment of the present invention, and FIGS. 2 and 3 are time charts for explaining the operation of the communication system shown in FIG. is there. The present invention is not limited to the embodiments shown in the drawings.

In the communication system 1 shown in FIG. 1, a plurality of stations are connected by a common transmission line 2. 20 shows one of the stations.

The communication system is an asynchronous NRZ communication system, and when a station transmitting "1" and a station transmitting "0" exist on the transmission line 2 at the same time, "0" becomes a line signal.

The line signal R _x captured by the line receiver 3 from the transmission line 2 is input to the CPU 4 as a reception signal.
Further, the AND circuit 8 and the exclusive OR circuit 18
Entered in. It also serves as a clear input signal for the idle signal counter 9.

The transmission signal U _{x of the} CPU 4 is given to the line driver 7 via the knot circuit 5 and the AND circuit 6, and the line driver 7 sends the sending signal T _x to the transmission line 2.

The output signal of the AND circuit 8 is connected to the clear input terminal of the bit time counter 13.

Therefore, both counters 9 and 13 are cleared by the falling edge of the reception signal R _x .

When the idle signal counter 9 is cleared, the idle signal I _x becomes “0”, and since the idle signal I _x is input to the AND circuit 11 via the knot circuit 10, it passes through the AND circuit 11. The clock signal is input to the idle signal counter 9 to start counting. Then, for example, after an idle time τ _w that is slightly longer than the bit frame length, the idle signal I _x =
It becomes "1".

When the idle signal I _x = “1”, the AND circuit 11 cuts the clock signal, and the idle signal counter 9 enters the hold state. Also, while counting, the AND circuit 8
The received signal R _x that has been cut by can be input to the bit time counter 13.

The idle signal I _x is input to the CPU 4. Further, it becomes a reset input of the mask flag 17, and the mask flag 17 is reset at the rising edge thereof.

Now, when the falling edge of the output signal of the AND circuit 8 is input to the one-shot circuit 12, a pulse is output after a time τ _s .

Further, the bit time counter 13 cleared at the falling edge of the output signal of the AND circuit 8 is
Counting is started with a clock given through, and a pulse is output every 1-bit time τ. The pulse is input to the one-shot circuit 14, and the one-shot circuit 14 outputs the pulse after a time τ _c from the rising edge of the input pulse.

The output pulses of the one-shot circuits 12 and 14 become the comparison timing signal C _x via the OR circuit 15 and become the clock input of the D flip-flop 16.

On the other hand, the reception signal R _x and the transmission signal U _{x of the} CPU 4 are input to the exclusive OR circuit 18, and the output signal of the comparison signal D _x is the D input of the D flip-flop 16.

Therefore, the D flip-flop 16 reads the comparison signal D _x at the rising edge of the comparison timing signal C _x .

The output on the negative side of the D flip-flop 16 becomes the set input of the mask flag 17 formed of the RS flip-flop. The idle signal I _x is input to the reset input.

Mask flag 17 is set on the falling edge to the set input and reset on the rising edge to the reset input. The negative side output is input to the CPU 4 and also to the AND circuit 6 as the mask signal M _x .

The CPU 4 transmits the idle signal I _x =
Check "1" to confirm that the transmission line 2 is not used, and output the transmission signal U _x . Then, after outputting the transmission signal U _x , the mask signal M _x is checked,
If it is not masked, it is determined that the transmission has been completed, and if it is masked, it is determined that the transmission has been stopped, and retransmission is performed.

In this case, the exclusive OR circuit 18 serves as the comparison means, and the one-shot circuits 12, 14 and the bit time counter 13 and the OR circuit 15 serve as the timing output means.
Further, the AND circuit 6, the D flip-flop 16 and the mask flag 17 constitute transmission control means.

Next, referring to FIG. 2, the operation when two stations simultaneously transmit will be described. However, the two stations are station A and station B,
The signal of the station A is attached with a subscript a, and the signal of the station B is attached with a subscript b.

Station A starts transmission at time t ₀ , and station B starts transmission at time δ
_It is assumed that the transmission is started at time t ₁ delayed by _one . However, δ ₁ <d.

The transmission signal T _a of the A station becomes a signal T _a ′ delayed by the transmission delay time d from the time t ₀ and reaches the B station. On the other hand, the transmission signal T _{b from} the B station reaches the A station as a signal T _b ′ delayed by the transmission delay time d from the time t ₁ .

The reception signal R _a of the A station is a product signal of the transmission signal T _{a of} its own station and the signal T _b ′ of the B station. On the other hand, the received signal R _b in B station is a product signal of the signal T _{a 'from} sending signal T _b and A station of its own station.

The comparison timing signal C _{a at the} A station is the received signal R _a
Time τ from the falling edge corresponding to the start bit of
the first pulse after _s and time τ from the falling edge
The second pulse after + τ _c and the third and subsequent pulses every time τ from the previous pulse.

Here, the following relationships are established.

τ _s + 2d <τ _c <τ To give a specific example, d = 1 μs, τ = 10 μs, τ _s =
2.5 μs and τ _c = 7.5 μs.

Similarly, in station B, the first pulse, time τ + τ, is received after time τ _s from the falling edge of the start bit of the received signal R _b.
After _c , the second pulse, and the comparison timing signal C _b having the third and subsequent pulses is generated every time τ from the previous pulse.

The start pulses are compared with each other in the first pulse of the comparison timing signals C _a and C _b . That is, those that have started transmission by this first pulse are subject to priority determination by the following bit comparison, but those that have not yet started transmission are no longer subject. Therefore, if the time τ _s is increased, the targets of priority order determination by bit comparison are expanded, and if the time τ _s is decreased, the targets are decreased and the one that starts the transmission first becomes dominant. .

Below the second pulse of the comparison timing signals C _a and C _b ,
This is to obtain the timing for properly comparing the corresponding bits of the priority code. From the perspective of the own station, the partner station can start the transmission by a time τ _s + d later than the transmission start time of the own station (as will be described later, the maximum time that can start the transmission later is τ _s + d), and the transmission delay time d for the transmission signal of the partner station to reach its own station.
Therefore, there is a possibility that the corresponding bits may be temporally displaced by the time τ _s + 2d. Therefore, the relationship of τ _s + 2d <τ _c should be established.

Now, returning to the relationship between the stations A and B, the start bits are compared with each other at the time of the first pulse of the comparison timing signals C _a and C _b of each station, and there is no merit. Therefore, both stations continue to transmit the transmission signals U _a and U _b .

At the timing of the second pulse, the comparison signal D _{a of} station A =
"1" indicates disagreement. Therefore, the mask signal M
_a is output, and the sending of the transmission signal U _a is stopped by the AND circuit 6. On the other hand, at the station B, the comparison signal D _b =
Since they match with “0”, the transmission of the transmission signal U _b is continued.

Thus, in the relation between the A station and the B station, the 0th bit a ₀ , b
The comparison of _0s determines the priority. The station A, which has stopped the transmission, confirms that the idle signal I _a = “1” has been obtained after the transmission of the signal T _b ′ from the station B is completed, and retransmits.

In the above description, the shift start time δ <d between station A and station B δ <d
However, the same applies to the case of d ≦ δ <τ _s + d.

However, when τ _s + d ≦ δ, the result is as shown in FIG.
That is, FIG. 3 shows that from the transmission start time t _{0 of} station A, time δ ₂
Although delayed by a time t ₂ to B station is a case where transmission is started, τ _{s +} d <δ Since a _2, a first pulse mask signal by M _b of the comparison timing signal C _b in B station
Occurs, and the transmission of the transmission signal U _b is centered. Therefore, it cannot be the target of priority determination by bit comparison, and station B needs to perform transmission after station A completes transmission.

〔The invention's effect〕

According to the present invention, a plurality of stations are connected by a common transmission line, communicate with each other in an asynchronous manner, and a station that sends "1" and a station that sends "0" simultaneously exist on the transmission line. In a communication system in which sometimes "0" is a line signal, a comparison unit that compares the level of a transmission signal of itself with the level of a received line signal to detect a match or mismatch between the levels of both signals, and a start of the line signal Time τ _s after the falling of the bit and time τ + τ _c (however, τ _s + 2d
<Τ _c <τ, where d is a transmission delay time and τ is a 1-bit time. ) A timing output means for outputting a comparison timing signal later, and a transmission control means for permitting transmission of a transmission signal if the output of the comparison means detects a match when the comparison timing signal is input, and a transmission control means for canceling if a mismatch is detected There is provided a communication system characterized in that at least one station having at least one is provided, whereby even if there is a time lag in the transmission signals of two or more stations, the corresponding bits can be compared at appropriate timings. Since it can be performed, it becomes possible to preferably determine the priority order by the bit comparison method.

[Brief description of drawings]

FIG. 1 is a block diagram of an essential part of one station of a communication system according to an embodiment of the present invention, and FIGS. 2 and 3 are time charts for explaining the operation of the communication system shown in FIG. (Description of symbols) 1 ... communication system 2 ... transmission line 3 ... line receiver 4 ... CPU, 6 ... AND circuit 7 ... line driver 9 ... idle signal counter 12 ... one-shot circuit 13 ... Bit time counter 14 One-shot circuit 15 Ao circuit 16 D flip-flop 17 Mask flag 18 Exclusive OR circuit U _x Transmission signal T _x Transmission signal R _x Received signal, I _x ... idle signal C _x ... comparison timing signal D _x ... comparison signal, M _x ... mask signal.

Claims (1)

[Claims] 1. When a plurality of stations are connected by a common transmission line and communicate with each other in an asynchronous manner, and a station transmitting "1" and a station transmitting "0" exist simultaneously on the transmission line. In a communication system in which "0" is a line signal, comparing means for comparing the level of its own transmission signal with the level of the received line signal to detect a match or mismatch between the levels of both signals, and a start bit of the line signal Time τ _s after the fall of τ and time τ + τ _c (where τ _s + 2d <τ
There is a relationship of _c <τ, d is a transmission delay time, and τ is a 1-bit time. ) A timing output means for outputting a comparison timing signal later, and a transmission control means for permitting transmission of a transmission signal if the output of the comparison means detects a match when the comparison timing signal is input, and a transmission control means for canceling if a mismatch is detected A communication system comprising at least one station having at least