JPH0624382B2 - Line adapter - Google Patents

Description

Detailed Description of the Invention A. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device, and more particularly to a line adapter (or line adapter) of a communication control device. The communication controller is used to manage transmissions in a teleprocessing environment where multiple user terminals are connected by transmission lines.

B. SUMMARY OF THE DISCLOSURE A line adapter (or line adapter) (1) of a communication control unit scans a teleprocessing line (26) connected to it, so that a bidirectional serial link (1)
2) -on this link the data and control information is divided into frames and slots-through the line (26)
And a circulating scanning device FES (10) for exchanging information with. Since the FES (10) and the serial link both operate at their respective timings, the interface FES to adapt the FES scan to the serial link (12) structure.
A (11) is provided. This FESA (11)
On the one hand the data and control information sent from the LIC (20) to the FES (10) via the inbound serial link (24), and on the other hand from the FES (10) via the outbound serial link (22). LIC (20)
And temporary storage means (36, 38, 40, 42) for storing data and control information transmitted to the.

Access to said storage means by FES, outbound serial link and inbound serial link is time-divisionally permitted by the arbitration logic based on the relative priority of the operation of said elements in the line adapter (1) of the communication controller. .

C. The prior art and its problems The main purpose of line adapters (or line adapters) is to enable groups of transmission lines to exchange information with the central control unit (CCU) of the communication control unit, each line being individually associated with the CCU. Connection is unnecessary.
Therefore, the line adapter includes scanning means for periodically scanning the line. Such line adapters have already been disclosed in European Patent Application Publication Nos. EP-A 0048781 and 0.
No. 0777863. In the line adapter, the transmission line connected to the user's terminal device,
Information is exchanged with the scanning means via a line interface circuit (LIC) reorganized into LIC units. Each L
The IC unit can contain up to eight LICs and is connected to the scanning means by means of a parallel bus and suitable connectors, which are quite large in size and occupy space in the computer and are expensive.

Thus, with the parallel bus between the LIC and the scanning means,
The connectivity of the communication controller is limited.

These disadvantages have been found in EP-A 023
Serialization realized between the LIC of each line adapter of the communication control device and the line scanning means (referred to as the front end scanning device FES in the cited patent) by multiplexing the information exchanged by the LIC as described in No. 2437. It has been removed by sending it over the sync link.

Thus, with a serial link, the LIC device and multiplexer interface can be implemented, if desired, outside the computer frame of the communication controller, i.e., at its periphery, thus providing connectivity, LIC switchability, and overall performance. improves.

However, the introduction of a serial link into a line adapter usually requires significant modification of the scanning means hardware and microcode, and, even more importantly, technical and economic considerations. From the known scanning means and the scanning device microcode, and introducing a suitable interface between said scanning means and the serial link.

Therefore, it is an object of the present invention to interface a parallel interface of an FES (as implemented, for example, in the IBM 3725 Communication Controller) with a serial interface of a serial link (hereinafter referred to as front end scanning device adapter FESA). ) Is to provide.

In the present invention, FES is the master device and FESA is F
The information presented by ES must be obtained directly. Similarly, when the FES needs the information from a given line X, the FESA must have that information ready.

More generally, another object of the invention is
Even if the operation timing of ES and serial link is asynchronous, F
It is an object of the present invention to provide a line adapter having a FESA interface that allows time-division access to information sent via FESA by ES, FES serial link and scanner microcode.

D. Means for Solving the Problems To achieve these objects, a line adapter (or line adapter) of the present invention provides a data interface between a line interface circuit connected to a transmission line and a central controller of a communication controller. And a bidirectional serial link by a frame provided for exchanging control information, the frame comprising data slots and control slots such that a pair of data slots and control slots correspond to each transmission line for scanning the transmission lines. A line adapter including scanning means for exchanging information with a line interface circuit via the scanning means and the serial link independently operating at their own timing, and the scanning means interfacing with the serial link. It is characterized by including the interface means of.

According to the invention, the line adapter (1) comprises a FESA interface (11) for interfacing a periodic scanning means (FES) and a serial link connected to the LIC, both the FES and the serial link having their respective timings. Can be operated by. Therefore, FESA
, On the other hand, via an inbound serial link
Data and control information sent from the FES to the FES from the FES to the LI via the outbound serial link.
C and storage means for temporarily storing data and control information transmitted to the teleprocessing line.

Access to the storage means by FES, outbound serial links and inbound serial links is time shared by the arbitration logic based on the relative priorities of the device operations within the line adapter of the communication controller.

E. EXAMPLE FIG. 2 shows an overall view of a system in which the present invention can be used.
The communication control device CC is Massi G.G.I., issued by Dunod Co. in 1979. Gilbert J. E. (G.Macchi, JEGu
ilbert) Co-authored “Data Communication” (Tele-informatique) -First
It is an element of a teleprocessing network of the type disclosed in chapter 0-. In the communication control device, the central control device C
CU is a terminal device T and a central processing unit CPU1, CPU
Process the data sent to and from. The unit CCU is a multi-channel (MP) unit of the central processing units CPU1 and CPU2 via channel adapters CA1, ...
X) connected to the bus. The device CCU is also connected to the terminal device T via line adapters LA1, ..., LAn connected to the CCU bus.

FIG. 1 shows an outline of a line adapter (or line adapter) 1 such as LA of FIG. Such a line adapter 1 includes a microprocessor 16 for executing the microcode included in the illustrated microcode storage device 17.
And the scanning logic specified by the FES (front end scanning device) 10, the details of which are European patent application publication EP-A 00 for a communication line adapter of a communication control device.
Described in No. 48781-.

In said patent, the data transmitted or received by the user terminal device via the transmission terminal device and the line interface circuit (LIC) is transmitted via the parallel bus to the scanning means and the LI.
Exchanged between C.

In the present invention involving the FESA interface between the FES 10 and the LIC, the data exchange between the LIC 20 and the scanning means is a multiplexing circuit (MUX) 14 as described below.
And well performed by the serial link 12.

In addition to FES10, serial link 12 and MUX14,
The line adapter according to the invention comprises a FESA (FES adapter) 11 for adapting the parallel interface of the FES 10 to a serial link structure, as will be explained later in connection with FIG.

According to the invention, FESA 11 must be transparent to FES. This means that the scanning activity of FES10 is based on European Patent Application Publication Nos. EP-A 0048781 and 0.
It is executed as if connected to the LIC by a parallel bus as described in 0777863.

The scanning timing of FES is briefly shown in FIG. Scanning a given line X includes a receive phase and a transmit phase, each of which includes seven steps (0-6) provided by ordering logic (not shown). When the scan of line X is complete, the scan of line (X + 4) usually follows.

However, the FES synchronous scan protocol is interrupted by microcode asynchronous operations requiring immediate read or write access to the LIC's registers at the end of the line scan.

FIG. 3 represents the concept of solving the asynchronous problem according to the invention. The outbound serial link (OSL) processes the information sent on line Y and the inbound serial link (ISL) processes the information received from line Z while the FES performs the scan on line X.

Furthermore, while FES scanning generally requires 2.8 μs per line, the time allotted to lines Y and Z for OSL and ISL processing is 3.9 μs, and ISL and OSL are further shifted by a constant delay d.

Thus, the main problem solved by the FESA 11 in accordance with the present invention is the asynchronous problem between the several components connected to it, which need to be able to exchange information. Since it is implemented between the FES 10 of the line adapter 1 and the serial link 12, the FESA must meet the individual user's four requirements: FES hardware, FES microcode, OSL and ISL. Therefore, as explained later, FESA is FES
Storage means is included between 10 and the serial link 12. The storage means is a data RAM (36, 38) as shown in FIG.
And the control RAMs (40, 42) are well implemented. In the figure, each arrow indicates a possible information flow between the serial link slot and the RAM and between the RAM and the FES. The flow of these pieces of information requires implementation of the interface logic described later.

However, another problem that FESA should solve is R
Each user has access to AM (36, 38, 40, 42) in arbitration of priority. In the present invention, this is also performed by the arbitration logic described below.

Although the above problems and their solutions can be easily generalized, in the present specification European Patent Application Publication EP-A 00
IBM 3725, as described in 48781.
An FES 10 similar to that included in the line adapter of the communication controller will be described more clearly and without limitation to the invention.

Further, the FESA design should not have a strong impact on the FES performance. The FESA must handle the FES and microcode requirements (discussed briefly below) as in the IBM 3725 design. That is, these requests are serviced by FESA at the highest priority, while serial link outbound and inbound requests are serviced at lower priority.

The principle of the FES scanning mechanism can be understood by referring to FIGS.

Fig. 1 shows that FES / FESA has eight LIC2s, for example.
0 connected by the serial link 12 and the MUX 14. Each LIC has a serial transmission line 26 connected to a user terminal device (T) 28 via a modem 30.
Support up to books.

As described in the aforementioned EP-A 0048781 and EP-0077863, each line adapter includes a scanning device for performing scanning of the line by a certain progressive scanning method. 2 in synchronous operation mode
The time interval between two line scans must be shorter than the time interval between two bits transmitted or received.
In the above example, the maximum scanning speed of the device of the invention was 3500.
00 received or transmitted bits per second (transmission over 4 lines is also called "full duplex" transmission). This scanning capability is automatically distributed over the number of connected lines. If there is one line, it is possible to operate at 256000 bits / sec. If there are 4 lines, it can be operated at 64000 bits / sec, and if there are 32 lines, it can be operated at 9600 bits / sec.
As mentioned above, the line is connected to the scanning device by the LIC. In the preferred embodiment, each LIC circuit can be connected to one or four lines. It is possible to provide 1 to 8 LIC circuits-each mounted on a so-called LIC card and connected to the scanning device. The number of LIC circuits connected automatically changes the line scan. When eight LIC circuits are installed in the order 0-7, the line scan is always performed by the FES described in the above patent application in the following order.

First line of first LIC (line 0), second LI
First line of C, ..., LIC installed last
First line, then the second line of the first LIC (line 1), the second line of the second LIC, ..., The second line of the last installed LIC, then First LI
C third line (line 2), second LIC third line, ..., Last attached LIC third line, finally first LIC fourth line (line) 3), scanning is performed in the order of the fourth line of the second LIC, ..., And the fourth line of the last mounted LIC, and returns to the first line of the first LIC. Another L
If there is only one line in the IC circuit, then that one line is scanned four times the other line. Of course, the FESA according to the present invention is easily adaptable to FES with other scanning schemes.

Interface between FESA and FES FESA is FE as described below in connection with FIG.
Interface logic for S (68, 70, 7
2), but since FES10 is not affected by the presence of FESA, EP-A-EP 0077
Represents a line for a normal interface, as described in 863. The most important parts of it are: Asynchronous operation is a new timing tag, FESA
That is, it signals an asynchronous microcode operation in the line frame construction device.

The function of the lines for these interfaces will become apparent later in this specification.

Interface operation between the FESA and the serial link The FESA according to the invention also provides the interface means (60, 61, 62, 63) with the serial link. In order to facilitate understanding of the interface means, first, the serial link structure will be described with reference to FIG. 4 (FIGS. 4A to 4C).

Serial information is spread in both directions in successive frames 44 (Fig. 4B).

• Within each frame, two 8-bit slots-one for exchanging data and another for passing control information-are dedicated to each connected device (Fig. 4B).

Superframes consisting of 32 frames are used to exchange up to 32 different control information with 32 devices connected via 32 transmission lines.

A given frame transfers the same type of control information to all 32 devices.

FIG. 4C shows the allocation of frames herein.
As used herein, the central scanning device is a 32 teleprocessing unit.
Control the line. In this superframe configuration, all frames are dedicated to one predetermined control register, multiple storage controller or line register of the LIC. 32
Line interface device is 8 lines of 4 lines each
It is realized by an interface coupling device (LIC).

Data slot contents (data burst) shown in FIG. 4A
Is independent of the number of frames. Depending on the data traffic, the data burst can vary between 0 and 5 bits.

To simplify the line interface level hardware, the data slots in both directions (reception and transmission) are not configured the same.

-In the receive data slot, the valid data bit field is the delimiter "1" -0 followed by bit 6-
The right side is restricted by. Received data slot bit 7 (X
REQ) is set by the transmit portion of the line interface device requesting that data be transmitted from the scanning device.

-In the transmission data slot, the valid data bit field is preceded by the delimiter "1" -0 until bit-1-
The left side is restricted by. Transmission data slot bit 0
(C) is set by the scanner and sends modem control information (clear or transmit ready) associated with the data burst (C = X21 transmit mode control bit).

The control slot configuration is the same in both directions (transmit and receive).

Control information is set in bits 1-6. Bit 0 is set to "1" in all control slots of frame 31, allowing both ends of the serial link to check and maintain superframe sync.

On the serial link, the bits are encoded by a differential Manchester code.

At the end of each frame, a specific code violation pattern is transmitted by each transmitting portion to allow the opposite receiving portion to detect the beginning of the next frame.

For 4 MBPS transmission, the frame duration is 125 μs and the superframe lasts 4 ms.

FESA RAM To solve the problem of asynchronousness between the four FESA users (ISL, OSL, FES and FES microcode) -each operating at its own timing-in order to solve the problem of RAM (36 , 38, 40, 42)
Are realized in the FESA 11 according to the present invention. These RAMs are temporary storage means and are capable of buffering data and controllers coming from or sent to the line.

The general flow of data between the FESA and its users, and within the FESA 11 itself is shown in FIG. In this figure, the data and control buses are shown in a single line for simplicity, and the FESA and FES10 or serial link 1
Interfaces between 2 are dashed lines (52, 54) respectively
Is displayed. Each constituent block of the FESA 11 will be described in detail later.

Of note regarding the general data flow of FESA is that the data and control slots provided by the ISL-serial link 12-are transmitted in bursts to the ISL interface 56 and the process logic (60,61).
Is processed according to the steps provided by. Thus, the data is stored in the "received data RAM" 38 in the appropriate format. The stored data is FES
Are held so that they can be scanned bit by bit via the data bit interface 70. The control data slots provided by the ISL are likewise stored in a suitable format in the "inbound control RAM" 40, while at the same time some specific control registers (LIC now, LIC wideband) directly needed for FES or microcode. Are sent directly to scan control logic 72 via line 71 (discussed below in connection with FIG. 13).

When transmitting the data and control information provided by the FES to the serial link 12 at its own timing and outputting to the LIC and the user's line, the data and control information are "transmit data RAM" 36 and "outbound control RAM". “42” are loaded respectively. This is performed via the data bit transmission interface 73 and the control interface 68, respectively. Transmission data RA
Once loaded into M36, O for outbound transmission
The data information sent to the LIC over the SL is processed by the outbound data processing logic 62 and the OSL interface 58.

On the other hand, when loaded into the outbound control RAM 42, the control information sent to the LIC via the OSL is available for outbound transmission and is executed by the outbound control process logic 63 and the OSL interface 58. The control process logic 63 is responsible for fetching the control word from the outbound control RAM and therefore provides it with the necessary timing signals.

Next, the process logic 61 and the OSL interface 5
8 and the corresponding operation will be described in more detail, but the point to note is that the information available in the transmit data RAM 36 and the outbound control RAM 42--corresponding to the information transmitted on a given line--is exactly what it does. OSL when representing the data and control slots corresponding to that line
Is to be taken into account.

The flow of information in the inbound direction follows the same rules. IS
When displayed by ISL via L interface 56, the information slot (data + control) for a given line is processed by inbound data processing logic 60 and inbound control processing logic 61, respectively. Thus, the line data and control information are stored in the appropriate format in the receive data RAM 38 and inbound control RAM 40, respectively. The stored information is retained for use in transmission to FES 10 via receive data bit interface 70 and control interface 68. Transmission to the FES occurs simultaneously with the next "receive scan" of the FES for the line under consideration.

Of course, since FES10, ISL24, OSL22 and scanner microcode operate at asynchronous timing, the relative priority when they access RAM (35, 38, 40, 42) is within line adapter 1. It must be arbitrated according to the required priority.

Therefore, according to the present invention, the arbitration means 100 is provided. The arbitration means is not shown in FIG. 5, but is shown in FIG.

Further, FIG. 5 shows the FESA control register unit 66. It exchanges control information with the FES control bus 80 via the control interface 68. Unit 66 may include various control registers: error report registers, FESA diagnostic registers, etc., but they are not part of the present invention.

As such, the control register unit primarily includes the FESA control register, each bit of which is used to control a particular mode of operation of the FESA. The possible operating modes of FESA are shown below.

The FESA can be in a reset state in a "reset RAM" state, a "freeze" state, or a "free running" mode. This allows normal operation of FESA.

Reset FESA The reset FESA command is a control lead coming from the FES and is active while the FES is reset (compare FES / FESA interface).

In FESA, this command resets all logic (resets latches, including control register bit 0) but initializes the reset of the FESA's RAM when the reset FESA goes inactive at the interface. Register bit 1 (reset RAM)
Set.

When the reset RAM is complete, the FESA operates in what is called a "free running" mode.

When the FESA is in the reset state, the FESA does not cause signal conversion at OSL. This lack of translation is decoded by MUX (14) as a reset command.

FESA Reset Latch: (Control Register Bit 0) This reset is activated in microcode by setting FESA Control Register Bit 0.

This causes FESA to be reset independently of FES.

This command has the same characteristics as the reset FESA, except for the following: Control register bit 0 remains on during the reset.

• Control register bit 1 is not automatically set by hardware.

The "reset rat" mode ends with a reset of bit 0 by microcode.

The next state may be "reset RAM", "freeze", or "free running". This depends on whether the bit in the control register is set by microcode at the time the reset latch is removed.

FESA reset RAM: (bit 1 of control register) The FESA reset RAM is started by either: -automatically starting at the end of reset FESA (FE
SA control register bit 1 is set by hardware).

Initiated by microcode (set bit 1) while control register bit 0 is reset.

The operation resets the RAM of all FESAs.

Finally, if control register bit 2 (freeze) is set by microcode when bit 0 is reset, FESA is in "free running" mode (control register bit 1 is automatically reset), Or go to "freeze" mode.

FESA freeze: (bit 2) In this state, use of the FESA function is prohibited.
The serial link is not operational (playing idle characters).

However, the FESA RAM can be loaded or dumped.

Freezing is fully controlled by microcode-by setting and resetting control register bit 2.

Bits 1 and 2 while Bit 0 is being reset
If is set, the freeze is valid at FESA upon completion of the reset RAM operation.

To get into the free running state, the microcode must reset the freeze. However,
Free-running state is correct only if the following sequence is observed (serial links are synchronized).

-Reset Latch, Reset RAM, Freeze or-Reset Latch, Freeze If FESA is stopped by Freeze during free running, it cannot be restarted by directly removing the Freeze.

Another limitation of freezes is that microcode access to FESA is programmable only if both FES and FESA are in freeze mode or if both FES and FESA are in free running mode. Two bits are provided (bits 3, 4) -a "control RAM address extension" bit and a "control RAM swap" bit (described below).

FESA Information Flow: Details of the various information (data, control) flows described above will be described with reference to corresponding hardware.

FIG. 6 shows inbound data transmission, that is, ISL interface 56, inbound data processing logic 6
0, the reception data RAM 38, and the data bit reception interface 70, the ISL line 24 to the FES1
2 shows the structure of the FESA hardware for sending data to 0.

The data RAMs (36, 38) include, for each line, a receive and transmit data buffer + (set of control bits).

In a receive operation, FESA uses the ISL data slot (4th
(Shown in the figure) to receive a burst of data from the line and serialize the data to feed the FES bit by bit.

If 32 lines are to be connected to the line adapter 1, the receive data RAM 38 has a receive SDF byte 74, a receive SDF control byte 76, respectively.
Receive PDF0 byte 78 and receive PDF1 byte 82-
SDF represents a "serial data field" and PDF represents a "parallel data field", which requires 32 areas (L0 to L31) of 4 bytes.

The reference RAM field is the working area of the FESA and assembles or serializes the data bursts in the manner described below.

The size of the received data burst is not constant. Each LIC fills its assigned data slot with the data available at the time the ISL scans that line.

Thus, the length of the received data burst depends on the speed of the line, and in the present invention it is zero due to the serial link used.
Similar serial links with fixed length bursts can work with the FESA provided by the present invention, although it can vary from 5 bits to 5 bits.

The ISL data slot is processed by FESA as follows: If there is a data burst transmission request (bit 7 of the receive data slot in Figure 4A), then the next transmit operation, as described for control RAM management. Then, the received data RA is sent in the send control 2 field (Fig. 8) together with the "line available" information coming from the inbound control RAM.
Stored in M38.

Received data bits are shifted to the right by the inbound data processing logic 60 and one delimiter is set to the left of the data bits in preparation for shifting the bits into the FES.

The table below shows an example of the contents of the bytes (74, 76, 78, 82) (Ri: received bit number i).

If bit 0 of the byte SDF control 76-called PDF0 valid-is set to "1", PDF0 will
Means set by a data burst coming from. Therefore, a new data burst is
Before loading one of the DF fields, the ISL determines the PDF field to be loaded with the new data burst and the ISL and PDF1 valid bits.
The valid bit of must be monitored. This is done by update logic 88 as described below. Bit 1 of the same byte (called PDF1 valid) has a similar meaning. Bit 2 of the same byte (called the PDF pointer) is the PD that should be loaded into the SDF shift register 84.
Refers to F (0 or 1).

FIG. 8 shows the ISL as described later (in FIG. 7).
An overview of the operations performed by ISL data processing logic 60 according to a number of ISL steps (ISLS0-S3) generated by timing step generation mechanism 110 is shown.

As shown in FIG. 8: After ISL step S0-writing the PDF transmission control (data burst transmission request) to the transmission data RAM as described above-in step S1, whether the bit PDF0 is valid or not. To check the data SDF
Read reception control.

In step S3, if bit 0 is off (PDF0 field is not valid), the ISL data process loads a new data burst at address PDF0,
Set bit 0 on.

If bit 0 is on, FESA loads a new data burst into address PDF1 and sets bits 1 and 2 of the receive control character field in SDF control register 86. The result is immediately loaded into the reception data RAM 38.

The receive data RAM 38 in which the processed data burst is to be written is provided by an address bus 81 containing the address of the slot and frame of the considered line in the serial link when a write command is activated. It is specified. This address is generated by the address decoder 108 shown in FIG. 7 and receives the clock from the ISL counter 118-which provides the slot and frame count of the serial link.

After being stored in the reception data RAM 38, the data burst can be transmitted to the FES 10 bit by bit via the data bit reception interface 70.

As a result, the SDF 74 and the SDF control 76 are loaded into the SDF shift register 84 and the SDF control register 86 (both of which are the data bit reception interface 7).
Run at 0).

FIG. 9 shows that the SDF 74 stored in the data RAM 38 is 1
An overview of the operations performed when they are to be transmitted bit by bit to the FES is shown.

When the FES scans the line it is receiving, it generates a bit of the receive service request on line 83, and the FESA is associated with that line and in the FES S1 step (FIG. 9),
Receive S previously loaded in SDF register 84
The DF74 is shifted to provide the data bits to the FES in step S2, unless the SDF is empty.

If the SDF shift register 84 is empty, the FESA takes out one of the PDFs (PDF0 or PDF1 whichever is valid) and sends the SDF in step S4 or step S6.
The data register transfer is restarted at the next FES scan while reloading the cyst register 84. FESA at this point
The process of is determined by the reception control bit described above. The monitoring and updating of the control bits is performed by the update logic 88, which is a simple combinational logic (AND / OR gate).

Decoding bits 0, 1, 2 by the update logic 88 results in an output command as shown in the table below: The operation steps S1, S2, S4 and S6 shown in FIG.
Corresponds to the same steps as the receiving operation performed by the FES 10, as described in EP-A-0077863.

These steps are derived from the FES step counter in the FES. Each receive operation performed by the FES is described as spanning a period of 7 steps (S0-S6). Therefore, the reception / transmission signal clock is FES / FE
Since it is fed to the FESA at the SA interface, it is easy to find the same step in the FESA by splitting the received / transmitted signals.

Fig. 7 shows ISL / OSL interface (56, 58)
Shows the structure of. Manchester encoded information from the ISL line 24 is received via the receiver circuit 126 and buffered in the Manchester decoder 116. Of course, if the information is encoded with another code, the decoder 11
6 is replaced accordingly.

All the necessary clock signals are easily available from the oscillator 120 operating at 49 MHz, for example. The frequency is divided in the frequency divider 122 to improve the symmetry of the signal.

The decoder 116 supplies an 8-bit information slot to the ISL shift register 106, a count pulse is supplied to the ISL counter 118 for each slot, and a slot and frame count are generated.

Since the slots correspond to lines multiplexed on the serial link, the decoding provided by address decoder 108 is used to address inbound control RAM 40 and receive data RAM 38 (bus 79).

The first 8-bit slot supplied to the ISL shift register 106 is a data slot, and the second slot is a control slot. The same applies hereinafter (compare with FIG. 4). Data and control slots are provided by the ISL shift register 106 to the ISL data PDF register 94 and IS.
Each is sent to the L control buffer 96 (its identification is made by an 8-bit count).

The data / control slot has inbound data processing logic 60 and inbound control processing logic 6
When each reaches 1, it is still a form dependent on the form on the serial link (compare FIG. 4: data burst contains data field delimiters). Thus, the data slots are processed or shifted so that they can be loaded bit by bit into the receive data RAM in a format that can be transferred to the FES.

However, this sloting may not be compulsory if another type is selected for the serial link.

The structure of the OSL interface 58 is similar to that of the ISL interface. Therefore, the information slot (data / control) is outbound data RAM and control R
It is supposed to be transmitted from AM (36, 42) to OSL.

Since the data slot fetched from the transmission data RAM 36 is in the format supplied by the FES, the outbound data processing logic 62-is to be loaded into the parallel register forming the OSL data PDF 90.
Mainly processed (shifted) in the shift register.

The control information is read from the outbound control RAM and outbound control process logic 63-the control RAM.
It can be functional depending on the type of control slot as stored in-via OSL control buffer 92.
Loaded in.

Data and control slots are alternately O
The data is transmitted to the SL shift register 104, serialized into the Manchester encoder 114, and output to the OSL line 22 via the driving mechanism 124.

The slot and frame OSL counters 112 are also implemented as in the inbound direction. The slot / frame count is used by the address decoder 102, which is to supply the slot and frame address (FIG. 11, bus 81) to the transmit data RAM 36, and the OSL timing step generator 98.

FIG. 11 shows outbound data transmission, that is, data bit transmission interface 73, transmission data R as described above.
AM36, Outbound Data Processing Logic 62
And a global structure of FESA hardware for transmitting data from FES 10 to OSL line 22 via OSL interface 58.

For each scanned line transmit operation, FESA
The data RAM requests the data bits from the FES to assemble the transmitted data burst with the burst size specified by the microcode per line, then the LIC request causes the OSL line to be allocated in the data slot assigned to that line. Send a data burst to.

The transmission data RAM 36 has S lines for each of the 32 lines.
DF byte 130 and its associated SDF control byte 132, PDF byte 134 and its associated PDF
Includes control byte 136.

The contents of the bytes are shown in the table below. X of data bytes
i is F through the data bit transmission interface 73.
Represents a data bit i transmitted by ES10.

SDF control byte 132 in transmission data RAM 36
Bits 2 to 4 specify the transmit burst size by the following encoding: FIG. 10 shows the data bit transmission interface 73 according to the work steps obtained from the FES steps S0 to S6.
An overview of the operations performed within is shown.

As shown in Figure 10: In step S1, the SDF field 130 is loaded into the SDF register 138 and its contents are examined. S
Unless the DF register 138 is full, the data bit transmit interface 73 causes the FESA to submit a bit service request (line 91) to the FES in step S2. The FES sends the data bit to line 89 and calls the bit service request reset signal in step S3 (line 9).
3, FIG. 11).

The transmit data bits are assembled in the transmit SDF field 138.

If SDF 138 is full (burst size), then two possibilities arise: If the PDF fetch bit in SDF control register 140 is off (ie OSL is still RAM 36 to PDF 13).
If you have not picked up 4), there is no process to do.

If the PDF fetch bit is on, the FESA submits a bit service request in step S2 to get a new send bit from the FES. In step S3, SDF
138 is loaded into the PDF 142 and further into the PDF field 134 of the RAM 36. SDF register 138
Are reset to determine the burst size for the next line, as described below. Finally, the "fetched PDF" is reset. The "transmit bit" just obtained from the FES is shifted in the SDF register 138 and the SDF register 138 is reloaded into the SDF field 130 of the transmit data RAM 36 in step S6.

SD depending on the burst size allowed for the line being scanned
To fully test F, a simple circuit included in interface 73 is provided, as shown in FIG.

In the circuit shown in FIG. 12, if the line corresponding to burst size = 5 is activated (when the FES scans a line whose data slot has 5 data bits).
When FES sends bit 7 onto the line, the burst must be fully examined. As a result, the corresponding NAND gate is activated and its output is ORed with the output of another NAND. Thus, the gate 148 outputs a "SDF full" signal each time a burst on a given line is full.

Data transfer from RAM 36 to OSL When the OSL scans line Y, the FESA fetches the transmit PDF 134 of this line and processes the contents of PDF 134, SL (serial link) as described in connection with FIG. ) Form prepares the PDF for transfer to the outbound data slot.

The PDF process involves a right shift of the data bits, with delimiter 1 set to the left of the data bits.

Loading of data slots depends on "line available" information.

Line Available: If processed, the processed PDF 134 will be serialized into the outbound data slot.

If there is no request to send, the FESA sends an empty data slot (bits 0-6 are set to 0, bit 7 is set to 1).

Line use prohibited: • Bits 0 to 7 of the data slot are set to 0.

At a given time, if SDF and PDF are both full and FESA does not receive a request from line 26, FESA stops requesting bits from FES and waits for the next request to send. The extracted PDF is the PD
A working bit set by the OSL process when F is sent to the LIC. It's waiting SDF1
30 can be loaded into the PDF field 134.

After the SDF is transferred to the PDF, the extracted PDF will be
Reset by FESA.

Control RAM As shown in FIG. 13, the control RAM has two parts: an outbound control RAM 42 and an inbound control RAM.
40-each buffering control information in the outbound and inbound directions for 32 lines.

The stored control information is the control register of the MUX 14, 32
LIC registers for book lines as well as 32 sets (1 set / set) managed by FESA to process the lines
Line) working registers.

The FES and microcode control information for the MUX and LIC (MUX and LIC write registers) is stored in the outbound control RAM 42, waiting for the appropriate slot of the output frame to be sent by OSL.

The MUX and LIC register information that enters FESA at ISL is stored in inbound control RAM 40, waiting for FES and microcode requests.

FIG. 13 shows the structure of FESA for exchanging control registers between FES 10 and LIC.

The MUX, LIC or line control slot--provided by the ISL control buffer 96 (FIG. 7) of the ISL interface 56--is loaded into the inbound control RAM 40 via the inbound control process logic 61. The ISL RAM addressing bus 160 is
Provided by the slot-frame address decoder 108 as described in connection with the figure.

The inbound control process logic 61 includes an ISL step counter 170 (FIG. 14) -providing four ISL steps S0-S3. In step S0, the contents of the current control slot are loaded into inbound control RAM 40. Steps S1-S3 are used to update the scan control register 72 (FIG. 5) as described above. First register: "LIC Current Register" is updated when the line control register is received at frame 13. The second register: "LIC Wideband" is updated when LIC type information is received at frame 7 and the given L
Tells if the IC is broadband (wideband lines are scanned four times more than non-wideband lines).

The control interface 68 is responsible for fetching from the inbound control RAM 40 the control information needed by the FES or microcode to control the line.

In step S1 of FES reception timing, the FES sends the control information regarding the connected modem to the inbound control RA.
Input from M40. In step S6 of the FES transmission timing, the FES supplies the control information to the modem. As described above, this information is obtained in step S6 of the FES transmission timing.
Is loaded into the outbound control RAM 42.

The control interface 68 is mainly a register (buffer)
And gate logic. It is also used by microcode to write control information to the outbound control RAM 42 or read control information from the inbound control RAM 40.

R by the user of RAM (FES or serial link)
The address of the AM can have two different (equivalent) forms: Each control RA, as can be seen from the FES interface.
The M address is a concatenation of the line address and the register address.

As it can be seen from the serial link, it is the concatenation of the slot number and the frame number (most significant 4 bits).

FES addressing: Serial link addressing: The RAM swap bit (bit 4 of register 66) can be set by microcode and the table below allows full read / write access to the FESA control RAM.

RAM is time shared by FES and two serial link interfaces (inbound and outbound).

The FESA must arbitrate the various RAM requests in synchronism with them.

FESA first monitors the FES interface and then
Identify when S needs access to RAM.

The remaining time is available for two serial link interfaces. It is time-shared as follows: In the control process, OSL always has a higher priority than ISL.

The priority depends on the FES receive / transmit operation, since the data process must avoid contention between ISL and FES reception on the one hand and contention between OSL and FES transmission on the other hand.

It can be seen that in the case of the control information process, the problem of arbitrating the RAM access is solved by the arbitration logic 100 shown in FIG. 14, and in the case of the data process a very similar circuit is realized.

Figure 14 shows the RAM users: FES, OS
L, ISL, three counters (162, 166, which generate the steps necessary to access the control RAM).
170).

SIR represents step S1 of FES reception timing. The FES step counter 162 is triggered by the receive / transmit signals of the FES interface and the OS step counter 166 is triggered by the occurrence of the OSL data bit 0 time-indicating the start of the OSL data process.

Similarly, the ISL step counter 170 is triggered by the ISL data bit 0 time.

The FES timing has the highest priority. Therefore, the hold state does not occur in the step counter 162.

On the other hand, the OSL step counter 166 is the OR gate 16
Suspended by FES step through 4 but ISL
The step counter 170 includes an OR gate 164 and an OSL.
It is held by the OR gate 168 resulting from the combination of outputs of step S0.

For data process arbitration logic, OSL and I
The SL step counter is held in the same manner except that the OSL step counter is held by the FES transmission timing and the ISL step counter is held by the FES reception timing.

F. As described above, according to the configuration of the present invention, the serial link can be introduced into the line adapter without requiring a great change in the hardware of the scanning means and the microcode.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a transmission subsystem of a communication device incorporating a FESA interface according to the present invention, FIG. 2 is a schematic block diagram of a system in which the present invention is used, and FIG. 3 is an FE.
Schematic diagram of information exchange between S and serial link, FIGS. 4A to 4C are diagrams showing the structure of serial link information flow, FIG. 5 is a schematic block diagram of the FESA interface, and FIG. 6 is from the serial link. FES for sending data to FES
FIG. 7 shows the structure of A, FIG. 7 shows the structure of the interface between FESA and serial link, FIG. 8 shows the steps of the process of inbound serial link data, and FIG. 9 sends data from FES to FESA FIG. 10 is a diagram showing the operations necessary for transmitting data from FESA to FES, and FIG. 11 is a diagram showing the structure of FESA for transmitting data from FES to a serial link. FIG. 12, FIG. 12 shows a logic circuit for detecting a complete data slot, FIG. 13 shows a structure of an FESA for transmitting control information between the FES and the serial link, and FIG. 14 shows a data RAM. It is a figure which shows the arbitration circuit which gives a selective access. 1 ... Line adapter, 10 ... FES, 11 ... FE
SA, 12 ... Serial link, 14 ... MUX, 16 ...
Microprocessor, 17 ... Microcode storage device, 20 ... LIC, 22 ... OSL line, 24 ...
ISL line, 26 ... Teleprocessing line, 3
6, 38 ... Data RAM, 40, 42 ... Control RA
M.

Claims (1)

[Claims] 1. A scanning means (10) essentially operating to scan a parallel line interface circuit periodically at its own timing, and information is transmitted and received on a bit basis between the scanning means. Data bit reception / transmission interface (68), (7
0), (73) and information transmission and reception on a burst basis between the input and output serial links (22) and (24) that are selectively connected to the transmission line and operate at their own timing. Serial link interface of incoming and outgoing credit (5
6), (58) front-end scanner adapter (1
1), and a line adapter for transmitting and receiving information on a burst basis between the plurality of line interface circuits each connected to a plurality of transmission lines through the serial link.
In (1), the front-end scanning device adapter (11) receives information input to the input serial link interface (56) and the transmission interface (68), (73) from each transmission line. Receive / transmit memory (38) that temporarily stores each
(36), (42) and the data slot and control slot corresponding to each transmission line in response to the request of the credit process logic (60), (61) related to the credit serial interface (56). Burst format information is loaded into the memory at predetermined data and control fields, while the corresponding fields of the memory are responsive to the respective requests of the data bit receive interface (70) and control interface (68). Read information from the above interfaces (70), (68)
From the scanning means to the scanning means on a bit-by-bit basis, and the memory of the memory in response to the request of the credit process logic (62), (63) related to the credit serial link interface (58). A transmission control means for transferring information from a predetermined field to the outgoing serial link interface in a burst format, and access to the memory by each of the scanning means, incoming serial link and outgoing serial link are predetermined. A line adapter having a front-end scanning device adapter, which is transparent to the scanning means, characterized in that it comprises arbitration means for controlling so as to execute in time division based on priority .