JPH0625657B2 - Method and device for inspecting printed matter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method and apparatus for inspecting the design of printed matter.

As shown in FIG. 1, a conventional printed matter pattern inspection apparatus takes out image information while scanning a printed matter 1 in a width direction by a line sensor camera 2, and outputs an image from a rotary encoder 4 attached to a cylinder 3 of a conveying system. Then, by synchronizing the scanning of the camera 2, the sample pattern 5 (Fig. 2) is divided into a large number of small pixels in a matrix.

The density of each of these pixels is similarly compared with the corresponding small pixel of the sample pattern 6 (FIG. 2) recorded in the memory in the same manner to detect the presence or absence of a defect.

In such a pattern inspection, if there is a positional deviation in the width direction of the transport system as shown in FIG. 3, among the gradations 7 obtained from the sample, the gradations obtained from the sample for the three pixels marked with a circle. When compared with the corresponding 3 pixels of 8, even if there is no defect in the sample pattern, it is erroneously determined that there is a defect.

As one method for preventing this, it is conceivable to set a large allowable value with respect to the gradation difference between the samples.

However, this causes a decrease in defect detection accuracy and is not necessarily a good countermeasure.

As a method without such a problem, it means to correct the positional deviation of the sample pattern with respect to the sample pattern,
Various methods have been devised.

The first is to detect the position of the design of the printed matter in the width direction as shown in Japanese Patent Application No. 56-146355 by the applicant of the present application, and this position change writes the data of the sample design in the sample pixel data memory. As a result of comparison between the time and the time of reading the data of the sample pattern, if the difference is a predetermined value or more, the sample pattern data at that time is written in the sample pixel data memory.

However, according to this method, a device for detecting the position change of the printed matter in the width direction and for correcting the position shift according to the position change information is required, which causes problems of hardware complexity and cost increase.

The second is shown in Japanese Examined Patent Publication No. 55-45948 and the like, which is a method of comparing a sample pixel with pixels corresponding to several points in the vicinity of the sample pixel.

However, this method has a problem in that the deterioration of inspection accuracy cannot be avoided.

The third is related to Japanese Patent Application No. 57-151,118 filed by the applicant of the present application. The widthwise pattern gradation data of the sample (hereinafter referred to as sample line data) is the widthwise pattern gradation data corresponding to the sample (hereinafter referred to as sample line data). ), A plurality of sample rows shifted by an allowable positional deviation for each sample are referred to for detection, and a pattern inspection is performed by the sample row and the sample row that are closest in phase to the sample row. It was.

However, in this method, depending on the positioning accuracy of the sample transport system, the number of sample rows required is extremely large, and since the transport system needs to be highly accurate, the position can be further simplified and reduced in cost. The development of a deviation correction method has been desired.

〔Overview〕

The present invention has been made in consideration of the above points, and compares the pattern data taken out from the sample printed matter with the pattern data previously taken out from the sample printed matter and stored in the memory to judge the quality of the pattern. One of the sample row data detected for each row from the sample and the sample row data stored in the memory is displaced relative to the other on a pixel-by-pixel basis to form a plurality of data. The sample row data and the sample row data are compared with each other according to the above data, and the positional deviation between the two data is obtained from the positional relationship between the two data when the level difference becomes the minimum value,
The present invention provides a method and apparatus for inspecting a pattern on a printed matter, which corrects one of the addresses of the both data based on the amount of positional deviation.

〔Example〕

Hereinafter, the present invention will be described with reference to FIGS. 4 to 21.

4 (a), (b) and (c) show sample data and sample line data, and FIG. 4 (a) shows the basics of sample line data and sample line data handled in the method of the present invention. Fig. (B) shows the relationship between the amount of positional deviation of both data and the number of defects, and Fig. (C) shows the sample line data in a special part such as the pattern edge of the printed matter. It shows the relationship with the sample row data.

First, referring to FIG. 1A, a plurality of sample row data 10 to 16 are referred to for one sample row data 9. These sample row data 10 to 16 are obtained by shifting the basic sample row data 13 to the left and right by one pixel by the amount of positional deviation expected from the accuracy of the transport system.

Then, the sample row data 9 can be compared with the sample row data 10 to 16 whose phase is closest to that of the sample row data 9 and the density of the sample row data 9 to detect the defect.

As a result, even if the sample row data 9 is displaced in the width direction of the printed matter, the data can be compared in terms of content, so that the defect can be detected with high accuracy. The method of selecting the one having the phase closest to the sample row data from the plurality of sample row data is as follows.

As shown in FIG. 4 (b), when defect detection is performed for one scan period of the camera for each of a plurality of sample row data, the number of defects in the sample row data that is closest in phase to the sample row data is higher than that in the other cases. Becomes the minimum. That is, for each scan, the sample row data with the minimum number of defects has the closest phase to the sample row data at that time. However, this illustrated example relates to a relatively light image, and an image having a high degree of shading produces a characteristic curve having a large inclination.

Next, according to FIG. 3C, the sample row data 17 is compared with the sample row data 18 having the closest phase, and the gradation difference allowable value is increased. As a result, it is possible to perform a defect inspection suitable for a case where the difference in gradation is extremely large like the edge portion of the pattern. That is, the sample row data 18 is the sample row data 17
The phase difference between the two is 1/2
It is the pixel width. Therefore, the gradation difference between the sample and the sample at the pixel corresponding to the edge when the shift of the half pixel width occurs may be set as the allowable value for the pixel. Various methods can be used for setting the permissible value for each pixel (see Japanese Patent Laid-Open No. 56-179599), or a pixel corresponding to an edge may be masked to be excluded from the determination target.

FIG. 5 shows an apparatus configuration for carrying out the method of the present invention constructed based on the idea of FIG.

In this device, a transport cylinder 3 that transports the printed matter 1
Is detected by the rotary encoder 4 and input to the synchronizing circuit 21. This synchronization circuit 21 has a camera 2
Similarly, the scanning position detection signal is input to detect an arbitrary position on the printed material 1. Based on the output of the synchronizing circuit 21, the A / D converter 22 converts the analog amount input from the camera 2 into a digital amount. Here, the address correction circuit 24 is a circuit that addresses the printed matter 1 based on the information of the synchronization circuit 21. An important function of this circuit is to correct the next row to the optimum address by feeding back the output result of the judgment circuit 23 regarding the sample row pattern having the closest phase to the sample row pattern. Then, the digital amount is detected.
Then, the sample row data is compared with the plurality of shift row data generated from the sample pixel data memory 25 in real time in the determination circuit 23 from the next screen. On the other hand, the data of the decision level data memory 26 and the sample pixel data memory 25 preset by the decision level setting circuit 27
The determination level is obtained in real time from this data and is output to the determination circuit 23.

In the figure, the signal indicated by the broken line given from the address correction circuit 24 to the determination circuit 23 is used when the sample pixel data from the camera 2 is corrected to the optimum address. In this case, the determination circuit 23 needs to have a shift register or the like so that the sample pixel data can be shifted by one pixel.

FIG. 6 shows a more specific configuration of the judgment circuit 23 in the apparatus of FIG. 5 by taking a shift amount of ± 3 pixels and one row of 512 pixels as an example. Sample row data SD and judgment level data MD are set to 1 Latches L _{1 to} L ₃ for shifting pixel by pixel
And the shift circuits by the latches L _{4 to} L ₆ for shifting the sample row data TD by one pixel, respectively, as the determination elements JE _{1 to} JE ₃ and JE _{4 to} JE.
_This is combined with the judgment element group according to No. ₇ .

Each of the shift circuits performs the shift operation by supplying the clock CLK used for scanning the camera 2 (FIG. 1) to the latch circuit, and the clock CLK may be supplied for each pixel.

For example, the sample row data TD1 is sequentially shifted by the latches L ₄ , L ₅ , and L ₆ in synchronization with the scanning of the camera TD2, T.
It becomes D3 and TD4. Similarly, the sample row data SD1 and the judgment level data MD1 are sequentially shifted in synchronization with the scanning of the camera by the latches L ₁ , L ₂ , and L ₃ , MD ₂ , MD.
₃ , MD ₄ and SD ₂ , SD ₃ , SD ₄ .

Then, the sample row data TD1 is the judgment elements JE ₁ , J
It is given to E ₂ , JE ₃ , and JE ₄ and is compared and judged with the sample row data and the judgment level data. That is, in the judgment element JE ₄ , the sample row data TD1 and the sample row data S
D ₁ performs the determination based on the determination level data MD ₁ , and the determination element JE ₁ determines based on TD ₁ and SD ₂ and MD ₂ , similarly JE ₂ determines based on TD ₁ and SD ₃ , MD ₃ , and JE ₃ determines TD ₁ . The determination based on SD ₄ and MD ₄ is performed. As a result, the determination is performed when the sample row data and the determination level data are delayed from the sample row data.

On the other hand, on the contrary, the judgment when the sample row data is delayed from the sample row data and the pixel control data is made by the judgment elements JE ₅ , JE ₆ , and JE ₇ . As a result, each of the determination elements JE _{1 to} JE ₇ causes the fourth
The comparison determination of the sample row data 9 and the sample row data 10 to 16 in FIG. Each judgment element J at this time
The output of E _{1 to} JE ₇ is the number of defects detected during one camera scan.

The outputs from these seven decision elements are the total decision circuit T
Given to JU. The comprehensive judgment circuit TJU selects a minimum value from the number of defects output from each element, and judges whether the value exceeds a threshold value or not. That is, the comparison determination is performed with the sample row data and the sample row data that has the best phase. In addition, the judgment element that gives this minimum number of defects is the total judgment circuit TJU.
By discriminating on the basis of the calculation result of, the number of pixels of the sample row data currently inspected is deviated from the sample row data. This identification data is transferred from the output terminal ST to the address correction circuit 24, and the leading address for the next scan of the camera 1 is corrected.

FIG. 7 shows a more specific structure of the judgment element JE used in the judgment circuit of FIG. This is a difference absolute value detection circuit DA, a comparator CP, a counter C.
It is composed of T and latch LA. Then, the absolute value circuit DA of the difference is used for each sample row data TD (TD _{1 to} T
The absolute value | TD-SD | of the difference between D ₄ ) and each sample row data SD (SD _{1 to} SD ₄ ) is determined. This value and each judgment level MD (MD ₁ to
MD ₄ is compared with the comparator CP, and pixels having a judgment level or higher are output to the counter CT as defect signals.
The counter CT is initialized each time the scanning start signal SZERO generated at the start of one scan of the camera is input, and can be counted only while the defect signal is output. The clock CLK of the counter CT is a clock used for timing generation of the inspection apparatus according to the present invention, and one clock corresponds to one pixel in image scanning by the camera. That is, the counter CT counts the number of defective pixels generated in one scanning period of the camera. The latch LA outputs the number of defects generated during the one scanning period as an FN (FN ₁ to FN ₇ ) signal to the comprehensive determination circuit TJU in response to the scanning end signal SEND generated each time the camera completes one scanning.

FIG. 8 shows a more specific structure of the absolute value circuit of the difference in the decision element of FIG.
It is composed of D ₁ and AD ₂ , an exclusive OR circuit EX and an inverter INV, and has TD as an input, ▲ ▼
Is given to form an output of | TD−SD |.
Since this circuit is well known, its detailed description is omitted.

FIG. 9 shows the configuration of the overall decision circuit TJU in the decision circuit of FIG. 6 in more detail. It is composed of six low value detection circuits MIN _{1 to} MIN ₆ , a comparator CP, and a decision element identification circuit JA. ing.

Judgment elements JE _{1 to} JE ₇ (FIGS. 6, 7, and 8)
A defective number of articles FN ₁ is lower-value detecting circuit for detecting the minimum one among ~FN ₇ MIN1~MIN6 from Figure), the detected minimum value, and the defect allowable number have been given in advance comparator If the number of scan lines is compared by CP and the number of scan lines exceeds the allowable number, a detection signal is output to the output terminal OUTPUT as a defective line. The allowable number of defects given here is a value for preventing erroneous determination due to noise or the like added with a value in a range acceptable as the quality of the printed matter.

Further, this comprehensive judgment circuit TJU has a judgment element discrimination circuit JA for detecting which sample row data is closest in phase with each sample row data group shifted by ± 3 pixels (minimum number of defects). It is provided. The output ST of this gives information on how many pixels the positional deviation amount when the camera is scanning is different from when the sample row data was taken into the inspection device.

FIG. 10 shows a more specific structure of the low value detection circuit MIN in FIG. 9, which includes a selector SE and a comparator C.
And P. The two inputs A and B are compared by the comparator CP, and a signal of A> B is obtained. One of them is a signal for determining element identification signal J, which goes to JA, and the other is a signal for selecting a low value from inputs A and B by selector SE. The output of this circuit is the signal MIN (A, B) that has detected a low value from the two inputs A, B.

Here, the comprehensive judgment circuit in FIG. 9 detects two low values by combining two of the seven inputs, compares the low value detection results with each other to detect the low value, and further performs the low value detection. Is used to detect the lowest value among the 7 inputs.

FIG. 11 shows the judgment element identifying circuit JA in FIG.
It shows the operation contents of. In FIG. 11, “1” in the chart is a state where the output J of the low value detection circuit satisfies A> B, “φ” is a state where A <B is satisfied,
"X" is a state in which either of them is acceptable. J1
It is possible to identify which of the outputs FN1 to FN7 from the seven decision elements JE is the smallest when each of J6 satisfies the chart-like condition.

FIG. 12 shows the judgment element identification circuit JA in FIG.
It shows a more specific configuration of the inverter INV ₁ ~
This is an example of a circuit in which the logic is constituted by INV ₆ , OR circuits OR _{1 to} OR ₆ , and encoder EN.

The applicant has already applied for the determination level setting method (Japanese Patent Application No.
6-179599) is further advanced, and it can be used for the determination result of the determination circuit in real time, and is more difficult to make an erroneous determination.

Here, three types of determination levels are adopted. The first is called "fixed portion", which is the minimum value for the shadow area (low density area) of the printed pattern, or the maximum value for the area that does not require inspection (margin area) (255 at 8 bits). give. This is written in the decision level data memory 26 in advance. The second is what is called "proportional amount", which is the ratio K in the sample pixel data 25.
It is a value obtained by multiplying (K <1), and improvement of inspection performance can be expected by this.

The third is called "edge", and by giving the difference between adjacent pixels of the sample pixel data memory 25 as a judgment level, it is useful for preventing malfunction in the portion where the density changes abruptly. The second and third judgment levels are calculated in real time from the sample pixel data memory 25.

When a judgment level of a certain pixel is given, the maximum value is selected from the three kinds of judgment levels and used.
This makes it possible to configure an inspection device that is unlikely to be erroneously determined. That is, when the inter-pixel level difference in the sample pixel data SD is small, the first determination level is used, and when the inter-pixel level difference is slightly large due to the gradation change, the second determination level is used, and the pixel at the edge portion is used. If the inter-level difference is extremely large, the third judgment level is used. Such a measure prevents erroneous determination.

FIG. 13 shows a concrete configuration example of the decision level setting circuit 27 shown in FIG.

One of the sample pixel data SD is shifted using the latches LA3 and LA4, an inverter INV, and absolute difference circuits DA2 and DA3.
At, the difference between adjacent pixels is obtained. High value detection circuit
In HL1, the larger of the differences between the left and right adjacent pixels is sent to the B input of the high value detection circuit HL2 as the "edge" determination level. In this way, by comparing with the pixels on both the left and right sides, it is possible to deal with the position difference in the width direction on either the left or right side with one determination level. Sample pixel data SD
The other one is a coefficient K (K
It is multiplied by <1) and sent to the C input of the high price detection circuit HL2 as a “proportional” determination level.

The reason why the sample pixel data SD is used as the output of the latch LA4 is to match the "edge" determination level with the phase of the pixel. For the same purpose, when quoting the "fixed" judgment level from the judgment level data CD, the latches LA1 and LA2
It is used as the input A of the high-value detection circuit HL2 for phase matching. The high-value detection circuit HL2 selects the maximum judgment level from the inputs A, B, and C, that is, the optimum judgment level obtained from the level difference between pixels in the corresponding area of the sample pixel data SD, and uses that value as the judgment level for that pixel. It is sent to the judgment circuit 27 as MD.

This series of operation is the timing clock CLK of the inspection device.
Since it is performed in synchronism with the above, it is possible to give a judgment level in real time to the judgment circuit 23 that compares the sample row data with the sample row data for each pixel.

Here, the absolute value circuits DA2 and DA3 of the difference have the same configuration as in FIG. 8, and the high value detection circuits HL1 and HL2 can be realized by the function reverse to that of the low value priority circuit MIN shown in FIG. Therefore, the circuit diagram is omitted.

FIG. 14 shows a specific example of the proportional component setting circuit RS of FIG. In the present embodiment, for simplicity, the gates G1 to G4 are selected by the decoder DE without using a multiplier or the like so that a specific determination level can be obtained. The proportional set value is set to 2 bits. Gate G
When the gate G1 is selected, the sample pixel data SD is connected to the input of 1 by connecting the highest bit to LOW and connecting the lower 7 bits to the upper 7 bits of the sample pixel data SD (the remaining 1 bit is not connected). The value of 50% of is output. Similarly, by selecting G2 to G3 respectively,
The input system is connected so that the values of 25%, 12.5%, and 6.25% of S2 are output.

When considering a conveyance system for the printed matter 1 such as a reversing inspection device for a printing machine, as shown in the fifteenth, a considerable lateral displacement occurs depending on the traveling accuracy of the conveyance system. Further, in the printing process, the flow of the web supplied from the paper feeding unit may shift in the width direction in some cases, so that the printing cylinder is often moved in the width direction in the printing step. At this time, of course,
The sample row data will move greatly in the width direction. Therefore, for a long period of time such as between the scanning positions a and c, it is expected that a considerable amount of lateral displacement will occur.
On the other hand, in the extremely short period between a and b, which corresponds to one scanning period of the camera, there is almost no positional deviation in the width direction (a margin of about 1 to 2 pixels is sufficient). Then, although it is necessary to take measures against the positional deviation in the width direction for a long period of time, preparing a large number of sample row data for this purpose results in a very heavy load on the hardware.

Therefore, in the present invention, a small number of sample row data (± 3 pixels in this embodiment) is used for a short-term shift (a shift in position between a and b), and a long-term shift (a, (positional deviation occurring between c), the hardware load is greatly reduced by correcting the scanning start address to the address with the smallest positional deviation before each scanning of the camera.

FIG. 16 shows at what timing the address correction is performed before the camera scanning. This correction operation is performed with reference to the start and end points of camera scanning. For example, the rotation direction of the cylinder 3 is divided based on the signal from the rotary encoder 4 and the camera scanning start points are summarized as N.
1 and N2, and the corresponding end points are ED ₁ and ED ₂ . For each scanning start point N1, N2 of the camera, start signal SZERO occurs, end signal SEND is generated for each scanning end point ED _1, E _2.

From this scan end point SEND to the scan start point SZERO,
The camera stores the amount of light, and the inspection device itself does not perform any arithmetic operation. During this period, the next camera scanning start address is corrected based on the ST signal (which gives the address of the sample row data that is closest in phase to the sample row data) obtained from the determination circuit 23 to correct the positional deviation in real time. Is possible.

FIG. 17 explains the definition of the position shift amount of the ST signal output from the judgment circuit 23. G1 represents the pixel position when the sample row data is taken in, and G2 and G3 represent the phase of the sample row data. Are data obtained by shifting the sample row data G1 in order to match with each other, G2 is defined as a direction shift, and G3 is defined as a direction shift. That is, in the present embodiment, by decoding the ST signal having the information of 3 bits, it is possible to know to which one of the ± 3 pixels the sample row data currently fetched is located closest to the sample row data. . The table below summarizes this.

FIG. 18 shows a specific circuit configuration example of the address correction circuit 24. This circuit has three types of counters C1 to C3 and a latch.
It is composed of LA5, an inverter INV, an AND circuit AND, and an OR circuit OR. Here, the SCLK signal is a signal output from the camera, and the information of one pixel is taken into the inspection device in synchronization with these one clock. Then, a CLK signal is generated from this signal in the inspection device in order to control the internal timing. Since the SCLK signal is generated by the camera, it is also generated when the address is not generated, that is, between the SEND signal and the SZERO signal.
Since the LK signal is a signal created in the inspection device, this signal
There is no output for the period between SZERO and SEND. Therefore, the clock that can be used as the address correction timing signal is SC.
It becomes the LK signal.

FIG. 19 shows the timing of generation of various clocks φ _{1 to} φ ₇ , and address correction is accurately performed between the SEND signal and the SZERO signal.

Each of the counters C1 to C3 has a preset function and
When the ad pin is LOW, preset data is output. C1 presets the ST signal from the decision circuit 23
As data, the number of misaligned pixels is counted. C2 is
This is an up-down counter, and the address at the scan end point one scan before is used as the preset data, and the SCLK signal counted up or down by the number of pixels counted by C1 is used as the current sample line data. Is output to the preset data of the internal address generating counter C3 as the address having the closest phase. C3 is C
Based on the preset data from 2, an internal address is generated in which the scanning start address of the camera is optimally corrected. Here, the internal address is treated as 16 bits. This output is used as an address for writing and reading data in the memory.

Next, the clocks φ ₁ to φ ₇ generated at the timing shown in FIG.
Each function is explained.

The ST signal is output from the determination circuit 23 in synchronization with the SEND signal. Take this data into latch LA5 at clock φ ₂ with enough time to settle. The highest bit of the output of the latch LA5 is input to the up-down counter C2 as data indicating the shift direction of the sample row data. In C2, after the up state and the down state are determined, the preset data (scan end address of one scan before) is output at clock φ ₃ . However, counting is not performed while clock φ ₁ is low (preset mode). On the other hand, Latch LA5
The lower 2 bit outputs of the above are input to the position shift pixel number detection counter C ₁ as preset data through the inverter INV. Here, how many pixels the sample row data deviates from the sample row data is counted and a φ ₇ signal is generated.
A φ ₄ signal is generated based on this φ ₇ signal, and the SCLK signal is passed to the clock input of the up-down counter C7 by the number of pixels having a positional shift. As a result, the counter C2
, The internal address is shifted according to the amount of positional deviation, and the scanning start address is corrected to the position where the phase is closest to the current camera scanning. Clocks φ ₅ and φ ₆ indicate timing clocks for replacing the corrected address with the internal address.

FIG. 20 is based on the timing chart of FIG.
This is an embodiment for actually generating the clocks φ _{1 to} φ ₆ . This clock generation circuit is a D-type flip-flop DF
_{1 to} DF ₅ , counters C4 and C5, and an inverter INV.

The flip-flop DF ₁ outputs the clocks φ ₂ and φ ₃ by setting the counters C4 and C5 in the count mode between the SEND signal and the SZERO signal. Clock φ
_The clock φ ₁ is obtained by using 3 as the input of the flip-flops DF2 and DF3. φ ₁ is obtained by inverting φ ₃ with the inverter INV. Further, by using a phi ₇ output of the counter C1 as an input flip-flop DF _4, DF _5, to obtain clock phi _5, the phi _6.

With the above configuration, even if the design of the printing unit is misaligned to some extent, the quality of the design can be accurately determined, high-speed inspection is possible, and the cost of the apparatus can be reduced. Also, in order to compare the sample row data with the sample row data,
It is possible to perform inspection with extremely high accuracy as compared with the case where the patterns are compared with each other as a whole.

Further, the displacement of the printed matter in the traveling direction can be dealt with by the circuit of FIG. 21 which is a partial modification of the determination circuit shown in FIG. This determination element JC ₁ ~JC _7, the shift register _SR 1 to SR ₆ and is by connexion configured total determination circuit TJU. The shift register SR is the camera 2
(Figure 1) is a number of bits equal to the number of sensor Areibitsuto sample row data SD, the decision level MD and the sample row data TD as the latch in FIG. 6, is delayed by one pixel, determining elements JC ₁ ~ given to J _7, each output j ₁ to j ₇ of these determination elements JC ₁ ~JC ₇ is given to the overall decision circuit TJU, the minimum value is detected.

[Effect]

As described above, the present invention compares the sample row data with the sample row data stored in advance in the memory for each row.
One of these two data is compared with the other data one by one as a plurality of data shifted by an appropriate number of pixels from the other, and the amount of positional deviation between the two data when the level difference is smallest among them is detected. Since the address of one of the data is corrected according to the amount of positional deviation, the minimum hardware for coping with the positional deviation of the printed matter expected in the printing machine feeding system can be realized. And while the hardware is simple, highly accurate inspection can be performed in real time.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an image information detection unit of a pattern inspection device which is an object of the present invention, and FIG. 2 is a model explanatory view of a sample pixel data and a recording system of sample pixel data for a pattern inspection,
FIG. 3 is a characteristic diagram for explanation in the case where a displacement of a picture pattern due to a printed material conveying system or the like occurs, and FIGS. 4 (a), (b) and (c) show a basic inspection method of the method of the present invention. FIG. 5 is a characteristic diagram showing a method for inspecting a pattern edge, FIG. 5 is a block diagram showing a device configuration for carrying out the method of the present invention, and FIG. 6 is a block diagram showing a more specific configuration of a judgment circuit in the device shown in FIG. FIG. 7 is a block diagram showing a more specific structure of the judgment element in the judgment circuit of FIG. 6, and FIG. 8 is a more specific structure of the absolute difference value detection circuit in the judgment element of FIG. Block diagram shown in FIG. 9, FIG. 9 is a block diagram showing a more specific structure of the comprehensive determination circuit in the determination circuit of FIG. 6, and FIG. 10 is a more specific example of the low value detection circuit in the comprehensive determination circuit of FIG. Block diagram showing the structure, Fig. 11 is the ninth
FIG. 12 is an operation explanatory diagram of the judgment element identification circuit in the comprehensive judgment circuit in the figure, FIG. 12 is a connection diagram showing a more specific configuration of the judgment element identification circuit, and FIG. 13 is a diagram showing the judgment level setting circuit in the apparatus of FIG. A block diagram showing a specific configuration, FIG. 14 is a block diagram showing a more specific configuration of the proportional component setting circuit in the determination level setting circuit of FIG. 13, FIG.
The figure is an explanatory view of the positional deviation in the width direction of the printed matter in the printed matter conveying system, FIG. 16 is an explanatory view of the image signal address correction operation of the camera in the apparatus of FIG. 5, and FIG. 17 is the sample pixel data in the apparatus of FIG. FIG. 18 is a block diagram for explaining the shift operation at the time of reading, FIG. 18 is a block diagram showing a more specific structure of the address correction circuit 24 in the apparatus of FIG. 5, and FIG. 19 is the timing of signals at various parts of the circuit of FIG. FIG. 20 is a diagram showing a circuit for generating a clock used in the circuit of FIG. 18, and FIG. 21 is a block diagram showing another example of the decision circuit in the device of FIG. 1 ... Printed matter, 2 ... Camera, 3 ... Cylinder, 4 ...
Rotary encoder, 5,7,9,17 ... Sample pattern (sample line) data, 6,8,10,18 ... Sample pattern (sample line) data. TD ... Sample line data, SD ... Sample line data, MD ...
... Pixel control data, JC ... Judgment circuit, JE ... Judgment element, L ... Latch, SR ... Shift register, T
JU: Comprehensive judgment circuit.

Claims (3)

[Claims] 1. A method of inspecting a printed matter for judging whether the printed matter is good or bad by comparing the pattern data taken out from the sample printed matter with the pattern data stored in a memory preliminarily taken out from the sample printed matter. In step 1, one of the sample row data detected for each row from the sample and the sample row data stored in the memory is displaced relative to the other by one pixel unit to form a plurality of data. , The number of defective pixels for each row data is obtained by performing a level comparison for each pixel of the sample row data and the sample row data using the plurality of data, and the number of defective rows for both rows when the number of defective pixels becomes the minimum value The amount of positional deviation between these two data is calculated from the positional relationship of the data, and one of the addresses of the amount data is corrected based on this amount of positional deviation. A method for inspecting a pattern on a printed matter. 2. A pattern inspecting method for a printed matter, comprising: comparing the pattern data taken out from the sample row data with the pattern data previously taken out from the sample printed matter and stored in the memory to judge the quality of the printed pattern. Either one of the sample row data detected for each row and the sample row data stored in the memory is displaced by one pixel unit relative to the other to form a plurality of data, and the plurality of data are used. Then, the pixel row data and the sample row data are compared in level for each pixel, and the obtained level difference is given as a fixed value, the sample row data is multiplied by a predetermined coefficient, the concentration abrupt change portion. The number of defective pixels of the pattern is obtained according to the relationship with one judgment level selected from among the density differences in 1. The printed matter characterized in that the positional deviation amount between the two data is calculated from the positional relationship between the two data, and the address is corrected to one of the two data based on the positional deviation amount. Pattern inspection method. 3. A device for forming a synchronizing signal in accordance with a conveying operation of a printed matter, a camera for scanning a pattern of the printed matter based on the synchronizing signal to take out image information, and an image information taken out from a sample printed matter by the camera. The sample pixel data memory to which is written and one of a plurality of preset determination levels are selected, and the image information for each pixel read from the sample pixel data memory is selected according to the selected determination level. A judgment level setting circuit that performs setting and outputs, and a judgment circuit that compares the image information from the judgment level setting circuit with the image information of the sample printed matter from the camera, and judges an image defect for each pixel, The read address signal of the sample pixel data memory is formed based on the output of the synchronization circuit, and the address is output based on the output of the determination circuit. Print pattern inspection apparatus having an address correction circuit that performs address correction for less signal.