JPH06259540A - Picture reducing device - Google Patents

Abstract

(57) [Abstract] [Purpose] To speed up the image reduction processing speed of the image reduction apparatus by reducing the processing load on the CPU. The CPU 1 sets parameters necessary for obtaining desired reduced image data in the address conversion circuit 31, the latch circuit 32, and the selector circuit 33 via the control line 6.
The CPU outputs the address for the image data reduced to the desired reduction ratio. The address conversion circuit converts the address to the image data actually stored in the image memory, and sequentially outputs the addresses from the converted address the number of times corresponding to the reduction rate of the image data. The read image data is temporarily stored in the latch circuit, and the selector circuit extracts the reduced image data thinned out at a desired reduction rate from the latch circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reducing device for reducing two-dimensional image information.

[0002]

2. Description of the Related Art Generally, when two-dimensional image data stored in an image memory is reduced, an arithmetic process for obtaining a vertical address of image data is required for vertical reduction, and Regarding the direction, in addition to the address calculation processing, calculation processing for each pixel with respect to the read image data is necessary. Further, the calculation processing for each pixel is generally performed by extracting image data pixel by pixel using a parallel-serial conversion circuit or the like.

FIG. 4 shows an example of an image reducing apparatus which adopts a conventionally known image reducing method of this type. The image reducing apparatus of this example shown in FIG. 4 selects a CPU (Central Processing Unit) 11 for processing image data, an image memory 12 for storing image data, and a target portion of the image data. And a data bus 15 for reading out image data. Further, as a data display device, a parallel-serial device for obtaining pixel data from the data bus 15 and taking out pixel by pixel. It includes a conversion circuit 131, a counter circuit 132 that selects and outputs the extracted pixel data of each pixel for each appropriate pixel, a display control circuit 17 and a display 18 for displaying a reduced image.

The CPU 11 is configured to process data in units of 8 pixels as one unit (hereinafter referred to as 1 byte). On the other hand, the image memory 12 has a memory configuration and address arrangement as shown in FIG. 5, and the two-dimensional image data for one image is stored in the image memory 12 for one address output from the CPU 11. It is stored so as to be output for each byte. That is, the image data handled in this example has a size of horizontal x pixels and vertical y pixels, and an address for selecting 1 byte indicating the beginning (upper left) of the image is address 0 and indicates the next 1 byte. The address is arranged in the image memory such that the address is 1 address, the address indicating one pixel below is x / 8 address, and the address of the data indicating the upper right corner of the image is x / 8-1 address.

Hereinafter, the operation of the image reducing apparatus according to the conventional example will be described with reference to FIG. 8 in which the two-dimensional image data stored in the image memory 12 is reduced by the thinning rate and the thinning method shown in FIGS. 6 and 7. Follow the instructions below. In the thinning rate and the thinning method of the image data in this example, as shown in FIG. 6 in the horizontal direction, the number of pixels in the horizontal direction is reduced to 1/3 by thinning out two pixels every three pixels.
As for the vertical direction, as shown in Fig. 7, 3 for every 4 lines
By thinning out lines, the number of pixels in the vertical direction is reduced to 1/4. Therefore, in this example, the size of the reduced image is horizontal x / 3 pixels and vertical y / 4 pixels.

First, at step s1 in FIG.
U11 prepares and initializes variables x1 and y1 for two-dimensional coordinates indicating one byte of pixel data with the upper left corner of the image as the origin. Here, it is assumed that x1 = 0 and y1 = 0 assuming that the reduction processing is executed from the upper left of the image. Further, in step s2, the CPU 11 obtains the address for the image data as shown in FIG. 4 from the coordinates x1, y1. Since the horizontal size of the image is x / 8 bytes, the address a1 is a1 = x1 + y1 + (x / 8). The address a1 is output to the address bus 14. Step s
In 3, the image memory 12 outputs 1-byte pixel data to the data bus 15 according to the address a1. In step s4, the CPU 11 actually performs the reduction processing in the horizontal direction using the pixel data obtained. Since it is reduced to 1/3 in the horizontal direction, 1 byte (8
Pixels), the first, fourth, and seventh pixels are sequentially selected to be the first three pixels. In step s5, the coordinate x1 is updated to the right to access the next pixel data (x
1 = x1 + 1), and the address a1 is obtained. There is also a method of increasing a1 by one address here, but as will be described later, the coordinate x1 is required to determine the end of processing for one line. This a1
Is output to the address bus 14 similarly to s3. In step s6, the image memory 12 outputs pixel data. Next, in step s7, thinning is performed in the same manner as s4, but the pixels to be selected are the second, fifth, and eighth pixels as shown in FIG. This is 6 pixels including the previous 3 pixels. Further, in step s8, x1 and a1 are obtained, and the address a1 is output. In step s9, the image memory 12 outputs pixel data. Similarly, in step s10, the third and sixth
The th pixel can be selected and the pixel data of the reduced image for 1 byte can be obtained here by combining with the previous pixel. Next, in step s11, it is determined whether the coordinate x1 indicates the right edge of the image. If it is not the right edge, x is determined in step s12.
1 is updated, and the process returns to step s2. If it is at the right end, it is determined in step s13 whether y1 indicates the last line of the image. When the end is indicated, the reduction processing for one image is completed as described above. If y1 is not the last line, then in step s14 y1 indicating the next line is obtained. That is, since it is reduced to 1/4 in the vertical direction as shown in FIG. 7, y1 = y1 + 4 is set in order to select one line every four lines. Further x
1 is initialized (x1 = 0), the process returns to step s2 and the above is repeated. With the above steps, one image data can be reduced to horizontal 1/3 and vertical 1/4.

Next, the display 18 in the conventional device
An example of a method of displaying the reduced image on the screen will be described. Similarly, the reduction ratio of the reduced image to be displayed is also 1/3 in the horizontal direction and 1/4 in the vertical direction. In order to reduce the size to 1/4 in the vertical direction as shown in FIG. 7, the CPU 11 first selects one line out of every four lines, and obtains the address of the first 1-byte pixel. The CPU 11 continuously outputs addresses for one line from this address to the address bus 14. The image memory 12 outputs the pixel data for one line corresponding to this address to the data bus 15. The parallel-serial conversion circuit 131 obtains 1 byte at a time from the data bus 15, takes out 1 pixel at a time from the beginning of the data for 8 pixels, and sends it to the counter circuit 132. The counter circuit 132 repeats a cyclic operation such that the first one pixel of the obtained data for each pixel is selected and sent to the display control circuit 17, and the next two pixels are ignored. By the operation of the counter circuit 132, the horizontal direction is reduced to 1/3, and the display control circuit 17 displays the reduced image data for each pixel obtained on the display 18.

[0008]

As described above, in the conventional image reducing apparatus, steps s3, s6, and s6 are performed in the series of operations for obtaining the reduced image data shown in FIG.
Except for s9 and s9, all must be executed by the arithmetic processing of the CPU 11, so that the processing load on the CPU is heavy and it is difficult to perform the reduction processing at high speed. In particular, in the case of this example, since there are many units of processing (one pixel at a time) smaller than 1 byte, a large processing load is imposed on the CPU 11. In addition, the reduced image data is displayed on the display 18.
Even when the image is displayed on the screen, the CPU 11 has to reduce the image data in the vertical direction to select an appropriate line and obtain an address, which further increases the processing load on the CPU. Further, these arithmetic processes are generally controlled by software, but the software becomes very complicated, which makes it difficult to develop the software. further,
As in steps s4, s7, and s10 in FIG. 8, since the pixels to be thinned out differ depending on the address of the pixel data, the reduction processing cannot be executed from a random address, and therefore it is difficult to arbitrarily obtain only a part of the reduced image. .
Therefore, in order to eliminate such inconvenience, the CPU
It is indispensable to develop a system configuration that can reduce the processing load.

The present invention has been made in order to solve the above technical problems, and has a high image reduction processing speed, easy development of control software, and data of a target portion of reduced image data. It is an object of the present invention to provide an image reducing device capable of randomly obtaining the image.

[0010]

In order to achieve the above-mentioned object, the present invention provides an image reducing device which comprises a plurality of consecutive two-dimensional image data, each of which is made up of two-dimensional image data having an arbitrary number of pixels in the vertical and horizontal directions. The image memory that stores the minute as one unit, the CPU that performs the selection, reading, and arithmetic processing of the image data, and the image data that has been reduced to the target reduction ratio output from the CPU Under the control of the CPU, the address is converted into an address for the image data actually stored in the image memory, and the converted address is successively output the number of times corresponding to the reduction rate of the image data. Address conversion circuit, a latch circuit for temporarily storing image data selected by an address from the address conversion circuit, and the latch circuit A selector circuit for extracting data thinned out at a thinning rate according to the target reduction rate from the image data stored in the address conversion circuit, the latch circuit, and the selector circuit.
U includes a control line for setting parameters.

Of course, in order to display the image data reduced by the image reduction device, an arbitrary portion of the image data is selected in the address bus connecting the CPU and the address conversion circuit to the device having the above-mentioned configuration. It is also possible to add a parallel-serial conversion circuit that can output an address for performing the conversion and that converts the data output from the selector circuit into data for each pixel, an image display control device, a display, and the like.

[0012]

According to the above-mentioned means, the CP is previously set through the control line.
U sets the parameters necessary for obtaining desired reduced image data in the address conversion circuit, the latch circuit, and the selector circuit, and outputs the address for the image data reduced to the target reduction rate from the CPU. ,
The desired reduced image data can be taken out from the selector circuit without the CPU performing the address arithmetic processing for accessing the image data and the arithmetic processing for the obtained data. Therefore, reduced image data of the image data in the image memory can be obtained at high speed, and
Since the parameters given to the address conversion circuit, the latch circuit, and the selector circuit can be arbitrarily changed, an arbitrary portion of the image data in the image memory can be randomly obtained. Moreover, since the software for controlling the CPU can be simplified, the software can be easily developed. Furthermore, if parameters are set in the address conversion circuit, the latch circuit, and the selector circuit,
Since the reduced image data can be displayed on the display or the like, even if a display or the like is additionally provided in the image reducing apparatus of the present invention, the processing load of the CPU does not increase, and the reduced image data of the image data in the image memory can be displayed. , Can be displayed on the display etc. at high speed.

[0013]

FIG. 1 shows an example of an image reducing apparatus according to the present invention. The image reducing apparatus of the present embodiment shown in FIG. 1 includes a CPU 1 for selecting, reading, and calculating image data, an image memory 2 for storing image data, and data of a target portion in the image memory. A plurality of address buses 41 for selecting addresses, a plurality of address buses 42 for addresses output by the CPU 1, and an address obtained from the address bus 42 are converted into appropriate addresses under the control of the CPU 1, An address conversion circuit for sequentially outputting addresses to the address bus 1 a proper number of times from the address, and a data bus 51 for 1-byte pixel data output from the image memory.
A data bus 52 for one byte of pixel data input to the CPU 1, a data bus 51 for a plurality of bytes of pixel data obtained from the data bus 51, and C
A latch circuit 32 for temporarily storing 1-byte pixel data input to PU1, and 1-byte pixel data obtained by thinning out the pixel data stored in the latch circuit 32 at an appropriate thinning rate are output to the data bus 52. A selector circuit 33 for outputting, an address conversion circuit 31, a latch circuit 32, and a control line 6 for the CPU 1 to set parameters in the selector circuit 33. Further, in the present example, in order to display the reduced image on the display 8, the parallel-to-serial conversion circuit 34 for extracting the pixel data of each byte obtained from the data bus 52 pixel by pixel and sending the pixel data to the display control circuit 7. And a display control circuit 7 for controlling the display of the obtained pixel data for each pixel.

The CPU 1 is a CPU 11 in the conventional device.
Like the image memory 12 in the conventional apparatus, the image memory 2 has a memory configuration and address arrangement as shown in FIG. The image memory 2 stores one-dimensional two-dimensional image data so as to be output byte by byte for one address.

As in the case of the conventional apparatus, the conventional example will be described below by taking the case where the two-dimensional image data stored in the image memory 2 is reduced by the thinning rate and the thinning method shown in FIGS. 6 and 7. The operation of the image reducing device will be described with reference to FIG. First, in step s1, the CPU 1 sets parameters in the address conversion circuit 31. This parameter is the vertical and horizontal reduction ratio and the number of pixels in the horizontal direction of the image. Similarly, in steps s2 and s3, parameters (horizontal reduction ratio) are set in the latch circuit 32 and the selector circuit 33. Next, in step s4, the address a2 for accessing the image memory 2 is initialized. This address is an address for image data reduced to a desired reduction ratio. That is, this address a2
As shown in FIG. 3, since the number of pixels in the horizontal direction of the image before reduction is x pixels (see FIG. 5), the horizontal direction of the reduced image is in the image memory, and the first (upper left) If the address indicating pixel data for 1 byte is address 0, the next pixel data is address 1, and the address indicating the pixel data on the upper right is (x / 3/8) -1 = (x / 24) -1 address, And so on. This address a2 is output to the address bus 42 in step s5. In step s6, the address conversion circuit 31 converts the address according to the set parameters. The address conversion circuit 31 can be composed of a multiplication / division circuit and a counter circuit. That is, using the address a2 and the set horizontal pixel number x, the horizontal and vertical coordinates of the pixel data indicated by the address a2 for the reduced image are obtained. The coordinates and the vertical and horizontal reduction ratios are used to convert the addresses into the image data actually stored in the image memory 2. Further, using the counter circuit, consecutive addresses from this address are sequentially output to the address bus 41 the number of times (three times in this case) according to the reduction rate. In step s7, the image memory 2 transfers the data for the continuous 3 bytes of addresses to the data bus 51.
Output to. In step s8, the latch circuit 32 sequentially stores the pixel data of 3 bytes, and sends 3 bytes (24 pixels) in parallel to the selector circuit 33. Step s9
Then, the selector circuit 33 outputs this pixel data to 2 for 3 pixels.
Pixels are thinned out to obtain 8 pixels (1 byte) and output to the data bus 52. The CPU 1 obtains the 1-byte data reduced in step s10. Hereinafter, in step s11, it is determined whether or not the processing for one reduced image is completed,
If not, go to step s12 and address a2
Is updated and the steps from step s5 are repeated.

As described above, in the image reducing apparatus of this embodiment, the CPU performs the arithmetic processing of the address output to the address bus and the arithmetic processing of the obtained pixel data.
Since the reduced image data can be obtained without performing step 1, the reduced image can be obtained at an extremely high speed. Further, since software for these arithmetic processes is not required, development of software for controlling the CPU becomes easy.

The above method is a method for obtaining a reduced image of the entire image data stored in the image memory 2.
By appropriately changing the parameters set in the address conversion circuit 31, the latch circuit 32, and the selector circuit 33, the CPU 1 determines that the reduced image data is already stored in the image memory, and determines the address for the reduced image data. Can be used to obtain reduced image data. That is, even when only an arbitrary part of the reduced image data is obtained, it is possible to obtain a reduced image of only a part by accessing using the address for the part. Further, the addresses output to obtain the reduced image do not have to be consecutive, and the reduced image can be obtained randomly.

The process of displaying the reduced image on the display 8 can be performed by the CPU 1 by only appropriately changing the parameters set in the address conversion circuit 31, the latch circuit 32, and the selector circuit 33. That is, as in steps s1, s2 and s3 of FIG.
1, the parameters are set for the latch circuit 32 and the selector circuit 33, and the display controller 7 continuously outputs the addresses for the reduced image to the address bus 42 so that the reduced image is transferred to the data bus 52 byte by byte. Is obtained from the parallel-serial conversion circuit 3
4 picks up pixel by pixel from the 1-byte pixel data, and the display control circuit 7 displays this pixel data on the display 8
, The reduced image data can be displayed on the display 8. Also in this case, the CPU 1 does not need to perform the arithmetic processing of the address for accessing the image data and the processing for the pixel data, so that the reduced image data can be displayed at high speed.

In the above embodiment, the CPU 1 is configured to process data byte by byte, and the image memory 2 has two-dimensional image data for one sheet for one address. However, the gist of the present invention is not limited to this, and has any processing capability or data transfer capability. Of course, a CPU and an image memory can be applied.

[0020]

As described above, according to the present invention,
Address calculation processing to access image data,
Since reduced image data having a desired reduction ratio can be obtained without causing the CPU to perform arithmetic processing on the obtained data,
The processing load on the CPU is reduced, and reduced image data of the image data in the image memory can be obtained at high speed. Also,
Since the parameters for the address conversion circuit, the latch circuit, and the selector circuit can be arbitrarily set,
It is possible to randomly obtain reduced image data of an arbitrary part of the image data in the image memory. Further, the software for controlling the CPU can be simplified, which facilitates the development of the software. Even when a display or the like for displaying the reduced image data is attached, the processing load on the CPU does not increase, so that the reduced image data can be displayed on the display or the like at high speed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an image reducing apparatus according to an embodiment.

FIG. 2 is a flowchart showing an image reducing method using the image reducing apparatus according to the embodiment.

FIG. 3 shows image data reduced to a horizontal 1/3 and a vertical 1/4,
It is explanatory drawing which shows the example of an address arrangement at the time of storing in an image memory.

FIG. 4 is a configuration diagram of an image reduction device according to a conventional example.

FIG. 5 is an explanatory diagram showing an example of an address arrangement of image data in an image memory.

FIG. 6 is an explanatory diagram showing a horizontal thinning method when image data is reduced to 1/3 in the horizontal direction.

FIG. 7 is an explanatory diagram showing a vertical thinning method when image data is reduced to 1/4 in the vertical direction.

FIG. 8 is a flowchart showing an image reduction method using an image reduction device according to a conventional example.

[Explanation of symbols]

 1 CPU 2 image memory 6 control line 7 display control circuit 8 display 31 address conversion circuit 32 latch circuit 33 selector circuit 34 parallel-serial conversion circuit 41 address bus output from address conversion circuit 42 address bus output from CPU 51 image Address bus output from memory 52 Data bus input to CPU

Claims (2)

[Claims] 1. An image memory in which two-dimensional image data, each of which is composed of an arbitrary number of pixels in the vertical and horizontal directions, is stored so that a plurality of consecutive pixels can be accessed as one unit, and selection of the image data, A CPU that performs reading and arithmetic processing, and an address for the image data reduced to a target reduction ratio output from the CPU, according to the control of the CPU, for the image data actually stored in the image memory. An address conversion circuit that converts the address into addresses and sequentially outputs the addresses from the converted addresses the number of times corresponding to the reduction rate of the image data, and temporarily stores the image data selected by the address from the address conversion circuit. Latch circuit and the image data stored in the latch circuit at a thinning rate according to the target reduction rate. A selector circuit for taking out the drawn data, the address conversion circuit, a latch circuit, and an image reduction apparatus, wherein the CPU to the selector circuit is configured to include a control line for setting the parameters. 2. The apparatus according to claim 1, which can output an address for selecting an arbitrary portion of image data to an address bus connecting the CPU and the address conversion circuit, and which is output from the selector circuit. An image reduction device, comprising: a parallel-serial conversion circuit for converting data into data for each pixel, an image display control device, and a display.