JPH0625966B2 - Micro program controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprogram controller, and more particularly to a constant generating means used in a microprogram.

[Conventional technology]

Generally, in a microprogram control device, a microprogram consisting of a series of microinstructions is stored in a control memory 201 as shown in FIG. After being temporarily stored in the micro instruction register, the output of the micro instruction register is decoded by the micro instruction decoder 203 to generate the information (micro order) aaa to zzz designated by the micro operation instruction to generate the register file 204 and the arithmetic logic. It is given to each control point such as the arithmetic unit 205.

A microinstruction for transferring data between the register file 204 and the arithmetic logic unit 205 via the data bus 206 is a microinstruction, and a microinstruction for designating the type of operation in the arithmetic logic unit is an operation micro. The instruction, the micro instruction to be executed next to determine the sequence of the micro program is stored in the control memory 201.
The microinstructions designated for are called branch microinstructions, and the microinstructions for controlling control points that cannot be controlled by these microinstructions are called control microinstructions.

As shown in FIG. 3A as a microinstruction format, transfer, operation, branch and control microinstructions are identified by the state of a specific bit or bit string of one word microinstruction (this bit or bit string is called an identifier ID). There is something to be done. The function of each instruction is other bit string (called a function field FUNC) In this instruction format, the command word length is short, so the capacity of the control memory is small, but the type of control points that can be controlled in one micro instruction cycle Has a drawback that it is unsuitable for high-speed processing because it is limited.

On the other hand, as shown in FIG. 3b, all the information relating to the transfer, operation, branch and control functions is provided in one instruction (the respective fields are transfer field TRN, operation field op, branch field BR and control field CNT. In the instruction format, multiple control points can be controlled in one microinstruction cycle, but since it is rare that all microinstructions require transfer, operation, branch and control functions, it is unnecessary. Since information is often included in microinstructions, the word length of one instruction is long, but there is a drawback in that less information is used effectively.

Generally, as shown in FIG. 3c, one instruction is used as a dedicated field (here, TRN for transfer instruction is assigned).
And the function variable field allows the function of the microinstruction to be changed flexibly, resulting in a microinstruction format with a short word length and multiple control points that can be controlled in one microinstruction cycle. Often selected.

In the transfer microinstruction, the source register resource called a source operand such as a register file or arithmetic logic unit is specified, and the destination register resource called a destination operand is specified. However, not only the register resource but also a constant required in the microprogram may be selected as the source operand resource.

When there are few types of these constants used in a microprogram, a method is used in which the constants are fixed in advance in a constant register and designated as a source operand as a register resource. However, this method has a drawback that flexibility is extremely lacking because the constant once set cannot be changed.

As another method of generating a constant, a field called a constant field is provided as part of the microinstruction, and when the transfer microinstruction specifies a constant as a source operand, it is used to transfer the information in this field as a constant. . If a constant field is dedicated to a specific part of a microinstruction, it will contain useless information if a constant is not specified as the source operand of the transfer instruction, so the operation, branch, or control field will replace the constant field. Can be used as.

Therefore, the number of bits of the constant field is relatively smaller than the basic word length of data processing (16 to 32 bits in the internal bus width) (about 8 bits for the basic word length of 16 to 32).
The range of constants that can be expressed is also limited (0 for 8 bits)
~ 255 range).

Next, an example of a conventional microinstruction format, particularly the configuration of a constant field will be described with reference to the drawings.

FIG. 4 shows an example of a microinstruction format, which is composed of a transfer field 401 and an instruction field 402 for designating operation, branch or control. A transfer field 401 is a field 403 that specifies a source operand (hereinafter SR
It is divided into a C field) and a field 404 (hereinafter DST field) for designating a destination operand. In addition, the command field 402
It is composed of an identifier 405 and a function field 406. Depending on the value of the identifier 405, the meaning of the function field 406 changes to a field for calculation, branching or control.
However, when a constant is selected as the SRC field 403, the identifier 405 and the function field 406 (that is, the instruction field 402) become invalid in the conventional sense and are used as the constant field.

FIG. 5 is a diagram showing a configuration of a micro program control device adopting the micro instruction having the conventional instruction format. Data transfer, particularly a constant transfer operation, in the microprogram controller will be described with reference to the drawings. The microinstruction stored in the control memory 502 designated by the micro address register 501 is stored in the microinstruction register 503. The output of the microinstruction register 503 is connected to the microinstruction decoder 504, and according to the contents of the transfer field and the instruction field (in particular, the output src and id corresponding to the SRC field and the identifier ID), the microorder IMD,
Generates OPR, BR, CNI. Micro Order I
MD indicates that a constant is specified as the source operand in the SRC field 403. micro·
The orders OPR, BR, and CNI respectively indicate that the arithmetic, branch, and control functions have been designated in the identifier 405. However, when a constant is specified as the source operand in the SRC field 403, OP
The respective micro orders of R, BR and CNT do not occur. The output func of the micro instruction register 503 corresponding to the function field 402 is the operation control device 5 respectively.
05, a branch control device 506, and a control device 507, and each control device is a micro-order OPR, B.
When R and CNT become active, the contents of func are interpreted and a subdivided micro-order is generated.
SRC field 403 and DST field 404
The outputs src and dst of the microinstruction register 503 corresponding to the above are connected to the source operand decoder 510 and the destination operand decoder 511 via the source operand bus 523 and the destination operand bus 524, respectively. It The source operand decoder 510 is src
The read select signal RDn for the register file 521 connected to the data bus 520 is generated according to the contents of the above. The data of the register Rn in the register file 521 corresponding to the read selection signal RDn is read to the data bus 520.

Meanwhile, the destination operand decoder 511
Generates a write selection signal WRn for the register file 521 according to the contents of dst. The data on the data bus 520 is written in the register Rn in the register file 521 corresponding to the write selection signal WRn. The source operand decoder 510 and the destination operand decoder 511 have read select signals RDn for the register file 520,
In addition to the write select signal WRn, a read select signal READn and a write select signal WRITEn for other register resources 522 connected to the data bus 520 are generated, and in the same manner between the register resources via the data bus 520. Control the data transfer of. SRC operand
When a constant is specified in the field 403 and the micro-order IMD is generated by the micro-instruction decoder 504, the constant buffer 512 to which the output op of the micro-instruction register 503 corresponding to the instruction field 402 is connected.
Is selected and op is output to the lower side of the data bus 520. At this time, the upper side of the constant buffer 512 has a plurality of 0s.
Is output to the upper side of the data bus 520 and the contents of op are zero-extended.

[Problems to be Solved by the Present Invention]

In the conventional constant transfer, when a constant larger than a value expressible in the instruction field 402 (hereinafter referred to as a long immediate, a constant expressible in the instruction field 402 is called an immediate) is generated, an immediate transfer is performed. A long immediate must be generated by using an operation instruction such as a multi-bit shift or a logical sum, and many micro instructions are required for the long immediate generation.

As an example, the data bus 520 has a width of 32 bits,
When the bit width of the instruction field 402 is 8 bits, the values that can be expressed as immediate are 0 to 255.
It is in the range of (0 to 28-1) and has a long length of 32 bits.
If you want to get an immediate, you need to execute the following micro-instructions.

Transfer the 8-bit immediate to register R ₁ .

Shift the contents of R ₁ to the left by 8 bits.

Transfer the new 8-bit immediate to register R ₂ .

It is stored in the logical sum of R ₁ and R ₂ .

Repeat steps ~ twice.

As described above, it is necessary to execute the micro-instruction of 10 steps and one extra register (R ₂ ) for calculation before obtaining the 32-bit long immediate in the register R ₁ .

[Means for solving problems]

The present invention selects means for temporarily holding a microinstruction, means for detecting a bit pattern of the first field of the holding means, and predetermined data or contents of the second field of the holding means. A plurality of data generating means for selectively outputting the contents of the second field of the holding means to only one of the plurality of data generating means according to the bit pattern detected by the detecting means. And outputting the predetermined data selected by the other plurality of data generating means are connected to independent bit positions and used as constant data.

〔Example〕

Next, the configuration and operation of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, which is an instruction register 10
Input the output src corresponding to the SRC field of 0 and the output id corresponding to the identifier ID to the micro order IM
The microinstruction decoder 102 for generating D, OPR, BR, CNT selects the lower 8 bits func of the instruction field of the microinstruction register 100 when the selection signals SEL0 to SEL3 are active, and otherwise outputs 8 bits of zero data. Means 110-113 for generating, a 32-bit data buffer 114 for connecting the outputs of the four 8-bit data generating means 110-113 to the 32-bit data bus 101 when the read signal IMD is active, byte position information 2 bits for generating selection signals SEL0 to SEL3 according to the contents of BYT0 / 1
It is composed of a decoder 115. Byte position information BYT
If 0/1 is 00, the selection signal SEL0 is 1, if 01, the selection signal SEL1 is 10, and if it is 10, the selection signal SEL2 is 1
If 1, the selection signal SEL3 becomes active. The lower 8 bits imd of the instruction field are output to the outputs of the 8-bit data generating means 110 to 113 selected by the selection signals SEL0 to SEL3, but the 2-bit decoder 11 is used.
5 generates the selection signals SEL0 to SEL3 so as to be exclusively activated, and therefore, the above-mentioned non-selected 8
8-bit zero data is output to the outputs of three sets of the bit data generating means 110 to 113. Therefore, when the read signal IMD becomes active, the contents of the byte position information BYT0 / 1 causes the 32-bit data buffer 114 to move to the 32-bit data bus 10.
The data output to 1 is as shown below.

However, the expression bus. [X..y] here is 32 bits.
Indicates the range from bit x to bit y of data bus 101, where nnnnnnnn is the lower 8 bits of the instruction field func
Indicates the contents of.

FIG. 6a is an example of the instruction format of the microinstruction applied to this embodiment. The instruction format is 6-bit SRC field, 6-bit DST field, 3-bit ID
It consists of a field and an 8-bit FUNC field. When the SRC field is 101010, a constant is designated as the source operand. ID field is 0x
It is specified that the FUNC field has a time branch function of x (x is 0 or 1), a time calculation function of 100, and a time control function of 101, but the SRC field is 101010.
, Ie if a constant is specified to be transferred, at which byte position is to arrange any 8-bit data having a value of 0 to 255 specified by the FUNC field to be configured as 32-bit data? Used to specify. That is, as the least significant 8-bit data if the ID field is X00, as 8-bit data of the next bytes for X01, as 8-bit data following additional bytes for X _10, the X ₁₁ If used, it is used to specify that the most significant byte is used as 8-bit data.

Next, the operation of this embodiment will be described.

Of the outputs of the microinstruction stored in the 23-bit wide microinstruction register 100, the bit src corresponding to the SRC field and the bit i corresponding to the ID field
The d is connected to the microinstruction decoder 102 and generates the microorder IMD, OPR, BR, CNT according to the contents of the transfer field and the instruction field. The output of the micro instruction register 100
The relationship among the orders IMD, OPR, BR and CNT is as shown below.

However, ----- here indicates a value other than 101010.

The micro order IMD is connected as a read signal of the 32-bit data buffer 114, and bit 8 (bit. [8]) and bit 9 (bit. [9]) of the micro instruction register 100 are byte position information BYT0 /. 1 is connected to the 2-bit decoder 115, and bits 0 to 7 (func) of the micro instruction register 100 are connected to the 8-bit data generating means 110 to 113.

Next, the operation of constant generation in this microprogram controller will be described.

Now, in the micro instruction register 100, 101010010101 010 0
If the data 1111010 is stored as a microinstruction, the microinstruction decoder 102 stores 10101 in src.
Since there is a pattern of 0, the micro-order IMD is activated and other micro-orders OPR, BR, C
Inactivate NT. Micro instruction register 1
Since the bit [8..9] of 00 is 10, the 2-bit decoder 115 activates only SEL2, SEL0,
Inactivate SEL1 and SEL3. Therefore, only 112 of the 8-bit data generating means 110 to 113 generates the same value as func, that is, 01111010, and the other 8-bit data generating means 110, 111, 113 generate 00000000. Since the 32-bit data buffer 114 is connected to the 32-bit data bus 101 by the micro-order IMD, the 32-bit data bus 10
1 can get 00000000 01111010 00000000 00000000.

As described above, by using the present embodiment, a 32-bit constant in which 8-bit data is placed at an arbitrary byte position, that is, m ^* ( ^256∧n ) (m is 0 to 255, n is 0)
~ 3) can be obtained.

In this embodiment, a value from 0 to 255 ^* (256 ^∧ 3) can be expressed, but since the precision of the value is only 8 bits, any 3
Although it is not possible to obtain 2-bit data, the constants used in microprograms often extract a specific bit string or use data with no weight in the bits concentrated for a specific byte data. , Can be used as is for many applications.

Further, in order to obtain arbitrary 32-bit data, the 8-bit shift operation is not necessary as compared with the conventional microinstruction execution for generating a constant, and therefore the following simplification can be performed.

Transfer the 32-bit immediate to register R ₁ .

Transfer the next 32-bit immediate to register R ₂ .

The logical sum of R ₁ and R ₂ is stored in R ₁ .

Transfer the next 32-bit immediate to register R ₂ .

The logical sum of R ₁ and R ₂ is stored in R ₁ .

Transfer the next 32-bit immediate to register R ₂ .

The logical sum of R ₁ and R ₂ is stored in R ₁ .

Whereas the conventional micro instruction for generating arbitrary 32-bit data described above requires 10 steps,
It is understood that the number of steps can be shortened to 7 in this embodiment.

Next, another embodiment of the present invention will be described. FIG. 7 shows another embodiment of the present invention, in which selection signals SEL0-S0.
Means 810-813 for selecting the lower 8 bits func of the instruction field of the microinstruction register 100 when EL3 is active, and otherwise generating 8-bit zero data or 8-bit all-1 data by the output selection signal ZERO. The characteristic is to have.

As in the above embodiment, the byte position information BYT0 / 1 is 0.
If it is 0, the selection signal SEL0 is set.
If L1 is 10, the selection signal SEL2 is active, and if L1 is 11, the selection signal SEL3 is active. Select signal SEL0
~ 8-bit data generating means 10 selected by SEL3
The lower 8 bits fu of the instruction field are output to 0 to 113
Although nc is output, the 2-bit decoder 115 generates the selection signals SEL0 to SEL3 so as to be exclusively activated, so that three sets of the unselected 8-bit data generation means 110 to 113 are output. 8-bit zero data or all 1's are output to the output of the output signal ZERO by the output selection signal ZERO.

Therefore, when the read signal IMD becomes active, the data output from the 32-bit data buffer 114 to the 32-bit data bus 101 according to the contents of the byte position information BYT0 / 1 is as follows.

However, the expression bus. [X..y] here is 32 bits.
Indicates the range from bit x to bit y of data bus 101, where nnnnnnnn is the lower 8 bits of the instruction field imd
Zzzzzzzz is 111111111 if the output selection signal ZERO is 1, and 00000000 if it is 0.

FIG. 6B is an example of the instruction format of the microinstruction applied to the present embodiment. SRC for the instruction format of FIG.
When a constant is selected in the field, the most significant bit of the ID field has a meaning to specify whether the 24-bit data that is not a valid byte for the 32-bit immediate is set to 0 or 1. Is.
That is, if the ID field is 0XX, all zeros are selected, and if 1XX, all 1s are selected.

Next, the operation of generating a constant in this embodiment will be described. Now, 101010 010101 in the micro instruction register 100
If the data 100 10 100 110 is stored as a microinstruction, the microinstruction decoder 102 outputs src101
Since there is a pattern of 010, the micro-order IMD is activated and other micro-orders OPR, BR, C
Inactivate NT. Micro instruction register 1
Since the bit. [8..9] of 00 is 00, the 2-bit decoder 115 activates only SEL0, SEL1,
Inactivate SEL2 and SEL3. Therefore, only 810 of the 8-bit data generating means 810 to 813 generates the same value as func, that is, 10100110, and the other 8-bit data generating means 811, 812 and 813 generate 11111111 because the output selection signal ZERO is 1. Let 32-bit data buffer 1 by micro-order IMD
14 on the 32-bit data bus 101 11111111 1
1111111 11111111 10100110 can be obtained. This 32-bit data is 00000000 00000000 00000000 0
It is the two's complement of 32-bit data such as 111010.

In this embodiment, the range of expressible values is expanded from 0 to 2 ^∧ 32-1. Furthermore, microprograms that require integer constants can easily express negative numbers.

FIG. 8a is a drawing for explaining the 8-bit data generating means used in FIG. 1 in more detail.
Gates 1030 to 1037 and the 2-input AND gate 1030 to
Two-input OR gate 1040 which uses the output of 1037 as one input
1047, a 2-input AND gate 1038, and an inverter 1050. The other inputs of the 2-input AND gates 1030 to 1037 are connected to the selection signal SEL, and the 2-input OR gate 1040 is connected.
The other input of ~ 1047 is connected to the output of a 2-input AND gate 1038. One input of the 2-input AND gate 1038 is connected to the output of the inverter 1050 whose input is the selection signal SEL, and the other input is connected to the output selection signal ZERO. If the selection signal SEL is active (1), 2 inputs A
The outputs of the ND gates 1030 to 1037 are the same as the inputs IN0 to 7. On the other hand, since the output of the 2-input AND gate 1038 becomes 0, the output of the 2-input OR gates 1040 to 1047 is the 2-input AN.
It is the same as the output of the D gates 1030 to 1037. Therefore, the same data as the inputs IN0 to 7 appears at the outputs OUT0 to OUT7.

When the selection signal SEL is inactive (0) and the output selection signal ZERO is 0, the 2-input AND gate 10
The outputs of 30 to 1037 are all 0 regardless of the values of the inputs IN0 to 7. On the other hand, the 2-input AND gate 1048 is 0 because one input ZERO is 0, and the outputs of the 2-input OR gates 1040 to 1047 are 2-input AND gates 1030 to 1037.
Is the same as the output of. Therefore, the outputs OUT0 to OUT7 are all zero. Furthermore, the selection signal SEL is inactive
When it is (0) and the output selection signal ZERO is 0, the output of the 2-input AND gate 1048 becomes 1, and the outputs of the 2-input OR gates 1040 to 1047 become 2 input AND gates 1030 to 1037.
Becomes 1 regardless of the output of. Therefore the output O
UT0 to 7 are all 1.

〔The invention's effect〕

As described above, by using the present invention, a constant having a large expression range can be obtained by executing one microinstruction without increasing the bit width of the microinstruction. Further, a constant having an arbitrary value can be obtained at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a conventional micro program control device, and FIGS. 3 a, b, and c are conventional micro instruction types. FIG. 4 is a format diagram showing a conventional microinstruction format, FIG. 5 is a circuit block diagram of constant generation using a conventional microprogram controller, and FIGS. 6a and 6b are used in the present invention. FIG. 7 is a block diagram showing another embodiment of the present invention, and FIG. 8A and FIG. 8B show details of the 8-bit data generating means used in the embodiment of the present invention. It is a circuit block diagram shown. 100: 23-bit micro instruction register, 101
32 bit data bus 102 micro instruction decoder 110-113 8 bit data generation means 114 32 bit data buffer 11
5 ... 2-bit decoder, 201 ... Control memory, 20
2 ... Micro instruction register, 203 ... Micro instruction decoder, 204 ... Register file, 205 ...
Arithmetic and logic unit, 206 ... Data bus, 401 ...
Transfer field, 402 Command field, 403
...... SRC field, 404 ...... DST field,
405 ... Identifier, 406 ... Function field, 501
...... Micro address register, 502 ... Control memory, 503 ... Micro instruction register, 504 ... Micro instruction decoder, 505 ... Operation control unit, 506 ...
... Branch controller, 507 ... Controller, 510 ... Source operand decoder, 511 ... Destination operand decoder, 512 ... Constant buffer, 520 ... Data bus, 521 ... Register file, 522 ... Other register resources, 523 ...
Source operand bus, 524 ... Destination operand bus, 1000 to 1007 ... 2-input AND
Gate, 1030 to 1038 ...... 2-input AND gate, 1040 to 10
47 …… 2-input OR gate, 1050 …… Inverter.

Claims (1)

[Claims] 1. A means for temporarily holding a microinstruction, a means for detecting a bit pattern of a first field of said holding means, and a predetermined data or contents of a second field of said holding means. It has a plurality of data generating means for selectively outputting, and according to the bit pattern detected by the detecting means, only one of the plurality of data generating means is provided with the contents of the second field of the holding means. A microprogram control device, characterized in that outputs of the predetermined data selectively output and selected by the other plurality of data generating means are linked to independent bit positions and used as constant data.