JPH0626054B2 - Tracking servo device - Google Patents

Description

The present invention relates to a servo method for a video tape recorder (VTR). Particularly, it relates to tracking adjustment of a servo circuit using a microcomputer.

(B) Conventional Technology The VTR motor servo was previously composed of analog circuits. However, in the case of an analog circuit, the characteristics of the circuit element change with temperature and aging, which poses a problem in terms of long-term stability.

Therefore, this motor servo circuit may be created by a digital circuit. Since the digital system uses a highly accurate and stable clock, circuit elements are less likely to change over time.

By the way, as is well known, it has been proposed to realize this digital type servo circuit by software (program). That is, the servo circuit is composed of a microcomputer. In this way, the specification of the servo circuit and the constants during special reproduction can be changed by changing the program.

A servo circuit based on such a microcomputer (software) is disclosed in the following document, for example. NEC
Technical report Vol.39 No.10 / 1986 p. 75-p.81 “CMOS 8-bit single-chip microcomputer, μPD7811
2 ”. Magazine "TV Technology" published by Electronic Technology Publishing Co., Ltd.
May 1987 issue ”p. 19-p. 25 "Sanyo Digital AF Equipped 8mm Video Movie". JP-A-61-94577 (H
02P 5/00). JP 62-55714 (G05D 13/62). Japanese Patent Application No. 62-42274 filed by the applicant on February 24, 1987
issue.

By the way, a 1/2 inch VTR for home use is provided with a tracking adjustment knob. This tracking adjustment is
As is well known, it is intended to correct tracking deviation when reproducing a video tape recorded by another VTR or reproducing a video tape expanded due to aging. This tracking adjustment adjusts the relationship between the tape feed during reproduction and the rotational phase of the video head in the same manner as during recording. In order to correct the relationship between the two, for example, the delay time of the reproduction control signal is changed. The tracking adjustment can also be performed by adjusting the delay time of the reference signal that is phase-compared with the reproduction control signal (JP-A-57-42278, G11B 5/783). In short, it suffices if the rotational phase relationship between the tape feed (capstan) and the head (cylinder) can be changed.

This delay circuit for tracking adjustment has a conventional resistance (R).
A monomulti that includes a capacitor and a capacitor (C) is used. If this mono-multi is changed to a digital mono-multi, the accuracy of this delay circuit can be improved. (JP-A-60-1
50260, G11B 15/467) Figure 5 shows such an example. Figure 5 shows VT during playback
The operation of R is shown. (10) is a video tape, and (10a) is a control track portion. (12) is a control head, and (14) is a control pulse amplifier. (1
6) is digital mono-multi. This digital mono-multi (16) delays the control pulse for a predetermined time and outputs it to the microcomputer (22). (18) is a tracking adjustment up / down button (tracking adjustment means). Reference numeral (20) is a memory in which data is set by the up / down button (18). The digital mono-multi (16) counts the clock after the control signal is input, and outputs a control pulse to the microcomputer (22) when the count value matches the data in the memory (20). (24) is a counter circuit.
This counter circuit (24) is reset by a 30 Hz reference signal (Ref). (26) is an oscillator for a clock signal.

The microcomputer (22) controls the capstan motor (CM) so that the data of the counter circuit (24) when the control pulse is input becomes a predetermined value. PWM wave signal generation circuit (hereinafter,
A PWM wave circuit (27) outputs a signal for this control as a PMW wave. Capstan motor (CM)
Is controlled by this. (26) is the capstan.
Reference numeral (28) is a signal line for outputting the FG signal of the capstan motor (CM) to the microcomputer (22).

Although the microcomputer (22) is controlled by software,
It is shown in a block diagram in FIG. (22b) is a speed servo circuit. This speed servo circuit (22b) is based on
As shown in No. 1-94577, speed servo data is output by measuring the FG pulse intervals. Reference numeral (22c) is a latch circuit for latching the value of the counter circuit (24) by a control pulse. The latch circuit (22c) constitutes a phase servo circuit that outputs phase servo data.
(22d) is an adder circuit for adding the phase servo data and the speed servo data. This adder circuit (22d) sets the duty ratio of the PWM wave circuit (27). (24) is a counter circuit. This counter circuit (24) is reset by the 30 Hz reference signal. This reference signal is also used as a reference signal for phase servo of a rotary head (cylinder) (not shown). That is, this reference signal is related to the rotational phase of the head.

Actually, the microcomputer (22) is time-divisionally (sequentially) controlled based on a program as is well known. That is, the microcomputer (22) has a mode of operating as a speed servo circuit of the capstan and a mode of operating as a phase servo circuit of the capstan. It is also conceivable to use this microcomputer as a system control circuit or as a servo circuit for a head motor.

(C) Problems to be solved by the invention By the way, if the value of the memory (20) is changed during the operation (counting) of the digital mono-multi (16), the first digital mono-multi (16) after the change is displayed. The output may be incorrect. For this reason, the timing of changing the value of the memory (20) must be controlled so as to be performed when the digital mono-multi (16) is not operating.

As a countermeasure, this digital mono
It is possible to have the function of (16). For example, the range indicated by the dotted line in FIG. 5 is the microcomputer (22 ').

The control pulse is input to the microcomputer (22 '). The microcomputer (22 ') is in the capstan phase servo circuit mode. The digital mono-multi (16) in the microcomputer (22 ') starts counting operation when this control pulse is input. At the end of this counting, the latch circuit (22c) latches the data of the counter circuit (24).

However, in the above operation, during the counting operation of the digital mono-multi (16) in this microcomputer (22 '), this microcomputer (2
2 ') maintains the capstan phase servo circuit mode.
For this reason, the microcomputer (22 ') operates for a long time in the capstan phase servo circuit mode, and the use time in other modes is limited.

(D) Means for Solving the Problems In the present invention, tracking adjustment data is created by the tracking adjustment means (18), and the latched data of the counter circuit (24) is corrected by the tracking correction data to use for phase servo. It is characterized by creating data of.

(E) Action Since the present invention has the above-described configuration, the latched data of the counter circuit (24) is corrected by the tracking correction data. By this correction, the same effect as the delay of the control signal by the conventional mono-multi can be obtained. Since this correction is executed by arithmetic processing such as addition or subtraction of the data of the counter circuit (24) and the tracking correction data, the required time is short.

(F) Embodiment An embodiment of the present invention is shown in FIG. Incidentally, in FIG. 1, the same parts as those in FIG.

Reference numeral (20 ') is a memory (tracking correction data output means) for tracking correction data set by the tracking adjustment means (18). The memory (20 ') is reset when the tape cassette is inserted and the tracking correction data is set to "0". (22e) is a memory read this tracking correction data (D _R). (22f) is data from the latch circuit (22c) (tracking data)
From (D _T), an arithmetic circuit for subtracting the memory tracking correction data (D _R) of (22e). This arithmetic circuit (22
f) outputs the capstan phase servo data (Dapc).

The above operation will be described. The counter circuit (24) is reset by the reference signal [Fig. 2 (a)] and outputs the data shown in Fig. 2 (b).

Here, the timing of the control pulse when playing back a cassette tape that does not require tracking adjustment
It is shown in Figure (c). At the rising portion of the control pulse (CTL) from the control head (12), the microcomputer (22) enters the capstan phase servo circuit mode. Then, the value of the counter circuit (24) is latched by the latch circuit (22c). At this time, the value latched by the latch circuit (22c) is used as a reference data value [A _{0 in} FIG. 2B). Latch circuit
(22c) outputs tracking data. At this time, the values of the memories (20 ′) and (20e) are “0”, so the value of the phase servo data (Dapc) output from the arithmetic circuit (22f) is (A ₀ ).
Is. This phase servo data (Dapc) is added to the adder circuit (2
It is added to the velocity servo data in 2d) and output to the PWM wave circuit (27) as capstan servo data. PWM
The wave circuit (27) keeps the PW according to this data until the next capstan servo data is output from the microcomputer (22).
Output M wave. In addition, the circuit of FIG.
Each part is set so that the output data (Dapc) of 2f) becomes the reference data value (A ₀ ).

Next, a case where a tape whose tracking is deviated is reproduced will be described. As shown in FIG. 2 (d), there is also a cassette tape in which tracking is suitable when the generation timing of the control signal is normal compared to [FIG. 2 (c)].

In this case, the user adjusts the tracking adjustment means (18) while watching the reproduction screen to perform the tracking adjustment. The value (tracking correction data) of the memory (20 ') at the time of completion of this adjustment is (B ₁ ) shown in FIG.

The operation in this case will be described. The rising of the control pulse (CTL) from the control head (12) causes the microcomputer (22) to enter the capstan phase servo circuit mode. The value of the counter circuit (24) is latched by the latch circuit (22c). At this time, the value latched by the latch circuit (22c) becomes (A ₁ ) in FIG. Then, the microcomputer (22) is tracking correction data (D _R) of the memory of the memory (20 ') (2
Take in 2e). Arithmetic circuits (22f), the data value from the latch circuit (22c) from (A _1), subtracts the tracking correction data in the memory _(22e) (B 1). Therefore, the value of the phase servo data is A ₀ (= A ₁ −B ₁ ). That is, the value of the phase servo data (Dapc) at this time is the same as in the normal case [in the case of FIG. 2C)], and the phase of the capstan motor (CM) does not change.

If the control pulse is as shown in Fig. 2 (e), the microcomputer
The value of the tracking data of the latch circuit (22c) of (22) becomes (A ₂ ) shown in FIG. The value of the tracking correction data memory (20 ') _{(D R)} becomes (-B _2). The value of the phase servo data (Dapc) of the arithmetic circuit (22f) is A ₀ (= A ₂ + B ₂ ).

In this circuit, control is performed so that the value of the phase servo data becomes (A ₀ ). As shown in FIG. 3, the phase servo data (Dapc) is converted into the phase servo reference data value (A
₀ ) and phase servo error data (Dapce) is created, and the capstan is controlled so that this value becomes "0". In FIG. 3 (a), (22g) is the phase servo data (Dapc) from the arithmetic circuit (22f) and the phase servo reference data (A ₀ ) previously stored in the memory (22h). Compare phase servo error data (Dapce)
Is a comparison circuit that outputs This VTR feedback-controls the capstan motor so that the phase servo error data (Dapce) becomes "0". (22i) is a comparison circuit, and this comparison circuit (22i) is a speed servo circuit (22h).
And the speed servo reference data stored in advance in the memory (22j) are compared and the speed servo error data is output. (22k) is an adder circuit for adding the speed servo error data and the phase servo error data.

FIG. 3 (b) is a modification of the calculation procedure of the phase servo error data, and the final data value is the same as that of FIG. 3 (a). That is, added by the memory tracking correction data (D _R) and phase servo reference data value in the memory (22h) in _(22e) (A 0) the adder circuit (22l). Then, the arithmetic circuit (22m) subtracts the data from the adder circuit (22l) from the tracking data (D _T ) from the latch circuit (22c).

Next, the outline of the servo circuit of the VTR adopting the present invention will be described with reference to FIG.

First, an outline of the operation of this servo circuit will be described. This servo circuit is of a type in which the capstan motor (CM) and the head motor (HM) are controlled by one microcomputer (22) (for example, a Hachimaru system microcomputer, Z80). As in the conventional case, the FG pulse (CFG) from the capstan motor (CM), the control pulse (CTL) from the control head (12), and the PG from the head motor (HM)
Microcomputer (22) for pulse (PG) and FG pulse (HFG)
To enter. The microcomputer (22) uses the FG pulse (CFG, H
For FG), the state of speed deviation is detected by detecting the generation interval. Regarding the PG pulse (PG) and the control pulse (CTL), the state of phase shift is detected by detecting the interval between the reference signal and these pulses (PG, CTL). The counter circuit (24) is used to detect this interval as in the conventional case.

The characteristic of this servo circuit is that pulse signals (PG, HFG,
The input terminal of CFG, CTL) is ▲ of the microcomputer (22)
One of the terminals (maskable interrupt terminals). For this reason, this servo circuit uses a well-known interrupt controller (30).
Is equipped with. This interrupt controller (30) is, for example, "8259A" manufactured by Intel or "μ" manufactured by NEC Corporation.
PD71059 ". The input terminal ▲ ▼ of this interrupt controller (30) indicates the priority.

When a signal is input to the ▲ ▼ terminal of the microcomputer (22),
Servo mode is entered, but the signal input to this terminal is four signals (PG, HFG ', CFG', C).
TL ') is inputted from the interrupt controller, and a mode (capstan phase servo circuit mode, capstan speed servo circuit mode, cylinder phase servo circuit mode,
Cylinder speed circuit servo mode) is set. The interrupt controller (30) determines which signal is input to the ▲ ▼ terminal via the buffer (38) (40) and the microcomputer (2
Output to 2). When multiple signals are input, the interrupt controller (22) selects the one with higher priority from the microcomputer.
Output to (22). For example, PG 'signal (priority 1) and C
When the FG 'signals (priority level 3) are input at the same time,
It outputs when the PG 'signal is input to the microcomputer (22).

Each part of FIG. 4 will be briefly described. (CM) is a capstan motor, which outputs an FG pulse (CFG).
(HM) is a head motor, and FG pulse (HF)
G) and PG pulse (PG) are output.

(12) is a control head. (SW ₁ ) is a changeover switch. This changeover switch (SW ₁ ) is a VTR
The control pulse (CTL) reproduced by the control head (12) is output at the time of reproducing, and the vertical synchronizing signal extracted from the video signal is halved at 30Hz at the time of VTR recording.
The reference signal of is output to the control head (12). (32)
Is a frequency dividing circuit, and the frequency dividing ratio of the frequency dividing circuit (32) is set by the microcomputer (22) according to the operation mode. (34a)
(34b) (34c) (34d) are latch circuits, which are pulse (PG,
HFG, CFG, CTL). (30) is an interrupt controller.

(22) is a microcomputer. (36) is a clock signal oscillator for the microcomputer.

(38) is an address buffer, and (40) is a data buffer. The microcomputer (22) controls (transmits and receives data) each part via the buffers (38) and (40).

Reference numeral (42) is a ROM for storing the control program, and (44) is a work area RAM. (46) is an EEPROM [Electric E that stores the adjustment data of the VTR equipped with this microcomputer.
rasable Program Read on Memory).

(24) is a counter circuit. The counter circuit (24) is reset by the reference signal. (26) is a counter circuit (24)
Is a clock signal oscillator. (48) is a second counter circuit for producing a 30 Hz reference signal. (SW ₂ ) is a changeover switch. When reproducing the VTR, the counter circuit (24) is reset by the reference signal (Ref) from the second counter circuit (48). During VTR recording, the counter circuit (24) is reset by a reference signal obtained by dividing the vertical synchronizing signal extracted from the video signal by 1/2.

A signal for resetting the counter circuit (24) is input to the ▲ ▼ terminal (non-maskable interrupt terminal) of the microcomputer (22). The microcomputer (22) enters a mode for detecting the VTR operation mode at this time by inputting to the ▲ ▼ terminal (since this detection is not directly related to the present application, the circuit for this detection is not shown). .

(18 ') is a tracking adjustment means composed of an up button and a down button, and outputs tracking correction data certified by the tracking adjustment. Reference numeral (50) is an interface circuit for outputting the tracking correction data from the tracking adjusting means (18) to the microcomputer (22). The interface circuit (50) acts as an intermediary between the microcomputer (22) and the tracking adjustment means (18).

(52) is a servo data latch circuit for latching servo data (for capstan and head) output from the microcomputer (22). This data latch circuit (52)
This data is held until the next servo data is output from the microcomputer (22).

(27) is a PWM wave circuit that outputs a PWM wave based on the capstan servo data from the data latch circuit (52). Reference numeral 54 is a PWM wave circuit that outputs a PWM wave based on the head servo data from the data latch circuit 52.

The speed servo control of the capstan motor in the above circuit will be briefly described.

The capstan motor (CM) outputs an FG pulse (CFG). This FG pulse (CFG) is frequency-divided by the frequency dividing circuit (32), then latched by the latch circuit (34c), and input to the terminal () of the microcomputer (22) through the interrupt controller (30). The microcomputer (22) uses the address buffer (3
The data indicating that this input signal is the CFG 'signal is read from the interrupt controller (30) via 8) and the data buffer (40), and the capstan speed servo circuit mode is set by this data.

The microcomputer (22) reads the value of the counter circuit (24)
It goes without saying that the buffers (38) (40) are used, so the description of the buffers (38) (40) is omitted to simplify the description. Then, the value of this counter circuit (24) is set to RA, for example.
The value is temporarily stored in M (44) and the value stored in RAM (44) at the time of the previous CFG signal input is read. And this R
Previous value read from AM (44) and counter circuit (24)
The read values are compared to calculate the FG pulse signal interval, and capstan velocity servo data is created.
When the value of the capstan speed servo data at this time is far from the normal value, the previous speed servo data is read from the RAM (44) and used. Incidentally, such a situation occurs, for example, immediately after the counter circuit (24) is reset.

Microcomputer (22) is RAM for capstan speed servo data
Store in (44). Further, the microcomputer (22) reads the capstan phase servo data stored in the RAM (44) and adds the capstan phase servo data and the capstan speed servo data. The capstan servo data created by the addition is output to the servo data latch circuit (52). The servo data latch circuit (52) converts the capstan servo data to the capstan PWM wave circuit.
Output to (27). The microcomputer (22) is an interface circuit (5
Release the latch of the latch circuit (34c) via 0).

Next, the phase servo control of the capstan motor (CM) will be briefly described.

Control pulse from control head (12) (C
TL) through switch (SW ₁ ) to latch circuit (34d)
Is latched by. Then, it is input to the ▲ ▼ terminal of the microcomputer (22) via the interrupt controller (30). The microcomputer (22) reads the data of the interrupt controller (30) via the buffers (38) and (40) by this input. The interrupt controller (30) outputs data indicating that the input to the ▲ ▼ terminal is a CTL 'signal.
The microcomputer (22) enters the capstan phase servo circuit mode by the data from the interrupt controller (30).

The microcomputer (22) is a counter circuit via the buffers (38) (40)
Read the data of (24). Microcomputer (22) is buffer (38)
(40) reads the tracking correction data of the tracking adjustment means via the interface circuit (50) (18 ') ( D R). The microcomputer (22) corrects the data read from the counter circuit (24) with tracking correction data to calculate capstan phase servo data.

The microcomputer (22) reads the capstan speed servo data from the RAM (44) and adds this data and the capstan phase servo data to create capstan servo data. This capstan servo data is output to the servo data latch circuit (52). The microcomputer (22) stores the capstan phase servo data in the RAM (44). Then, the microcomputer (22) resets the latch circuit (34b) via the interface circuit (50).

In this embodiment, the head servo requires higher accuracy than the capstan servo, so the signals (PG, HFG) from the head motor are set to have a high priority.

(G) Effect of the Invention As described above, in the present invention, the tracking adjustment is not performed by adjusting the delay time of the control pulse or the reference signal, but the data value of the latched counter circuit is corrected by arithmetic processing. Therefore, even if the tracking adjustment is performed in the microcomputer, the processing time is short and no inconvenience occurs. Therefore, the digital mono-multi for tracking adjustment can be omitted, which is useful.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram for explaining the operation. FIG. 3 is a diagram showing another example when the present invention is shown as hardware. FIG. 4 is a diagram for explaining the microcomputer servo. FIG. 5 is a diagram showing a conventional example. (D _R) ...... tracking correction data, (10) ... tape, (22e) (20 ') ... memory (tracking correction data output means), (18') ...... tracking adjustment means (tracking correction data output means ), (CTL) ... control pulse, (PG) ... PG pulse (signal related to head rotation phase), (Ref) ... reference signal (signal related to head rotation phase), (D _T ). ...... (Tracking data), (Dapc) …… Phase servo data (data for phase servo), (Dapce) …… Phase servo error data (data for phase servo), (24) …… Counter circuit, (26 ) ...
… Capstan.

Claims (3)

[Claims] 1. Tracking correction data output means for outputting tracking correction data, and data creating means for creating tracking data related to a phase difference between a control pulse reproduced from a tape and a signal related to a rotational phase of a head. A tracking servo apparatus comprising: means for correcting the tracking data with the tracking correction data by an arithmetic process such as addition and subtraction to create data for phase servo. 2. The data creating means comprises a counter circuit that is reset by a reference signal related to the rotational phase of the head, and a latch circuit that latches the value of the counter circuit when a control pulse is input. The tracking servo device according to claim 1. 3. The tracking servo device according to claim 2, wherein the phase servo data is for controlling the rotation of the capstan.