JPH0626166B2 - Rotary solenoid circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a rotary solenoid circuit in which a method for driving a rotary solenoid is energy-saving.

<Prior Art> A conventional rotary solenoid circuit has a circuit configuration in which a rotary solenoid or a solenoid (hereinafter, simply referred to as “solenoid”) is driven by simply energizing a coil.

However, the force required to drive the solenoid (that is, current and voltage) needs to be large only at the time of starting, and the force required to maintain the drive state of the solenoid after the operation at the time of starting is small. There were many things. Even in such a case, if the coil is continuously energized and a force of the same magnitude as that at the time of starting is applied, the following problem occurs. That is, there are problems such that the temperature rise of the coil becomes large and the electronic device incorporating the solenoid circuit is adversely affected, the insulation resistance of the solenoid itself is lowered, or the solenoid or the like is overheated. .

<Problems to be Solved by the Invention> The present invention has been made in view of the drawbacks of the conventional example, and an object thereof is to provide a rotary solenoid circuit capable of driving the rotary solenoid with the least energy. is there.

<Means for Solving Problems> A feature of the present invention for solving the above problems is that a large voltage is applied in the rotary solenoid circuit at the early stage of driving the solenoid to secure a driving torque, and the solenoid operates once. After that, the circuit configuration is such that the minimum necessary torque is generated and the rotation angle is secured.

<Example> Hereinafter, the present invention will be described in detail with reference to the drawings. First
1 is a circuit diagram of an embodiment of the present invention, in which 1 is a solenoid, 2 is a capacitor connected in parallel to the solenoid 1, 3 is an AC power supply, 4 is a photothyristor coupler PC ₁ , PC ₂ and NAND. A zero-cross pulse generator circuit 5 which sends out a pulse signal A at a zero-cross timing of an AC voltage waveform for each half cycle of an AC voltage applied from an AC power source 3, and a command signal B for turning on the solenoid 1 and a later-described command signal B. A central processing unit (hereinafter referred to as "CPU") that sends out a setting signal (divided signal, etc.) of the counter 6, 6 is a pulse signal A of the zero-cross pulse generation circuit 4.
Output signal C corresponding to the above setting signal from CPU 5
Is a counter for sending out, and 7 is the above setting signal B from the CPU 5.
A flip-flop circuit that sends an output signal B'that turns on the solenoid 1 at the timing of the pulse signal A sent from the zero-cross pulse generation circuit 4, and 8 rectifies the applied AC voltage into a DC voltage. Wave rectifier. FIG. 2 is a time chart for explaining the operation of the embodiment of the present invention having the above-described structure. In the figure, (a) is the power waveform of the AC power supply 3 and (b) is the zero-cross pulse generation circuit 4. Waveform of pulse signal A sent from, (C) is CPU
5, the waveform of the command signal B sent from the circuit 5, (d) is the waveform of the output signal B ′ sent from the flip-flop circuit 7, (e)
Is the waveform of the output signal C sent from the counter 6, (f) is the waveform of the control voltage E applied to the full-wave rectifier 8, and (g) is the waveform of the solenoid drive voltage F applied to the capacitor 2.

The operation of the embodiment of the present invention will be described below with reference to FIGS. 1 and 2. In FIG. 1, the zero-cross pulse generation circuit 4 is, as shown in FIGS. 2A and 2B,
The zero cross point of the voltage waveform of the AC power supply 3 is detected, and the pulse signal A synchronized with the voltage waveform is output. Counter 6
It is set by a setting signal from the CPU 5, and when it receives the pulse signal A, it outputs an output signal C as shown in FIG. 2 (e) according to the setting. On the other hand, as shown in FIG. 2 (d), a command signal B (see FIG. 2 (c)) for turning on the solenoid 1 is sent from the CPU 5 and is output at the timing of the pulse signal A in the flip-flop circuit 7. Output signal B '. The output signal B'and the output signal C of the counter 6 are input to an AND circuit and output as a solenoid drive signal D in order to prevent noise generation. The drive signal D is input to the AC voltage control unit including the photothyristors PS ₁ and PS ₂ and the triac T _{1 and the} like, as shown in FIG.
A voltage E having a waveform as shown in (f) is applied to the full-wave rectifier 8. The voltage E is converted by the full-wave rectifier 8 into a solenoid drive voltage F as shown in FIG.
By the action of the capacitor 2, the average voltages V ₁ and V ₂ as shown by the wavy line in FIG. by the way,
A large force is required to operate the solenoid 1 for a period X (hereinafter, this period is referred to as "driving initial period") for a while after the solenoid drive signal D is output from the AND circuit, and the counter 6 is ON during this period. The counter output C is transmitted. Further, during the subsequent period Y (hereinafter, this period is referred to as "drive holding period"), the torque for holding the solenoid 1 may be small, so that the setting signal sent from the CPU 5 to the counter 6 is shown in FIG. For example, 1 as shown in (e)
A counter 6 outputs an output signal C that has been frequency-divided to / 3 (the frequency-division ratio is arbitrary, and can be a frequency-division ratio of m / n when m and n are integers). In this way, the drive voltage V ₁ is applied to the solenoid 1 only during the period X, and the drive voltage V ₂ is applied during the period Y. Therefore, the solenoid 1 is driven with the least energy, and the wasteful consumption of electric power and heat generation as seen in the conventional example can be effectively and appropriately prevented. The present invention is not limited to the above-described embodiment, and various modifications can be made. For example, a photo interrupter for detecting the operation of the solenoid 1 is installed, and the output signal of the interrupter is fed back to the counter 6 for division. The circumference ratio may be changed.

FIG. 3 is a modified constitutional circuit for explaining a modified embodiment of the present invention, and FIG. 4 is a time chart of FIG. In the figure, the same symbols as those in FIG. 1 are used with the same meanings, and duplicate explanations are omitted here. Further, 9 is a gate circuit composed of a plurality of AND circuits, 10 is a latch circuit for latching the output of the gate circuit 9, 11 is a counter, and 12 is a counter 1.
1. A gate control unit composed of an AND circuit, a NOT circuit, and an OR circuit for sending a gate opening / closing signal to the gate circuit 9, N _{1 to} N ₇ are solenoid drive signals D _{1 to} D ₇ output from the latch circuit 10. The receiver is a solenoid drive unit for applying a desired drive voltage to each built-in solenoid as described in detail with reference to FIGS. 1 and 2. In the modified embodiment of the present invention having such a configuration, the zero-cross pulse generation circuit 4 detects the zero-cross point of the voltage waveform of the AC power supply 3 (Fig. 4 (n)), and the pulse signal A synchronized with the voltage waveform. (Fig. 4 (L)) is output. The signal A
Are sent to the CPU 5, the latch circuit 10, and the counter 11, and the counter 11 sends output signals C ₁ and C ₂ (FIG. 4 (e) (wa)) according to the pulse signal A.

The output signals C ₁ and C ₂ are generally signals represented by a voltage waveform of m / n of a half-frequency divider voltage waveform of an AC power supply, where m and n are integers. Further, the signals C ₁ and C ₂ are
It is input to the OR circuit via the AND circuit or NOT circuit. The driving ON signal B ₀ (FIG. 4 (re)) is also input from the CPU 5 to the OR circuit via the NOT circuit, and the logical sum operation of these two inputs is performed. As a result of such calculation, a gate opening / closing signal is sent from the gate controller 12 to the gate circuit 9. On the other hand, command signals B _{1 to} B ₇ (FIG. 4 (so), (tsu), (ne)) for turning on the respective solenoids in the solenoid drive units N _{1 to} N ₇ are also input from the CPU 5 to the gate circuit 9. ing. Therefore,
These command signals B _{1 to} B ₇ are input to the latch circuit 10 according to the gate opening / closing signal, and the output D _{1 of the} latch circuit 10 is input.
˜D ₇ (FIG. 4 (na) (la) (mu)), a desired drive voltage E is applied to each solenoid of the solenoid drive parts N _{1 to} N _7.
(Fig. 4 (c) (a) (no)) is applied. That is, when the driving ON signal B ₀ is sent from the CPU 5, a gate open signal is sent from the OR circuit of the gate control unit 12 to all 1 AND circuits of the gate circuit 9, and ultimately the solenoid drive unit N ₁ ... A large driving voltage is applied to all solenoids of N ₇ . Further, when the driving on signal B ₀ is turned off at the end of the period X, the OR of the gate control unit 12 is performed.
A gate opening / closing signal corresponding to the outputs C ₁ and C ₂ of the counter 11 is sent from the circuit to the gate circuit, and finally the smallest drive voltage is applied to the solenoid. Therefore, also in the modified embodiment of the present invention, as in the case of the embodiment of the present invention described in detail with reference to FIG. 1 and FIG. Effectively preventable.

The driving ON signal B ₀ is a signal for applying a large voltage during the initial period X of the drive start α of the rotary solenoid valves 2 and 5 (shown in FIG. 4 (SO)) originally in the embodiment. However, at the same time, the rotary solenoid valves 1, 4 and the rotary solenoid valves 3, 6, 7
A large voltage is being applied. This is because the driving ON signal B ₀ is connected in parallel to the three OR circuits of the gate control unit 12 to save the driving ON signal B ₀ circuit.

For each group of the rotary solenoid valves 1 and 4 and the rotary solenoid valves 3, 6 and 7, that is, for each OR circuit of the gate control circuit 12, a separate operation is performed according to the drive start timing of the rotary solenoid of each group. If the driving ON signals B ₀ , B ₀ ′ and B ₀ ″ are applied to the corresponding OR circuits, the rotary solenoid valves 1 and 4 and the rotary solenoid valves 1 and 4 during the drive holding period as in the embodiment of FIG. It is possible to avoid applying a large voltage to the rotary solenoids of each group of solenoid valves 3, 6, 7.

Further, as the OR circuit of the gate control unit 12, if so provided seven to correspond to the solenoid driving unit N ₁ to N _7, a large voltage is applied to the initial driving period of a predetermined rotary solenoid drive hold A rotary solenoid circuit is obtained in which there is no fear that a large voltage will be applied to other rotary solenoids during the period. The modified embodiment of the present invention is also the third embodiment.
The present invention is not limited to the embodiment shown in the figure. For example, the number of solenoid drive units N _{1 to} N ₇ may be n (n ≠ 7), and n solenoids may be driven.

<Effect> As described in detail above, according to the invention described in the first aspect of the invention, the solenoid is initially driven (during the period X).
A circuit configuration in which a large voltage V ₁ is applied to secure a drive torque and a small voltage V ₂ is applied once the operation is completed (during the period Y) to secure a rotation angle with a minimum required torque. Therefore, useless power consumption and heat generation can be prevented. Therefore, the disadvantages of the conventional example such as bad influence on the electronic device incorporating the solenoid circuit, insulation deterioration of the solenoid itself, and overheating of the solenoid are solved at once, and the rotary solenoid which can drive the solenoid with the least energy. The circuit is realized.

Further, since the setting means for increasing the frequency division ratio is used during the drive holding period, the voltage applied to the rotary solenoid becomes an intermittent ON voltage and OFF voltage.

Therefore, even in the drive holding period, a period in which the applied voltage is off can be obtained, and the power consumption can be significantly reduced.

Furthermore, according to the invention as set forth in claim 2, the same effect as that of the invention as set forth in claim 1 can be obtained, and in the gate control section, it is applied to the rotary solenoid in the drive holding period. By shifting the timings of intermittent on-voltages, it is possible to level the load of the power supply without overlapping the on-voltage timings of the plurality of drive circuits.

[Brief description of drawings]

FIG. 1 is a configuration circuit diagram of an embodiment of the present invention, FIG. 2 is a time chart explaining the operation of the embodiment of the present invention, FIG. 3 is a configuration circuit diagram of a modified embodiment of the present invention, and FIG. 4 is FIG. 6 is a time chart illustrating the operation of the embodiment. 1 ... Solenoid, 4 ... Zero cross pulse generation circuit,
7 ... Flip-flop circuit, 8 ... Full-wave rectifier, 9 ...
… Gate circuit, 10 …… Latch circuit, 11 …… Counter, 12
...... Gate control unit.

Claims (2)

[Claims] 1. A rotary solenoid circuit comprising a drive circuit having a rectification circuit for rectifying an AC power supply and a rotary solenoid connected to the output side of the rectification circuit, wherein a pulse signal is generated based on a zero cross of the output voltage of the AC power supply. And a setting means for setting a setting signal for increasing the frequency division ratio during the drive holding period subsequent to the initial period. A counter that divides the zero-cross pulse signal based on the frequency division ratio set by the setting means and outputs a rotary solenoid drive signal; and a counter that is applied from the AC power supply to the rectifier circuit based on the rotary solenoid drive signal. And an AC voltage control unit for turning on and off the AC voltage. . 2. A rotary solenoid circuit comprising a plurality of drive circuits each having a rectifying circuit for rectifying an AC power supply and a rotary solenoid connected to the output side of the rectifying circuit, wherein the output voltage of the AC power supply is zero-crossed. A zero-cross pulse generation circuit for transmitting a pulse signal based on the pulse signal, and an initial period for starting the drive of the rotary solenoid based on the pulse signal and the ON signal during driving has a small frequency division ratio and the drive hold following the initial period of the rotary solenoid. During the period, a gate control unit that sends a gate opening / closing signal with a large frequency division ratio, and a logical sum of the gate opening / closing signal and a command signal for operating a specific rotary solenoid of the plurality of rotary solenoids are calculated. A gate circuit for transmitting a selection signal and a plurality of drive circuits selected by the selection signal. A rotary solenoid circuit that operates.