JPH0626252B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MOSFET formed on a semiconductor on an insulator such as an insulating film or an insulating substrate.

[Background of the Invention]

In the conventional device, as shown in FIG. 2, a source / drain region is formed in a single crystal Si2 on a sapphire substrate 1 which is an insulator.
⁺ As a region, the channel region n ^- and the Deep Depletion
Type MOSFET. In (I E E E A transaction on Electron Devices Boriyumu Idei 13:00 No. 846-855 (1966) refer) This device, in the weak inversion region operation (operation at a gate voltage near the threshold) channel the n ^- entire area Therefore, although the carrier has a high mobility, it occurs in the interface region between the single crystal Si2 and the gate oxide film (gate insulating film) 3 in the strong inversion region (the operation is mainly in this region during actual use). The accumulated layer becomes a channel. Therefore,
Since the carrier is strongly drawn toward the gate oxide film 3 and travels in the channel while colliding with the gate oxide film 3, there is a problem that the mobility of the carrier becomes small. Further, in order to make such a deep depletion type MOSFET into an enhancement type, the conduction type of the polycrystalline Si 4 of the gate must be set to the conduction type opposite to the channel region (n-channel).
In the case of MOSFET, there is a problem that the process becomes complicated because of p ⁺ ).

In FIG. 2, electrode 5 is silica in FIG.

As another conventional device, a compound semiconductor is used as shown in JP-A-55-117281, and two or more compound semiconductors having different band gaps are joined (heterojunction).
There is an example in which a recess is formed in the conduction band to form a channel. As described above, since the channel is formed inside the semiconductor, not at the interface between the gate oxide or the insulating film and the semiconductor, in this conventional example, the gate oxide film or the insulating film collides with the carrier in the operation region where the gate voltage is high. Therefore, the mobility of the carrier does not become smaller than that of the above conventional example. However, the compound semiconductor has two heterojunctions.
There is also a problem that the manufacturing process becomes very difficult because it is also necessary to form a portion, and the crystallinity is disturbed or uneven in the heterojunction surface, though not so much as at the interface between the semiconductor and the oxide film. As a result, carriers are scattered and mobility is reduced.

In addition, the most common conventional surface channel MOSFET
Then, in addition to the problem due to the collision of carriers at the SiO ₂ —Si interface described above, there was a bad effect called the kink phenomenon of bending the drain current. This is n channel
In the case of MOSFET, since the potential of the p layer where the channel is formed is not fixed, this potential moves and the npn bipolar transistor is turned on. When this phenomenon occurs, normal MOSFET characteristics cannot be obtained.

[Object of the Invention]

An object of the semiconductor device of the present invention is to provide a high-speed and highly reliable MOSFET in which carriers are prevented from being directly scattered by the gate oxide film and the insulating film.

[Outline of Invention]

The feature of the present invention resides in that a pn junction is formed in the semiconductor region under the gate insulating film, and the conduction band wall is provided due to the difference in the Fermi level.

The basic structure of the present invention will be described by taking an n-channel MOSFET formed in single crystal Si on an insulating substrate as an example.

The sectional view is shown in FIG. 1, and the energy level diagram showing the principle is shown in FIG.

The same parts as those in FIG. 2 and corresponding parts are designated by the same reference numerals.

First, the principle when the present MOSFET shown in FIG. 1 is turned off will be described.
There is a pn junction in the single crystal Si2 under the gate,
As shown in FIG. 3 (a), due to the diffusion potential due to this junction, the depletion layer spreads to the bottom (insulator) in the n ⁻ region and pinches off, so that no carrier is present and a current flows in the n ⁻ layer. Absent. In the p-layer just below the gate, even if the depletion layer does not reach the gate oxide film 3, no current flows because there is a pn junction in the opposite direction to the direction in which the carrier should flow. Therefore, when the gate electrode 4 has a zero potential, the source and drain are turned off.

On the other hand, as shown on pages 804 to 807 of IDM 84, even when only the conduction type is the same as that of the present invention, in the case where the single crystal Si on the support side is formed by the deep level donor impurity, However, the object of the present invention cannot be achieved. That is, as shown in FIG. 4 (a), in the n ⁻ layer to which a large number of impurities such as oxygen that form a deep level of 0.15 eV or more are added, the Fermi level is located near the center of the forbidden band. The diffusion potential formed by the junction is small. Further, since the n ⁻ layer is a large amount of impurities forming a deep level, the depletion layer does not extend,
It does not go into a pinch-off state. Also, even if the depletion layer is S
Since the impurities form a deep level even if they extend to the i end, a recombination current is generated and a large amount of leak current flows. For the above reason, the conventional example using the layer formed by the impurities forming the deep level cannot achieve the function at all.

Next, the ON state will be described. When a positive potential of the gate electrode 4 is applied, the band of single crystal Si near the gate oxide film 3 is pushed up as shown in FIG. 3B, but the region in contact with the gate oxide film 3 is p-type. Therefore, the conduction band is pushed up by the diffusion potential, and the conduction band is in a low energy state not only in the vicinity of the Si-gate oxide film interface but also over almost the entire Si layer. As a result, a carrier is generated in this low energy state region, that is, almost the entire surface of the Si layer, a wide region of the Si layer becomes a channel, and the carrier is the gate oxide film 3.
The probability of collision with is reduced, and the mobility becomes large even in the accumulation state (when the gate voltage is high). In this way, unlike the case where carriers are not concentrated in the Si layer of the number of the interfaces between the gate oxide film 3 and the single crystal Si 2 + Å, the chemical and electrical junction p Since carriers are generated in the -n junction and the entire amount of Si, the decrease in mobility due to scattering at the junction of the carriers is reduced.

In consideration in terms of reliability, in the saturation region of the I _D -V _D characteristic in the conventional structure MOSFET has reached the Si surface depletion layer is channel in the gate region on the drain side, the electric field in this region is concentrated Then the carrier is accelerated,
Electron avalanche occurs, and hot electrons (hot carrier) with large kinetic energy are generated. The photoelectrons penetrate into the gate oxide film and change the threshold voltage, which causes a problem of impairing reliability.

On the other hand, in the MOSFET structure of the present invention, as described above, since the channel is widely formed inside the Si layer, the current flowing through the region where the electric field is concentrated at the gate oxide film-Si interface is reduced and the photocarrier is reduced. .

Further, even if the photo-carriers occur, the photo-carriers generated in the region in contact with the gate oxide film 3 are small, so that the phenomenon that the photo-carriers jump into the gate oxide film 3 and the threshold voltage is changed is reduced, and the reliability is improved. Is improved.

On the other hand, a conventional example with many deep levels (IEDM84, p80
4 to p807), the effect of the present invention cannot be achieved. That is, as shown in FIG. 4 (b), the Fermi level is located near the center of the forbidden band in the n ⁻ layer formed by the impurities forming the deep level. Further, since there are many deep levels, electrons generated by the electric field are trapped in the deep levels in this region. Therefore, actually, the n ⁻ layer formed by this deep level is not affected by the electric field and only the band near the gate oxide film of the p layer is pushed up. For this reason,
As with the conventional MOSFET, carriers are generated in the Si-gate oxide film, and the effects of the present invention cannot be achieved.

As described above, according to the present invention, p is formed in the region where the gate is formed.
The formation of the -n junction facilitates the normally-off operation and prevents the carrier from colliding with the gate oxide film in the ON state.

Further, as described above, since the carriers are generated over the entire Si layer, the number of carriers flowing in the region where the electric field is concentrated is smaller than that of the conventional structure, the number of hot carriers generated is small, and the potential of the channel forming region is reduced. The rate of change decreases. Even if a photocarrier is generated in the n ⁻ layer on the substrate side, since this layer is connected to the source and drain, it is not accumulated in this layer,
The effect of turning on the parasitic bipolar, ie the kink effect, does not occur.

Example of Invention

Example 1 An example of the present invention will be described with reference to FIG. First,
As shown in (a), polycrystal Si is formed on the quartz substrate 1 in an amount of 0.
Polycrystalline Si deposited by post-melting recrystallization method after 4 μm deposition
Is crystallized. Next, as shown in (b), other single crystal Si2 is oxidized while leaving a region for forming a MOSFET. Next, P (phosphorus) is implanted at an acceleration voltage of 125 kV to have an impurity concentration of 1 to 3 × 10 ¹⁶ cells / cm ³ . Next, the gate oxide film 3 is formed to a thickness of 500 Å by an oxidation process as shown in (c), and then 1 × 10 ¹² cm ^-2 BF ₂ (boron) is ion-implanted from the gate oxide film 3 at an acceleration voltage of 75 kV. 15μ
Only m is p-type. Next, as shown in (d), the polycrystalline Si is formed and subjected to phosphorus treatment to reduce the resistance of the polycrystalline Si. Next, by using the photolithography technique, the polycrystalline Si in the gate region and the polycrystalline Si4 to be the wiring region are left, and the other polycrystalline Si is removed, and then p ions are implanted to form the source / drain regions. Next, as shown in (e), after depositing an oxide film, a hole is formed in the oxide film in the contact region to form an Al film.

After forming the wiring region 5 of this Al film by the photolithography technique, it is annealed in an atmosphere containing hydrogen.

The activation of the ion-implanted layer and the like is achieved by a thermal process of the whole process.

When the characteristics of the nMOSFET formed by the above steps were examined, the leak current was 0.1 pA / μm or less, and the field effect mobility showed a large value of 900 cm ² / V · S. The body current of the photo carrier is 10 pA / μm, which is less than 3 digits compared to the conventional device, and it was found that the photo carrier is sufficiently stronger than the conventional structure.

FIG. 6 shows the most general conventional surface channel type nMOSFET and the structure n of the present invention in which the element size and the measurement conditions are the same.
The drain currents of the MOSFETs are shown for comparison. In the conventional structure of (a), kinks are generated as described in the background of the present invention, whereas in the new structure of (b), kinks are not generated, and the drain current is twice as large as that in the conventional structure. You can see that it is flowing.

FIG. 7 shows the current distribution of the nMOSFET manufactured in Example 1. The gate oxide film thickness is 500Å, the gate width is 3.0 μm, the source-drain voltage is 5.0 V, and the source-gate voltage is 2.5 V. In the conventional structure, as shown by the curve A, 0.02 of the gate oxide film-Si interface is
The current is concentrated on the surface of the Si layer having a thickness of 0.03 μm, and in the deep depletion structure MOS, the surface layer has a width of 0.06 to 0.08 μm at the most even if it spreads a little as shown by the curve B. In the structure MOS, as shown by the curve C, the current flows on average in almost all layers of the Si layer at 0.3 to 0.4 μm from the surface. This result shows that the carriers are distributed over the entire Si layer in the MOS structure of the present invention, and the present invention is also numerically correct.

Second Embodiment Although the nMOSFET according to the present invention has been described in the first embodiment, the pMOSFET embodiment will be described here. As shown in FIG. 8 (a), the thickness on the quartz substrate 1 was changed by the same process as in Example 1.
A 0.3 μm single crystallized Si 2 layer is formed.

Next, as shown in (b), a region for forming a MOSFET is left, and Si in other regions is oxidized. Next, (boron) is applied at an accelerating voltage of 30
Ion implantation at kV and impurity concentration of 10 ¹⁶ / cm ³
And Next, as shown in (c), the gate oxide film 3 is formed to a thickness of 500 Å by an oxidation process, and then As is applied at an acceleration voltage of 25 kV for 4 times.
Ion implantation is performed only at × 10 ¹¹ cm ^-2, and contrary to the first embodiment, only about 0.1 μm from the gate oxide film 3 is made n-type. Next, as shown in (d), polycrystalline Si is formed and phosphorus treatment is performed to reduce the resistance of the polycrystalline Si. Next, by using the photolithography technique, the polycrystalline Si in the gate region and the polycrystalline Si4 to be the wiring region are left and other polycrystalline Si is removed, and then B (boron) ions are implanted to form the source / drain regions.

The subsequent steps are performed in exactly the same manner as in the example, and p shown in (e) is used.
Form MOSFET.

When the pMOSFET thus formed was evaluated in the same manner as in the example, the leakage current was sufficiently low at 0.1 pA / μm, and the field effect mobility was 300 cm ² / V · S, which was the value of the conventional pMOS.
The value was about 1.5 times higher than that of FET. We also found that it was strong enough for Hottokiya.

Embodiment 3 In Embodiment 1, an nMOSFET according to the present invention is used, and in Embodiment 2, pMO.
Described SFET. A cMOSFET can be formed by combining a part of the processes of the nMOSFET and the pMOSFET. A cross-sectional view of a cMOSFET using the present invention is shown in FIG. Regarding the device characteristics of this device, the operating speed was about 1.5 times that of the conventional device.

In the above embodiments, the embodiments using single crystal Si on the quartz substrate have been described, but it is obvious that any structure may be used as long as it is a semiconductor structure on an insulator. For example, Si on a sapphire substrate or spinel substrate or Si or Ge on a SiO ₂ or Si ₃ N ₄ film formed on the Si surface may be used. With III-V compound semiconductors and II-VI compound semiconductors as well, characteristics can be improved by using a pn junction instead of using a heterojunction in which two materials having different band gaps are stacked, unlike the conventional example. That is clear. Also,
It is obvious that the present invention can be applied even if a polycrystalline or amorphous semiconductor is used.

〔The invention's effect〕

As described above, according to the present invention, a MOSFET that operates at high speed and has high reliability can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view of a MOSFET showing the basic structure of the present invention, FIG. 2 is a sectional view showing a conventional MOSFET, and FIGS. 3 and 4 are the present invention shown in FIGS. 1 and 2, respectively. FIG. 5 is a diagram showing an energy level of a conventional example, FIG. 5 is a diagram showing an embodiment of the present invention, and FIGS. 6 (a) and 6 (b) are diagrams showing drain currents of conventional examples and MOSFETs of the present invention. FIG. 7 is a diagram showing a current distribution state of the MOSFET of the present invention, and FIGS. 8 and 9 are diagrams showing other embodiments of the present invention. 1 ... Quartz substrate, 2 ... Single crystal Si, 3 ... Gate insulating film, 4 ... Gate electrode, 5 ... Source and drain electrodes,
6 ... silica.

Claims (2)

[Claims] 1. A semiconductor device in which a MOSFET is formed in a semiconductor layer on an insulator, wherein a semiconductor layer of a conductivity type opposite to that of the channel region is provided in the channel region adjacent to the gate insulating film. A semiconductor device, wherein a depletion layer of a pn junction formed between the semiconductor layer and a channel region reaches the above-mentioned insulator when not applied. 2. The semiconductor layer according to claim 1, wherein the semiconductor layer has a valence band or conduction band edge of 0.15e.
A semiconductor device, wherein a source, a drain, a channel region and a semiconductor layer of opposite conductivity type are formed by adding an impurity that does not form a deep level of V or more.