JPH0626328B2 - Frame aligner device - Google Patents

Description

The present invention relates to a technique of configuring a frame aligner device having a large number of bits by using a frame aligner having a limited number of bits.

(Prior Art) FIG. 3 shows an example of a conventional frame aligner. 1 is a write sync signal input terminal, 2 is a write clock input terminal, 3 is a write side counter, 4 is a read sync signal input terminal, 5 is a read clock input terminal, 6 is a read side counter, 7 is a phase comparison circuit, and 8 is Frame aligner body, 9 is a data input terminal, 10 is a data output terminal, 11
Is a memory, 12 is a data delay circuit, and 13 is a selector.

A write sync signal input terminal 1 receives a sync signal indicating the phase of input data, and a write clock input terminal 2 receives a sync signal.
A clock synchronized with the input data is applied to drive the write side counter 3. On the other hand, a sync signal indicating the phase of output data is applied to the read sync signal input terminal 4, and a clock synchronized with the output data is applied to the read clock input terminal 5 to drive the read side counter 6. The phases corresponding to the input and output are compared by the phase comparison circuit 7, and the output of the comparison circuit 7 causes the frame aligner 8
To control. The frame aligner 8 comprises a memory circuit 11 capable of writing the input data 9 once at the input side timing and reading it as output data at the output side timing, a delay circuit 12 and a selector 13. That is, when the phase of the input data 9 and the phase of the output data 10 approach within a certain range, the delay amount of the input data 9 is reduced by the delay circuit 12.
And the selector 13 are used to control so that writing and reading are always executed correctly.

FIG. 4 is a time chart showing an example of the frame aligner function. The input data DATA IN arrives in 8-bit units in synchronization with the write clock WCLK. The sync signal for identifying the 8-bit phase is WSYNC. On the other hand, the output data DATA OUT is a clock RC that is faster than WCLK.
8 bits are output in burst in synchronization with LK. DATA O
The sync signal indicating the beginning of UT is RSYNC. WSYNC and RSYNC
The phase of DATA IN is arbitrary, so that DATA IN can always be converted to burst DATA OUT in 8-bit units from 1 to 8.
2 types of delay amounts are prepared, the output of either delay circuit is written in the memory, and then the data is read out as DATA OUT. In this time chart, the correspondence with Fig. 3 is that WSYNC is terminal 1, WCLK
Is terminal 2, DATA IN is terminal 9, RSYNC is terminal 4, RCLK is terminal 5, and DATA OUT is terminal 10. Of course, the same circuit can be used to perform the inverse conversion in which DATA OUT in FIG. 4 is input and DATA IN is output.

FIG. 5 is a time chart of another example of the frame aligner function. Here, DATA IN, WCLK and WSYNC are the same as in FIG. On the other hand, RCLK is a clock having the same frequency as WCLK but different phase, and RSYNC is a synchronizing signal having the same waveform as WSYNC but different phase. DATA IN synchronized with WCLK and WSYNC
Converted to DATA OUT synchronized with RSYNC in 8-bit units. According to the phase relationship between WSYNC and RSYNC, after selecting the delay amount of DATA IN and writing it in the memory, it is said that the same circuit can realize the reverse conversion such that DATA OUT is input and DATA IN is output. The points are the same as in the case of FIG.

In addition, in FIG. 4 and FIG. 5, the input data DATA IN
Are written in the memory at the falling edge of the write clock WCLK and are read from the memory at the rising edge of the read clock RCLK. The synchronization signals WSYNC and RSYNC are
It is supposed to be recognized at the falling edges of WCLK and RCLK.

The hardware for realizing the time charts of FIGS. 4 and 5 is large in scale when it is configured by a general-purpose digital IC, so that recently, an LSI is often used for commercial purposes. Although data is converted into 8-bit units in FIGS. 4 and 5, it goes without saying that the scale of the memory and the delay circuit increases as the number of unit bits to be converted increases.

(Problems to be Solved by the Invention) However, according to the above-mentioned conventional technique, when the scale of the memory and the delay circuit is increased or when the number of bits of the counter is increased, these functions are provided inside the LSI circuit. Since it often contains, it cannot be easily modified. Eventually, the circuit will be constructed again with a general-purpose digital IC, and there is a drawback that the circuit that has been made into an LSI cannot be used.

The present invention eliminates the above-mentioned drawbacks, and by using a plurality of LSIs already developed for general-purpose frame aligners, it is possible to expand the number of bits to be written in the memory by simply adding an external circuit. It relates to a circuit configuration.

(Means for Solving the Problems) According to the present invention, the frame aligner device that provides the output data by converting the speed of the input data in units of a predetermined number of bits through the memory without changing the bit order is limited. A plurality of frame aligners each having a memory having a number of bits and write / read control means for the memory; means for sequentially shifting input data to each frame aligner by a write clock, the means being connected to inputs of the plurality of frame aligners; Is connected to the output of the frame aligner and has means for multiplexing output data from each frame aligner, and is a clock having a bit rate of 1 / A (A is the number of frame aligners) of the input data,
Input data is written to the memory in each frame aligner every (A-1) bit, the contents of the memory in each frame aligner are sequentially read at a clock having a bit rate of 1 / A of the output data, and the read data is A It is configured to be multiplexed and output.

(Operation) The input data is sequentially written in the memory in each frame aligner at every (A-1) bit with a clock having a bit rate of 1 / A (A is the number of frame aligners).
The contents of the memory in each frame aligner are read sequentially with a clock having a bit rate of 1 / A of output data,
A-multiplexed and output. Therefore, even when the memory capacity (bit number) of each frame aligner is small, it can operate as if it were a large capacity frame aligner.

(Embodiment) FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which 14 is a write side timing generation circuit, 15 is a write synchronization signal applied to the frame aligner, 16 is a write clock applied to the frame aligner, and 17 is a write clock. Is a frame aligner that represents the whole of Fig. 3 in one block, and 18 is a frame aligner 17
1 is a data input terminal of 9 in FIG. 1, 19 is a write sync signal input terminal of the frame aligner 17 corresponding to 1 of FIG. 3, and 20 is a write clock input terminal of the frame aligner 17 in 2 of FIG. Correspondingly, 21 is a D flip-flop, 22 is an input data DATA IN in the D flip-flop 21 and WCLK is 1
Data delayed by a bit, 23 is the same frame aligner as 17, 24 is a data input terminal of the frame aligner 23 corresponding to 9 of FIG. 3, 25 is a write sync signal input terminal of the frame aligner 23 of FIG. 1, 26 is a write clock input terminal of the frame aligner 23, which is equivalent to 2 in FIG. 3, 27 is a read side timing generation circuit, 28 is a read synchronization signal applied to the frame aligner, and 29 is read applied to the frame aligner. Reference numeral 30 is a read sync signal input terminal of the frame aligner 17 corresponding to 4 in FIG. 3, 31 is a read clock input terminal of the frame aligner 17 corresponding to 5 in FIG. 3, and 32 is a read sync signal of the frame aligner 23. An input terminal corresponds to 4 in FIG. 3, 33 is a read clock input terminal of the frame aligner 23, 5 in FIG.
34 is a data output terminal of the frame aligner 17 and corresponds to 10 of FIG. 3, 35 is a data output of the frame aligner 1, 36 is a data output terminal of the frame aligner 23 and is equivalent to 10 of FIG. 3, 37 is Frame aligner 23 data output, 38
Is a multiplex circuit, and 39 is a multiplex control signal applied to the multiplex circuit 38.

FIG. 2 is a time chart showing the operation of the circuit of FIG. In this time chart, in the time chart of FIG. 5, DATA IN is written and read in the memory of the frame aligner in 8-bit units, whereas writing and reading is performed in 16-bit units. DATA IN
Is synchronized with the clock WCLK, and the synchronization signal WSYNC for identifying 16 bits and the clock WCLK are applied to the write side timing generation circuit 14. From the timing generation circuit 14,
A write synchronization signal 15 and a write clock 16 applied to the frame aligner are output. Write clock 16
It has a cycle twice that of WCLK. Input data DATA IN is connected to the data input terminal 18 of the frame aligner 17, the synchronization signal 15 is connected to the write synchronization signal input terminal 19, and the clock 16 is connected to the write clock input terminal 20. Further, the input data DATA IN is connected to the D input of the D flip-flop 21, shifted by 1 bit by the clock WCLK, and the data 22 appears at the Q output of the D flip-flop. Data 22
Is connected to the data input terminal 24 of the frame aligner 23. Further, the sync signal 15 is supplied to the write sync signal input terminal 25 of the frame aligner 23 and the write clock input terminal 26
A write clock 16 is applied to. In the time chart of Fig. 2, sync signal 15, clock 16 and DATA IN
As can be seen from the phase relation with the data 22 and the data 22, the even number bit of DATA IN is written in the memory in the frame aligner 17, and the odd number bit of DATA IN is written in the memory in the frame aligner 23. Be done.

Reading of these bits is performed as follows. A clock RCLK synchronized with 16-bit data to be read and a 16-bit identification synchronization signal RSYNC are applied to the read side timing generation circuit 27, and a read synchronization signal 28 and a read clock 29 are generated. The clock 29 has a cycle twice that of RCLK. These signals are read sync signal input terminal 30 and read clock input terminal of frame aligner 17.
31 and the read sync signal input terminal 32 and the read clock input terminal 33 of the frame aligner 23. Data output terminal of frame aligner 17 by these signals
Data 35 is output from 34, and data 37 is output from the data output terminal 36 of the frame aligner 23. Data 35 is DA
The even numbered bit of TA IN and the data 37 are odd numbered bits. The data 35 and the data 37 are input to the multiplexing circuit 38, and the multiplexing control signal generated from the timing generation circuit 27.
It is multiplexed at 39 and becomes DATA OUT. The multiplexing circuit 38 outputs the input 35 when the control signal 39 is at "L" level and outputs the input 37 when the control signal 39 is at "H" level.

FIGS. 1 and 2 show the case where the data to be written is twice the memory capacity in each frame aligner, but in the case of N times, the number of frame aligners is N and the input data is shifted by D. The number of flip-flops is N (N-bit shift register), the output of each D flip-flop is sequentially input to the frame aligner, and the output data multiplexing circuit is N
→ One multiplex circuit should be used. However, N is 2 ^k (k is a positive integer). Although the output data multiplexing circuit is in the selector format in the above description, it can also be in the parallel-in-serial-out shift register format. In that case, the timing given to the multiplexing circuit is RCLK and parallel data. It becomes a load signal.

Although the above description corresponds to the time chart of FIG. 5, the block diagram corresponding to the time chart of FIG. 4 is the same as that of FIG.

(Effects of the Invention) As described in detail above, the frame aligner apparatus of the present invention includes a plurality of frame aligners each having a memory having a limited number of bits and write / read control means for the memories, and a plurality of frame aligners. It has means connected to the input and sequentially shifting the input data to each frame aligner by a write clock, and means connected to the outputs of multiple frame aligners for multiplexing the output data from each frame aligner. , Input data is written to the memory in each frame aligner every (A-1) bits with a clock having a bit rate of 1 / A (A is the number of frame aligners), and 1 / A bits of output data Data read out sequentially by reading the contents of the memory in each frame aligner at the rate clock Are multiplexed and output, the number of bits of data handled by the frame aligner can be expanded only by adding a simple peripheral circuit.

That is, when the memory of the existing frame aligner has N _B bits, this frame aligner cannot be used for the data of the number of bits N _D (N _D > N _B ), but according to the present invention, By using A of this frame aligner so that A × N _B ≧ N _D and adding a simple peripheral circuit, an equivalent function can be obtained without using a new frame aligner having a large capacity memory. be able to. In particular, recently, many frame aligners are integrated into one LSI, but even when the number of bits of the memory of such an LSI is smaller than the number of bits of data to be handled,
According to the present invention, the LSI can be effectively utilized without waste.

[Brief description of drawings]

FIG. 1 is a block diagram of a frame aligner device according to the present invention, FIG. 2 is an operation time chart thereof, FIG. 3 is a block diagram of a conventional frame aligner, and FIGS. 4 and 5 are operation time charts thereof. 1 is a write sync signal input terminal, 2 is a write clock input terminal, 3 is a write side counter, 4 is a read sync signal input terminal, 5 is a read clock input terminal, 6 is a read side counter, 7 is a phase comparison circuit, and 8 is Frame aligner body, 9 is a data input terminal, 10 is a data output terminal, 11 is a memory, 12 is a data delay circuit, 13 is a selector,
14 is a write side timing generation circuit, 15 is a write synchronization signal applied to the frame aligner, 16 is a write clock applied to the frame aligner, 17 is a frame aligner expressing the whole of FIG. 3 in one block, and 18 is a frame aligner 17 Data input terminal, 19 is a frame aligner 17
Write sync signal input terminal, 20 is a frame aligner 17
Write clock input terminal, 21 is a D flip-flop, 22 is input data DATA IN in the D flip-flop 21
Data delayed by one bit of CLK, 23 is a frame aligner, 24 is a data input terminal of the frame aligner 23, 25 is a write synchronization signal input terminal of the frame aligner 23, 26 is a write clock input terminal of the frame aligner 23, and 27 is Read side timing generation circuit, 28 is a read sync signal applied to the frame aligner, 29 is a read clock applied to the frame aligner, 30 is a read sync signal input terminal of the frame aligner 17, 31 is a read clock input terminal of the frame aligner 17, 32 is a read sync signal input terminal of the frame aligner 23, 33 is a read clock input terminal of the frame aligner 23, 34 is a data output terminal of the frame aligner 17, 35 is a data output of the frame aligner 1, 36 is a data output of the frame aligner 23 Terminal, 37 is data output of frame aligner 23, 38 is multiplexed A circuit 39 is a multiplex control signal applied to the multiplex circuit 38.

Front page continuation (72) Inventor Abe Senetsu 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Kuniharu Hirose 1-7 Toranomon Minato-ku, Tokyo Oki Electric Industry Incorporated (72) Inventor Noriyuki Terada 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Japan Telegraph and Telephone Public Company

Claims (1)

[Claims] 1. A frame aligner device for providing output data by speed-converting input data in units of a predetermined number of bits without changing the bit order through a memory, and a memory having a limited number of bits and writing / reading to / from the memory. A plurality of frame aligners each having a control means, a means connected to the inputs of the plurality of frame aligners and sequentially shifting input data to each frame aligner by a write clock, and connected to the outputs of the plurality of frame aligners. Means for multiplexing the output data from each frame aligner, and
/ A (A is the number of the frame aligners) bit rate clock, the input data is written to the memory in each frame aligner every (A-1) bits, and the clock of the bit rate of 1 / A of the output data The frame aligner device is characterized in that the contents of the memory in each frame aligner are sequentially read and the read data are A-multiplexed and output.