JPH0627774B2 - Failure simulation method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure simulation method for a logic circuit.

[Background of the Invention]

The conventional failure simulation method is the first method (parallel method, deductive method, concurrent method) in which the state of the circuit of the previous test is stored using a failure list.
And the second method (SFP:
Single Fault Propagation method).

The first method is applicable to both combinational circuits and sequential circuits, but the second method is applicable only to combinational circuits.

The first method faithfully implements the failure propagation path at each time of the simulation by using the failure list.
There is a problem that a large-scale area for storing the failure list is required, and the failure list needs to be frequently added and deleted according to the change of the failure propagation state, which causes an increase in processing time.

In the second method, since each test and each fault are processed independently and the propagation path of each fault is not particularly stored, the fault list is unnecessary and the required memory amount is small. However, since the fault propagation state in the previous test is unknown, it is necessary to execute wasteful processing that overlaps with the previous test for test patterns with few signal changes, which shortens the processing time. There is a problem that you cannot do it.

[Object of the Invention]

An object of the present invention is to eliminate the above-mentioned problems and to provide a failure simulation method that enables high-speed processing with a small memory amount.

[Outline of Invention]

The number of faults detected in one test is as small as about 2 to 3% of all faults, and the simulation result requires only information on the detected faults. Therefore, if a fault that is not detected by the test can be identified at high speed, the number of target faults can be reduced, leading to higher speed.

As the identification method, the fact that "non-propagable failure is undetectable" derived from the natural law that "the manifestation of failure and propagation of failure are necessary and sufficient conditions for failure detection" is used.

Propagation prevention gate for a fault that could not be propagated in the previous test to determine the fault's non-propagation capability (propagation frontier)
Remember only the state of. As long as the state of the propagation blocking gate for this failure does not change, the failure cannot propagate beyond the propagation frontier, and the impossibility of propagation can be easily checked.

In this way, the non-propagable failure is identified at high speed, and the number of applied failures is reduced to shorten the processing time.

Example of Invention

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is an explanatory diagram showing a fault propagation state in a certain test pattern. 1 to 4 are AND gates, 5 and 6
Indicates the output ezdin pin. 21 is a fault assumed to the output pin of the AND gate 1. In the test pattern, this fault 21 is input pin 1 of AND gate 3
1 propagates to the input pin 13 of the AND gate 4, but the propagation to the output pin side is blocked because the logical values of the input pins 12, 14, 15 are "0". Therefore,
The fault 21 does not propagate to the output engine pins 5 and 6, and the fault 21 cannot be propagated.

Such impossibility of propagation is stored using the table shown in FIG. The pointer storage table 51 corresponding to the input pin is a pointer storage area having an entry corresponding to each input pin, and this pointer chains the failure number storage area. For example, the entry 31 corresponding to the input pin 11 has a pointer pointing to the failure storage area 52 that stores the failure 21, and the entry 33 corresponding to the input pin 13 also points to the failure storage area 53 that stores the failure 21. The pointer is stored. The failure-corresponding pointer storage table 61 is a pointer storage area that has an entry for each failure, and this pointer chains the input pin number storage area.

For example, a pointer pointing to an input pin storage area 62 for storing the input pin 11 is stored in the entry 41 corresponding to the failure 21, and an input pin storage area for storing the input pin 13 is stored in the input pin storage area 62. A pointer pointing to 63 is stored.

Next, a logical value storage table for checking the propagation possibility of the input pins 11 to 15 will be described.

FIG. 3 is an explanatory diagram showing a logical value storage table. 1
11 to 115 are entries for storing the logical values of the input pins 11 to 15 in the logical value storage table 100,
For example, the entry 111 stores “1” as the logical value of the input pin. Similarly, entries 112 to 1
15 has the logical values of the input pins 12 to 15,
"0", "1", "0", "0" are stored. The contents of the respective entries 111 to 115 of the logical value storage table 100 are updated when the input logical value changes.

Next, an operation example of the present invention will be described with reference to the flow chart of FIG. Each entry 11 of the logical value storage table 100
When 1 to 115 are in the above states, it is assumed that the logical value of the input pin 14 of the AND gate 4 changes from "0" to "1" in the next test pattern. At this time, the entry 114 of the logical value storage table 100 is updated from "0" to "1".

First, the input pin 13 of the AND gate whose input signal has changed
About the propagation possibility (step 21)
0,220). Since the input pin 13 cannot be propagated like the previous test and the state of the input pin 11 is unchanged,
The propagation state of the fault 21 does not change as in the previous test, and it can be easily determined that the fault 21 cannot be detected in this test.

Furthermore, it is assumed that the logical value of the input pin 15 of the AND gate 4 changes from "0" to "1" in the next test pattern. At this time, the entry 115 of the logical value storage table 100 is updated from "0" to "1". First, the input pin 13 is checked to see if it has changed to the propagation enabled state (steps 210 and 220). Since the input pin 13 has changed to the propagable state, the fault 21 stored in the fault storage area 53 chained from the entry 33 of the table 51 is restored as a propagable fault. At this time, the propagation state related to the failure 21 is removed from the pointer storage table 51 corresponding to the input pin and the pointer storage table 61 corresponding to the failure (step 230). In this way, the propagation processing is executed for all the listed faults with the possibility of propagation, and it is checked whether or not the influence of the fault propagates to the output edge (step 24).
0,250). If the propagation is impossible, the states of the propagation blocking gate (propagation frontier) are set in the tables 51 and 6.
1 is registered (step 260). Since a propagable fault does not have a propagation blocking gate, it is unconditionally targeted for a propagation trial in the next test.

As explained above, it is possible to easily check the propagation possibility of the fault in the next test by simply checking the propagation potential of the input pin of the signal change gate based on the propagation state of the fault in the previous test. Therefore, it is possible to reduce wasteful trials of fault propagation processing, and speed up can be achieved.

〔The invention's effect〕

As is clear from the above description, according to the present invention, most of the non-propagable failures can be easily identified, the number of trial failures can be significantly reduced, and the processing time for failure simulation can be shortened. .

For example, 1 in a circuit with 1000 gates and 900 failures
The number of trial failures when 40 test patterns were applied was 14K when this method was not used, but can be reduced to 3.5K by using this method.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an example of a propagation state of a failure, FIG. 2 is an explanatory diagram showing an example of a table structure for storing the propagation state and its contents, and FIG. 3 is an explanation showing a logical value storage table. FIG. 4 and FIG. 4 are flow charts showing an operation example of the present invention. 1 to 4 ... AND gates, 5, 6 ... output edge pins,
11-15 ... Input pin, 21 ... Failure, 51 ... Input pin corresponding pointer storage table, 52, 53 ... Failure storage area, 61 ... Failure corresponding pointer storage table, 62, 63 ... Input pin Storage area.

Claims (1)

[Claims] 1. When simulating a logic circuit including an assumed fault while successively inputting a test pattern using an electronic computer having a memory device, a propagation block gate for disabling output of information indicating the fault. The state is recorded in the storage device, and it is determined that a failure in which the state of the propagation blocking gate has not changed with respect to the test pattern is undetectable,
A fault simulation method characterized in that a simulation other than the fault is performed as a target of fault propagation.