JPH0627984B2 - Thin film transistor matrix array and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention uses a thin film semiconductor on an insulating substrate such as glass,
The present invention relates to a thin film transistor matrix array in which a large number of thin film transistors are provided in a matrix and a manufacturing method thereof.

[Conventional technology]

Thin film transistors (TFTs) using amorphous silicon or polycrystalline silicon can be formed at low temperature,
Since it can be formed in a large area on a transparent glass substrate, a large number of switching elements for large area photosensors and switching elements for liquid crystal display elements have been integrated and are being put to practical use in a form provided in a matrix. In addition, T using other thin film materials such as group IV elements and group IV crystals such as amorphous, microcrystalline, and polycrystalline
FT is also being made into a prototype, and a high-speed switching element is also being studied. Here, as a representative side, amorphous silicon T
A conventional example of FT will be described.

Amorphous silicon (Si) TFTs are often used mainly in liquid crystal display devices. For example, as described in Japanese Patent Application No. 58-191866 (Japanese Patent Laid-Open No. 60-083373), a gate, a gate insulating film, a semiconductor layer, and a drain / source are sequentially laminated on a substrate. Reverse staggered structure T
FT matrix arrays are commonly used. A similar structure will be described in detail by schematically showing its cross section in FIG.

A gate electrode 403 is provided on a substrate 401 such as glass, and a gate insulating film 404, a semiconductor layer 405, and a semiconductor contact layer are further provided.
After the metal of 411, the drain electrode 407, and the source electrode 409 is formed, it is provided as a part of the TFT left on the island. After that, the ITO that will become the pixel pad 410
A conductive film 413 is formed and a TFT channel 415 is formed together with the patterning of the pixel pad 410. In addition, a passivation film 412 is generally provided on the entire surface. Using such a TFT matrix array, as is well known, other necessary elements such as a counter substrate are combined to form a liquid crystal display element.

[Problems to be solved by the invention]

However, the liquid crystal display device using the TFT matrix array produced by the above-described conventional structure and manufacturing method has many places where no display can be obtained (display defects) and the quality is remarkably poor.

The cause was caused by disassembling the display element and examining the TFT matrix array with an electron microscope to examine the defective portion in detail. As shown in FIG. 4, the source electrode 409 and the pixel pad
It was found to be caused by poor connection with 410. ITO conductive film 41 forming pixel pad 410
3 is that it is difficult to obtain a thick film, and the step of the semiconductor layer 405 due to the TFT island is caused by the end surface 414 of the TFT island.
This is due to the problem of disconnection of the wiring.

As a method to prevent display defects due to disconnection as described above,
A method for reducing the unevenness of the drain bus line has been proposed as described in the specification of Japanese Patent Application No. 60-163359 of the present applicant. It was left.

It is an object of the present invention to provide a thin film matrix array having a structure for preventing the wiring of an inverted staggered TFT matrix array from being broken at a step due to a laminated film of thin films, and a manufacturing method thereof.

[Means for solving problems]

According to a first aspect of the present invention, in a thin film transistor matrix array having an inverted staggered structure in which at least a gate, a gate insulating film, a semiconductor layer, and a drain / source are sequentially stacked on a substrate, a step between a stacked source electrode and a pixel pad is small. As described above, an insulating film having a thickness substantially equal to the thickness of the semiconductor layer is buried in a portion where the semiconductor layer is not provided in the matrix array region.

According to a second aspect of the present invention, at least a gate, a gate insulating film, a semiconductor layer, and a drain source are sequentially stacked on a substrate,
In a method of manufacturing a thin film transistor matrix array having an inverted staggered structure, a step of forming an island and a thin film channel portion of the semiconductor layer, and a step of providing an insulating film having a thickness substantially equal to the thickness of the semiconductor layer on the entire surface of the matrix array region. By providing a negative resist, exposing from the back surface of the substrate using the island as a mask, and exposing again from the main surface of the substrate using a negative mask having a pattern wider than the thin film transistor channel portion, and developing the drain / source of the thin film transistor. The method includes the steps of providing a resist pattern with exposed regions, removing the exposed insulating film on the drain / source regions, and removing the negative resist, and then providing a conductive film to form pixel pads. I am trying.

[Action]

In the TFT matrix array of the present invention, an insulating film having a thickness substantially equal to the thickness of the semiconductor layer is buried in the concave portion at a portion other than the island of the semiconductor layer, so that a planar step between the source electrode and the pixel pad is formed. It can be made extremely slight. As a result, the disconnection between the source and the pixel is about to occur, and defects such as disconnection due to the wiring can be eliminated.

Further, in the method of manufacturing a TFT matrix array of the present invention, after forming the island and the TFT channel portion of the semiconductor layer, an insulating film having a thickness substantially equal to the thickness of the semiconductor layer is provided on the entire matrix array region, and a negative resist is used. Since the patterning is performed by the double-sided exposure, the insulating film can be left in the area other than the island in a buried state and can also serve as the passivation film of the TFT channel portion.

By these actions, the TFT matrix array can be formed without any defect, and the display defect of the liquid crystal display element can be eliminated.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a perspective view schematically showing a cross section and an upper surface of a part of the TFT matrix array shown for explaining one embodiment of the TFT matrix array of the present invention.

According to this structure of the TFT matrix array, the gate electrode 103 connected to the gate bus line 102 is provided by Cr metal on the substrate 101 such as glass, the gate insulating film 104 of SiN _x , the semiconductor layer 105 of amorphous Si. After the formation of the n ⁺ semiconductor contact layer 111, the TFT portion is provided leaving an island shape. After the TFT channel portion is formed, SiN _x is formed, and the buried insulating film 106 is provided in the recesses other than the island in a thickness substantially the same as the thickness of the amorphous Si semiconductor layer 105. A pixel pad 110 formed of ITO is provided on the buried insulating film 106,
After that, the drain electrode 107 connected to the drain bus line 108 and the source electrode connected to the pixel pad 110
109 and are formed of Cr metal. In the figure, 112 is a passivation film.

According to the structure of this embodiment, there is almost no planar step between the source and the pixel, and the cause of the step break in the wiring can be eliminated.

FIG. 2 shows T of a TFT matrix array shown for explaining another embodiment of the TFT matrix array of the present invention.
It is sectional drawing of a FT part.

2A shows the case where the buried insulating film 206 is provided with the same thickness as the semiconductor layer 205, and FIG. 2B shows the buried insulating film 20.
6 is provided in the total thickness of the semiconductor layer 205 and the semiconductor contact layer 211, and FIG. 2 (c) is shown in FIG. 2 (a),
Different from (b), the buried insulating film 206 is provided on the passivation film 212 of the TFT.

In FIGS. 2A, 2B, and 2C, 201 is a substrate such as glass, 203 is a gate electrode, 204 is a gate insulating film, 207 is a drain electrode, 209 is a source electrode, and 210 is a pixel pad. Is.

Next, one embodiment of the manufacturing method of the present invention will be described with reference to FIG. FIG. 3 shows a part of T of the TFT matrix array.
It is sectional drawing of a FT part, and is shown in order of a process.

In FIG. 3A, the gate electrode is formed on the glass substrate 301.
303 and gate bus line (not shown) are made of Cr metal 10
Form with 00Å. SiN is formed on this by plasma CVD
_x 2000 gate insulating film 304, and amorphous Si semiconductor layer
305 to 3000Å and n ⁺ amorphous Si contact layer 311
Form with 500 Å. Then, as shown in FIG. 3B, the semiconductor layer 305 and the contact layer 31 are formed on the portion to be the TFT.
An island is formed by etching, leaving 1. Further, the TFT channel portion 315 is dug and removed by etching. Thereafter, as shown in FIG. 3C, SiN _x having the same thickness as the semiconductor layer 305 is formed as a buried insulating film 306 by plasma CVD. Thereafter, as shown in FIG. 3D, a negative resist 316 is provided, and the back surface of the substrate is exposed by using the island of the semiconductor layer 305 as a mask. In the figure, 317 indicates the direction of the back exposure light.

Further, using a negative mask having a pattern wider than that of the TFT channel portion 315, the substrate main surface is exposed again and developed,
A negative resist pattern in which the drain / source regions of T are opened is formed. In the figure, 318 indicates the direction of light for exposure on the principal surface. Then, the buried insulating film 306 on the exposed drain / source regions is removed, and the negative resist 316 is removed as shown in FIG. After that,
As shown in FIG. 3 (f), the drain electrode 307 and the source are formed into 1000 liters of Cr metal to serve as the electrode 309. The drain electrode 307 is formed together with a drain bus line (not shown), and the source electrode 309 is formed so as to be connected to the pixel pad. Finally, the passivation film 312 and the light shielding film 319 are formed.

According to the manufacturing method of the above-described embodiment, not only a planar step is not formed between the source electrode and the pixel pad, but also the buried insulating film 306 can serve as passivation of the TFT channel portion 315.

The present invention is not limited to the above embodiment.
It goes without saying that the material, thickness, etc. can be variously changed within the scope of the present invention.

〔The invention's effect〕

As described above, according to the present invention, it is possible to eliminate disconnection of wiring due to a step between the source pixel and the pixel. Also,
The buried insulating film can also serve as the passivation film of the TFT. From these, the yield of defect-free elements of the TFT matrix array can be greatly improved.

[Brief description of drawings]

FIG. 1 is a perspective view schematically showing a cross section and an upper surface of a part of a TFT matrix array for explaining an embodiment of a TFT matrix array of the present invention, and FIG. 2 is another TFT matrix array of the present invention. TFT of a matrix array for explaining an embodiment
FIG. 3 is a sectional view of a TFT portion showing the order of steps of a TFT matrix array for explaining an embodiment of a manufacturing method of the present invention. FIG. 4 is a sectional view of a TFT portion of a conventional TFT matrix array. FIG. 101,201,301,401 ...... Substrate 102 ...... Gate bus line 103,203,303,403 ...... Gate electrode 104,204,304,404 …… Gate insulating film 105,205,305,405 …… Semiconductor layer 106,206,306 …… Filled insulating film 107,207,307,407 …… Drain electrode 108 …… Drain bus line 109,209,309,409 …… Source electrode 110,210,310,410… … Pixel pad 111,211,311,411 …… Contact layer 112,212,312,412 …… Passivation film 413 …… Conductive film 414 …… TFT island end face 315,415 …… TFT channel part 316 …… Negative resist 319 …… Shading film

Claims (2)

[Claims] 1. In a thin film transistor matrix array having an inverted staggered structure in which at least a gate, a gate insulating film, a semiconductor layer, and a drain / source are sequentially stacked on a substrate, a step between a stacked source electrode and a pixel pad is small. As described above, the thin film transistor matrix array, wherein an insulating film having a thickness substantially equal to the thickness of the semiconductor layer is buried in a place where the semiconductor layer is not provided in the matrix array region. 2. A method of manufacturing a thin film transistor matrix array having an inverted staggered structure, in which at least a gate, a gate insulating film, a semiconductor layer, and a drain source are sequentially laminated on a substrate, and the island of the semiconductor layer and the thin film channel portion are formed. A step of forming, an step of providing an insulating film having a thickness substantially equal to the thickness of the semiconductor layer on the entire surface of the matrix array region, a step of providing a negative resist, and exposing from the back surface of the substrate by using the island as a mask, and the thin film transistor channel portion. By exposing again from the main surface of the substrate using a negative mask having a wider pattern and developing, a step of forming a resist pattern in which the drain / source regions of the thin film transistor are exposed, and removing the insulating film on the exposed drain / source regions And the negative resist A method of manufacturing a thin film transistor matrix array, comprising the step of providing a conductive film after removing the pixel pad.