JPH0628263B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a high breakdown voltage bipolar integrated circuit having at least a two-layer epitaxial layer structure.

[Conventional technology]

Conventionally, in a bipolar integrated circuit (hereinafter referred to as an IC), for example, in order to realize a high breakdown voltage of a vertical transistor in which a base diffusion layer and an emitter diffusion layer are sequentially formed in an epitaxial layer which is an NPN transistor, the following measures are taken. It has been subjected.

(1) Increase the depth of the diffusion layer (hereinafter referred to as xj).

(2) Increase the resistivity of the epitaxial layer (hereinafter referred to as sepi).

(3) Increase the epitaxial layer thickness (hereinafter referred to as tepi).

With respect to (1), for example, the depth xj of the base diffusion layer is made deeper, the electric field concentration on the surface or the side surface portion due to the curvature of the base diffusion layer is alleviated, and the breakdown voltage is improved. With respect to (2), the depletion layer extending from the base-collector junction to the epitaxial layer side is expanded to relax the electric field concentration on the surface, the side surface, or the bottom surface to improve the breakdown voltage.
Regarding (3), the depletion layer extending from the base-collector junction to the epitaxial layer side does not reach the high-concentration layer, for example, the high-concentration buried layer, and reach through to prevent the breakdown voltage from decreasing.
It is intended to improve the breakdown voltage.

As described above, in the vertical transistor, the base-collector breakdown voltage (hereinafter referred to as BV _CBO ) and the emitter-collector breakdown voltage (hereinafter referred to as BV _CEO ) can be improved. However, in a high voltage IC having a BV _{CEO of} about 200 V, a two-layer epitaxial layer structure as shown in FIG. 3 is used. FIG. 4 shows the impurity concentration profile in the AA ′ sectional view of FIG. That is, P
After the P-type second buried layer 3 and the N-type first buried layer 2 are provided on the mold substrate 1 and the N-type first epitaxial layer 4 is provided, the P-type second epitaxial layer 4 is provided on the N-type first epitaxial layer 4. Provide a third buried layer 5, N
After the second type epitaxial layer 6a is provided, the P-type isolation region 10 is provided and a large number of island regions are provided in the first and second epitaxial layers 4 and 6a, and P is added to the second epitaxial layer 6a. The high voltage transistor is obtained by sequentially forming the type base region 8, the N type emitter region 9a, and the N type collector contact region 9b.

Generally, the high breakdown voltage transistor having a two-layer epitaxial layer structure has the following characteristics: (I) A heat treatment time for insulation separation is short.

(II) Due to (I), the increase in device size can be relatively small.

(III) Low breakdown voltage device (eg MOS transistor,
I ² L etc.) is possible.

and so on.

[Problems to be solved by the invention]

However, in the case of a high withstand voltage IC of BV _{CEO of} about 200 V, the resistivity of the epitaxial layer becomes a fairly high resistivity of about 30 Ωcm, so that P can be easily doped by boron from the P-type buried layer during epitaxial layer growth. ^- a phenomenon that reverses to the type was often happened. Generally, in high voltage IC,
Since the thickness of the epitaxial layer is thicker SiCl ₄ and a source is used a large growth rate, the epitaxial growth by SiCl ₄ source for the growth temperature is carried out at a high temperature of about 1170 ° C., the auto-doping is promoted There is.
When this phenomenon occurs especially in the boundary region between the first epitaxial layer and the second epitaxial layer, the current amplification factor (hereinafter referred to as h _FE ) of the NPN transistor is reduced and the collector saturation voltage (hereinafter referred to as V _CECsai ). ) Caused a rise. Even if the P ⁻ type inversion layer is not reached, the boundary region between the first epitaxial layer, the second layer, and the epitaxial layer becomes an N ⁻ type high resistance layer, which causes deterioration of similar device characteristics. It was FIG. 5 shows the impurity concentration profile of the cross-sectional view taken along the line AA ′ in FIG. 3 when the P ⁻ type inversion layer or the N ⁻ type high specific resistance layer is formed.

The present invention is devised to solve such a problem, and in a bipolar high breakdown voltage IC having at least two epitaxial layers, an inversion layer is formed in a boundary region between one epitaxial layer and the other epitaxial layer. _Another object of the present invention is to provide a method for manufacturing a semiconductor device, which prevents generation of a high resistance layer and prevents a decrease in h _{FE and} an increase in V _{CE (sat)} .

[Means for solving problems]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first buried layer of another conductivity type and a second buried layer of one conductivity type from a surface of a semiconductor substrate of one conductivity type, and then a method of forming a second buried layer of one conductivity type. Forming a first epitaxial layer, then forming at least the third buried layer of one conductivity type from the surface of the first epitaxial layer, and then forming a second epitaxial layer of another conductivity type In the method of manufacturing a semiconductor device, the first epitaxial layer is formed of a SiCl ₄ source, and the second epitaxial layer is formed of a SiH ₄ source. At this time, desirably, the specific resistance of the second epitaxial layer is smaller than the specific resistance of the first epitaxial layer.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

1 (a) to 1 (c) are structural sectional views showing an embodiment of the present invention. First, as shown in FIG. 1 (a), the N ⁺ type first buried layer 2 is formed from the surface of the P ⁻ type substrate 1 by diffusion of, for example, Sb or As, and then, for insulation isolation by diffusion of, for example, BCl _3. Of the P-type second buried layer 3 is formed on the substrate 1 including the first and second buried layers 2 and 3, and Sepi 25 to 35 Ωcm,
A tepi 20-25 μm N ⁻ type first epitaxial layer 4 is grown. At this time, the first epitaxial layer 4 is grown by a reduction reaction of SiCl ₄ at about 1170 ° C. Next, as shown in FIG. 3B, a P-type third buried layer 5 for insulation separation is formed by diffusion of BCl ₃ from the surface of the first epitaxial layer 4.
Then, an N ⁻ -type second epitaxial layer 6b is grown on the first epitaxial layer 4 including the second buried layer 3. By growing the second epitaxial layer 6b by thermal decomposition of SiH ₄ at about 1050 ° C., the autodoping of boron is reduced as compared with SiCl ₄ grown at high temperature. Therefore, the first
Tepi 20 to 25μ with a resistivity similar to that of the epitaxial layer 4
m to grow. Thereafter, the P-type isolation region 10 is diffused to form the first and second epitaxial layers 4, 6
b is separated into island regions, and a P-type base region 8, an N-type emitter region 9a, and an N-type collector contact region 9b are formed to obtain a transistor.

2 (a), (b), and (c) show another embodiment of the present invention, in which the first epitaxial layer 4 is formed in the step of FIG. After the P-type third buried layer 5 is formed in the step (b), the Sepi 1 to 20 having lower resistance than the first epitaxial layer 4 are formed.
A tepi 5-10 Ωμm second epitaxial layer 6a is grown in Ωcm. At this time, the second epitaxial layer 6a has a thickness that covers the P-type third buried layer 5. Next, as shown in FIG. 2 (c), N of Sepi 25 to 35 Ωcm is formed by an appropriate vapor phase growth method.
^{A −} type third epitaxial layer 7 is grown with a tepi of 10 to 15 μm. After that, a P-type isolation region 10, a P-type base 8, an N-type emitter region 9a and an N-type collector contact region 9b are formed to form a transistor as shown in FIG. 1 (c). At this time, since the second epitaxial layer 6a has a high concentration, autodoping can be more completely prevented and a transistor is formed in the third epitaxial layer 7, so that the transistor characteristics do not change.

〔The invention's effect〕

As described above, according to the present invention, since the second epitaxial layer is grown by the thermal decomposition of SiH ₄ , the growth temperature is 1050 ° C., which is lower than that of SiCl ₄ , so that the boron of the third buried layer is volatile. Auto-doping is reduced, and it is possible to prevent the formation of an inversion layer or a high resistance layer in the boundary region between the first epitaxial layer and the second epitaxial layer. Further, if the second epitaxial layer is made to have a high concentration, this autodoping can be completely prevented.

Therefore, an extremely high diffusion yield can be realized without lowering h _FE of the NPN transistor and raising V _CE (sat).

The present invention is not limited to the above embodiment, and the same effect can be obtained even if the polarity is changed.

[Brief description of drawings]

1 (a) to 1 (c) are structural cross-sectional views showing a manufacturing process for explaining an embodiment of the present invention, and FIGS. 2 (a) to 2 (c) are other embodiments of the present invention. Sectional views showing the manufacturing process for
FIG. 3 shows a conventional NP having a two-layer epitaxial layer structure.
Structural cross-sectional view of N-transistor, FIG. 4 is A- in FIG.
The impurity concentration profile of the A ′ cross section, FIG. 5 shows AA ′ of FIG. 3 when an inversion layer or a high resistivity layer is formed in the boundary region between the first epitaxial layer and the second epitaxial layer.
It is an impurity concentration profile of a cross section. 1 ... P type substrate, 2 ... N ⁺ type first buried layer, 3 ... P type second buried layer, 4 ... N type first epitaxial layer, 5 ...
P-type third buried layer, 6a, 6b ... N ^- type second epitaxial layer, 7 ... N ^- type third epitaxial layer, 8 ... P
Type base region, 9a ... N type emitter region, 9b ... N
Type collector contact region, 10 ... P type isolation region, P
...... P ^- -type inversion layer, q ...... N ^- -type high resistivity layer.

Claims (3)

[Claims] 1. A step of forming a first buried layer of another conductivity type and a second buried layer of one conductivity type from a surface of a semiconductor substrate of one conductivity type, and thereafter, a first epitaxial layer of the other conductivity type. A step of forming a layer by a reduction reaction of SiCl4, and thereafter forming a third buried layer of one conductivity type in a portion corresponding to the second buried layer from the surface of the first epitaxial layer; Vapor-depositing the second epitaxial layer of another conductivity type by a thermal decomposition method;
The method further comprises the steps of subjecting an upper epitaxial layer including an epitaxial layer to insulation isolation diffusion reaching the third buried layer, and forming a semiconductor element in the upper epitaxial layer surrounded by the insulation isolation diffusion. Manufacturing method of semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the specific resistance of the second epitaxial layer is smaller than the specific resistance of the first epitaxial layer. 3. The third epitaxial layer of one conductivity type is formed on the second epitaxial layer to form the upper epitaxial layer.
The method for manufacturing a semiconductor device according to item (1) or (2).