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JPH0628391B2 - Noise elimination circuit - Google Patents
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JPH0628391B2 - Noise elimination circuit - Google Patents

Noise elimination circuit

Info

Publication number
JPH0628391B2
JPH0628391B2 JP59175114A JP17511484A JPH0628391B2 JP H0628391 B2 JPH0628391 B2 JP H0628391B2 JP 59175114 A JP59175114 A JP 59175114A JP 17511484 A JP17511484 A JP 17511484A JP H0628391 B2 JPH0628391 B2 JP H0628391B2
Authority
JP
Japan
Prior art keywords
circuit
signal
noise
waveform
video signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP59175114A
Other languages
Japanese (ja)
Other versions
JPS6153878A (en
Inventor
隆人 成田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP59175114A priority Critical patent/JPH0628391B2/en
Publication of JPS6153878A publication Critical patent/JPS6153878A/en
Publication of JPH0628391B2 publication Critical patent/JPH0628391B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/14Picture signal circuitry for video frequency region
    • H04N5/21Circuitry for suppressing or minimising disturbance, e.g. moiré or halo

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Picture Signal Circuits (AREA)
  • Television Signal Processing For Recording (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、映像信号からフィルタを介して比較的高い
周波数成分を取り出した後、所定のレベル以上の信号を
制限し、前記映像信号と逆相で加算してこの映像信号か
ら雑音を除去するときに利用されている雑音除去回路に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention extracts a relatively high frequency component from a video signal through a filter and then limits a signal of a predetermined level or higher to reverse the video signal. The present invention relates to a noise removing circuit used when removing noise from this video signal by adding in phases.

〔従来の技術〕[Conventional technology]

映像信号を記録,および再生するときの雑音除去方式と
しては、まず記録側で第2図(a),(b)に示すよう
にハイパスフィルタFとリミッタ回路Lによって映
像信号の高域成分を抽出した波形Sを形成し、もとの
映像信号の波形Sと加算回路Aによって加算するこ
とにより高域成分が強調された波形Sを記録する。
As a noise removing method for recording and reproducing a video signal, first, as shown in FIGS. 2 (a) and 2 (b), a high-pass component F 1 and a limiter circuit L 1 of the video signal on the recording side are used. forming a waveform S 2 was extracted, recording the waveform S 3 to a high-frequency component is emphasized by adding the waveform S 1 of the original video signal by adder circuit a 1.

そして、再生側では、第3図(a),(b)に示すよう
に再生されたノイズを含む映像信号の波形Sをハイパ
スフィルタF、リミッタ回路Lによってノイズ成分
を含む高域成分の波形Sを形成し、イコライザE
介してレベル調整したのち、前記波形Sを遅延回路D
によって所定時間遅らせて位相を合わせ、加算回路A
において両者を逆相で加算してノイズ成分が除去され
た波形Sを得る技術が知られている。
Then, on the reproducing side, as shown in FIGS. 3A and 3B, the waveform S 4 of the reproduced video signal containing noise is converted into a high-pass component including a noise component by the high-pass filter F 2 and the limiter circuit L 2 . Waveform S 5 is formed and the level is adjusted through the equalizer E 1, and then the waveform S 4 is added to the delay circuit D 5.
1 to delay the predetermined time to match the phases, and adder circuit A
In 2 there is known a technique of adding both in opposite phases to obtain a waveform S 6 from which a noise component is removed.

このような雑音除去方式は、例えば特開昭55−567
75号公報にもみられるように映像信号の雑音除去方式
として公知の技術手段であるが、記録・再生にわたって
映像信号が2回ハイパスフィルタを通過しているため、
波形Sにみられるように2重微分されたエラーノイズ
HHSが残るという問題がある。
Such a noise removing method is disclosed in, for example, Japanese Patent Laid-Open No. 55-567.
As disclosed in Japanese Patent Laid-Open No. 75-75, it is a known technical means as a noise elimination method for a video signal. However, since the video signal passes through the high pass filter twice during recording and reproduction,
There is a problem that the error noise HHS 1 which is double differentiated remains as seen in the waveform S 6 .

この2重微分のエラーノイズHHSはかなり小さいレ
ベルのノイズであるが、このようなノイズもダビングを
繰り返すと無視できないような画質の劣化として問題と
なる。
This double differential error noise HHS 1 is a noise of a very small level, but such noise also poses a problem as image quality deterioration that cannot be ignored when dubbing is repeated.

第4図(a)は、かかる2重微分形のエラーノイズHH
Sも除去できるように提案された再生側の雑音除去回路
を示したもので、その動作を以下に数式的に説明する。
FIG. 4 (a) shows such double differential type error noise HH.
A noise eliminating circuit on the reproducing side proposed so that S can be eliminated is also shown, and its operation will be mathematically described below.

まず、第2図(a)の記録側に設けられているハイパス
フィルタFの信号回路の伝達関数と、第3図(a),
第4図(a)のハイパスフィルタF,Fの信号回路
の伝達関数をそれぞれ等価な値Hで表わすと、第2図
(a)においては、 S=HS=S+S=S+HS の信号が得られている。
First, the transfer function of the signal circuit of the high-pass filter F 1 provided on the recording side of FIG. 2 (a) and FIG. 3 (a),
When the transfer functions of the signal circuits of the high-pass filters F 2 and F 3 of FIG. 4 (a) are represented by equivalent values H, S 2 = HS 1 S 3 = S 1 + S in FIG. 2 (a). The signal of 2 = S 1 + HS 1 is obtained.

波形Sの信号が記録されたのち、再生されるとノイズ
成分nが付加されるので、 S=S+n=S+HS+n となる。
When the signal of the waveform S 3 is recorded and then reproduced, the noise component n is added, so that S 4 = S 3 + n = S 1 + HS 1 + n.

第3図(a)の従来例では S=HS=H(S+HS+n) S=S−S =S+HS+n −H(S+HS+n) =S+n(1−H)+HHS =S+HHS となって、前述したようにHHSなる2重微分のエラ
ーノイズが残る。
Figure 3 (a) in the conventional example S 5 = HS 4 = H ( S 1 + HS 1 + n) S 6 = S 4 -S 5 = S 1 + HS 1 + n -H (S 1 + HS 1 + n) = S 1 + N (1−H) + HHS 1 = S 1 + HHS 1 and the double differential error noise of HHS 1 remains as described above.

(なお、ノイズ成分nにはリミッタがかけられるためH
≒nとみることができる) ところで、第4図(a)の雑音除去回路では第4図
(b)の波形図に示すように S=S−S =S+HS+n−HS =S+HS+n −H(S+HS+n−HS) =S+n(1−H)−HHS+HHS n(1−H)≒0とすることができるから、 S(1−HH)=S(1−HH) より、S=Sとなり、ノイズ成分nが除去できる。
(Note that the noise component n is limited by H
It can be regarded as n ≒ n) Incidentally, in the noise reduction circuit of FIG. 4 (a) is 4 (as shown in the waveform diagram of b) S 8 = S 4 -S 7 = S 1 + HS 1 + n- Since it is possible to make HS 8 = S 1 + HS 1 + n −H (S 1 + HS 1 + n −HS 8 ) = S 1 + n (1-H) −HHS 1 + HHS 8 n (1-H) ≈0, S than 8 (1-HH) = S 1 (1-HH), becomes S 1 = S 8, the noise component n can be removed.

しかし、この雑音除去回路はハイパスフィルタF,リ
ミッタ回路Lから得られる遅延された波形Sの信号
と、波形Sの信号位相を合わせることが不可能であ
る。
However, this noise removing circuit cannot match the signal phase of the delayed waveform S 7 obtained from the high pass filter F 3 and the limiter circuit L 3 with the signal phase of the waveform S 4 .

したがって、現実の回路では波形Sにみられるように
雑音が除去された信号を得ることは困難でありキャンセ
ル効果は低いものとならざるを得ない。
Therefore, in an actual circuit, it is difficult to obtain a signal from which noise is removed as seen in the waveform S 8 , and the canceling effect is unavoidable.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

この発明の雑音除去回路は上記の点にかんがみてなされ
たもので、2重微分によるエラーノイズを現実の回路で
も除去できるようにしようとするものである。
The noise elimination circuit of the present invention is made in view of the above points, and is intended to eliminate the error noise due to double differentiation even in an actual circuit.

〔問題点を解決するための手段〕[Means for solving problems]

第1図(a)は、この発明の実施例を示すブロック図
で、A,Aは逆相の加算回路、Fはハイパスフィ
ルタ、Lはリミッタ回路、Eはイコライザ、D
遅延回路を示す。
FIG. 1 (a) is a block diagram showing an embodiment of the present invention. A 4 and A 5 are anti-phase adder circuits, F 4 is a high pass filter, L 4 is a limiter circuit, E 4 is an equalizer, and D 4 is Indicates a delay circuit.

なお、RV,RVはレベル調整用の可変抵抗器であ
る。
In addition, RV 1 and RV 2 are variable resistors for level adjustment.

〔作用〕[Action]

以下、この回路の動作を第1図(b)の波形図とともに
説明する。
The operation of this circuit will be described below with reference to the waveform chart of FIG.

端子Tから入力された再生映像信号の波形Sはノイ
ズ成分nを含み、前述したように S=S+S+n ハイパスフィルタFを通る回路の伝達関数をHとする
と加算回路Aの出力は S=S−S10 また、 S10=HS =H(S−S10) =H(S+S+n−S10) S10=H{(S+S+n) −H(S+S+n−S10)} =HS+HS+Hn−HHS −HH(S+n−S10) HS=S,Hn=nであるから、 S10=S+n−HH(S+n−S10) ∴(1−HH)S10 =(1−HH)(S+n) S10=S+n 一方、加算回路Aでは S11=S−S′10(但し、S′10=S10) =S+S+n−(S+n) =S したがって、記録時の映像信号の波形Sと同様にノイ
ズ成分nを除去した映像信号が抽出できる。
The waveform S 4 of the reproduced video signal input from the terminal T 1 contains the noise component n, and as described above, assuming that the transfer function of the circuit passing through S 4 = S 1 + S 2 + n high-pass filter F 4 is H, the adder circuit A The output of 4 is S 9 = S 4 −S 10 and S 10 = HS 9 = H (S 4 −S 10 ) = H (S 1 + S 2 + n−S 10 ) S 10 = H {(S 1 + S 2 + n) -H (S 1 + S 2 + n-S 10)} = HS 1 + HS 2 + Hn-HHS 1 -HH ( since it is S 2 + n-S 10) HS 1 = S 2, Hn = n, S 10 = S 2 + n-HH (S 2 + n-S 10 ) ∴ (1-HH) S 10 = (1-HH) (S 2 + n) S 10 = S 2 + n On the other hand, in the addition circuit A 5 , S 11 = S 4 -S '10 (where, S' 10 = S 10) = S 1 + S 2 + n- (S 2 + n) = S 1 Therefore, Video signal to remove the same noise component n and the waveform S 1 of the recording time of the video signal can be extracted.

なお、実際に加算回路Aで演算される信号は遅延回路
を通過した信号(S′)とイコライザEによっ
て周波数特性を改善した信号(S′10)とすることがで
きるので、信号処理による遅れ、波形歪を遅延回路
,イコライザEで補正することができる。
The signal actually calculated by the adder circuit A 5 can be a signal (S 4 ′) that has passed through the delay circuit D 4 and a signal (S ′ 10 ) whose frequency characteristic has been improved by the equalizer E 4 . Delay and waveform distortion due to signal processing can be corrected by the delay circuit D 4 and the equalizer E 4 .

〔発明の効果〕 以上説明したように、この発明の雑音除去回路(ノイズ
キャンセラ)は記録−再生系のハイパスフィルタを含む
信号変換回路で発生する2重微分形のエラーノイズを効
果的に取り除くことができるという効果がある。
[Effect of the Invention] As described above, the noise removing circuit (noise canceller) of the present invention can effectively remove the double differential type error noise generated in the signal conversion circuit including the high-pass filter of the recording-reproducing system. The effect is that you can do it.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)、(b)はこの発明の雑音除去回路のブロ
ック図とその波形図、第2図(a)、(b)は映像信号
の高域周波数を強調する回路図とその波形図、第3図
(a)、(b)は再生された映像信号からノイズ成分を
除去する一般的な回路図とその波形図、第4図(a)、
(b)は二重微分形のエラーノイズも除去できるように
した雑音除去回路のブロック図である。 図中、F、F、F、Fはハイパスフィルタ、L
、L、L、Lはリミッタ回路、Dは遅延回
路、Eはイコライザ、A、Aは加算回路を示す。
1 (a) and 1 (b) are block diagrams and waveform diagrams of the noise elimination circuit of the present invention, and FIGS. 2 (a) and 2 (b) are circuit diagrams and waveforms thereof for emphasizing a high frequency of a video signal. FIGS. 3 (a) and 3 (b) are a general circuit diagram for removing a noise component from a reproduced video signal and its waveform diagram, FIG. 4 (a),
FIG. 6B is a block diagram of a noise removing circuit that can remove double differential type error noise. In the figure, F 1 , F 2 , F 3 , and F 4 are high-pass filters, L
1 , L 2 , L 3 , and L 4 are limiter circuits, D 4 is a delay circuit, E 4 is an equalizer, and A 4 and A 5 are adder circuits.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】再生映像信号が入力される入力端子と、 前記再生映像信号の高域周波数成分を抽出するハイパス
フィルタおよびリミッタ回路からなる信号変換回路と、 上記入力端子から供給されている再生映像信号から上記
信号変換回路の出力を減算し、その減算出力を上記信号
変換回路の入力側に供給する第1の減算回路と、 上記再生映像信号から上記信号変換回路の出力を減算
し、雑音が除去された出力信号を得る第2の減算回路を
備えていることを特徴とする雑音除去回路。
An input terminal to which a reproduced video signal is input, a signal conversion circuit including a high-pass filter and a limiter circuit for extracting a high frequency component of the reproduced video signal, and a reproduced video supplied from the input terminal. The output of the signal conversion circuit is subtracted from the signal, the subtraction output is supplied to the input side of the signal conversion circuit, and the output of the signal conversion circuit is subtracted from the reproduced video signal. A noise removal circuit comprising a second subtraction circuit for obtaining a removed output signal.
JP59175114A 1984-08-24 1984-08-24 Noise elimination circuit Expired - Fee Related JPH0628391B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59175114A JPH0628391B2 (en) 1984-08-24 1984-08-24 Noise elimination circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59175114A JPH0628391B2 (en) 1984-08-24 1984-08-24 Noise elimination circuit

Publications (2)

Publication Number Publication Date
JPS6153878A JPS6153878A (en) 1986-03-17
JPH0628391B2 true JPH0628391B2 (en) 1994-04-13

Family

ID=15990515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59175114A Expired - Fee Related JPH0628391B2 (en) 1984-08-24 1984-08-24 Noise elimination circuit

Country Status (1)

Country Link
JP (1) JPH0628391B2 (en)

Also Published As

Publication number Publication date
JPS6153878A (en) 1986-03-17

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