JPH0628422B2 - Video signal processing circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit, and particularly to improving visual performance in a video display device in which a response speed of a liquid crystal display (LCD) monitor is slow and an afterimage is prominent. The present invention relates to a video signal processing circuit.

(Prior Art) Even in the case of a video display device that does not display a moving image such as a display device (display monitor) of a computer terminal, it is preferable that the response speed (response time) is fast (short).

In the case of the above display monitor, a response time of about 40 ms / frame is practically required, and in the case of a television receiver for displaying a moving image, 20 ms / frame is used in order to avoid image unnaturalness. Less than or equal is required.

Further, the liquid crystal material used as a display element needs to satisfy various conditions such as an operating temperature range, orientation, stability and electro-optical characteristics. In an actual liquid crystal display device, some liquid crystal materials are mixed and used, and so far, it is 40 to 60
The response time is about ms, which seems to be no visual problem.

Furthermore, in the TN-FE type matrix liquid crystal display element,
The drive method shortens the response time.

The amount of transmitted light of each pixel of the TN-FE type matrix liquid crystal display element does not change so much by one voltage application, but changes in a form in which the effects of pulse voltages applied one after another for each frame are accumulated. Therefore, even though the response time of the individual pixels on each scan electrode is somewhat longer, the electro-optic response over the entire frame is observed to be sufficiently short, showing essentially a frame following response. Since the entire image changes like a fade in / out, there is an advantage that the human eye does not feel much discomfort with respect to the response time.

However, such a response also includes the effect of a bias pulse train, and has a drawback of so-called crisp image quality. The bias voltage pulse becomes background noise and reduces the contrast ratio of the image.

Further, in order to further increase the number of display lines of the matrix liquid crystal display device, development of a smectic C-type matrix liquid crystal display device (memory type matrix liquid crystal display device) using a memory effect is also active.

In a general memory type matrix liquid crystal display device, the contents are rewritten one by one from the upper scanning electrode to the lower scanning electrode, and new information is fixed to the entire frame by one scanning. The frame follow-up time is a value obtained by multiplying the response time of pixels arranged on each scan electrode by the number of scan electrodes. For example, in a smectic C-type matrix liquid crystal display device including 1000 rows of scanning electrodes, in order to display 20 ms / frame, the scanning time of each scanning electrode must be 20 μs or less [Journal of the Television Society of Japan, Vol.42. , N
o.1 (1988); Special feature "LCD devices and their application to TV"
(By Eiji Kaneko)].

(Problems to be Solved by the Invention) As described above, the material itself of the LCD is improved or L
The response speed (response time) of the LCD is made faster (shorter) by the method of supplying the drive pulse for driving the CD, but when the LCD is applied to a video display device such as a television monitor or a projector, it is still sufficient. However, the afterimage caused by the low response speed of the LCD has been a serious problem in performance.

Therefore, the present invention solves the problems of the above-mentioned conventional techniques,
An object of the present invention is to provide a video signal processing circuit which has a slow response speed and reduces an afterimage in a video display device in which an afterimage is conspicuous and which improves visual performance.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a first amplifier having a gain of “2” to which an input video signal is supplied and an input signal for one frame (or one field). A frame memory (or field memory) that stores and outputs only for a period, a second amplifier having a gain “α” (0 <α <1) to which an output signal of the frame memory (or field memory) is supplied, and this second amplifier A cyclic circuit composed of an adder circuit for adding the output signal of the second amplifier and the input video signal to supply to the frame memory (or field memory); and the cyclic circuit based on the output signal of the first amplifier. A video signal processing circuit comprising a subtraction circuit for subtracting the output signal of the addition circuit of the circuit and outputting it as an output video signal is further provided. De) period only a frame memory for storing and outputting (or field memory), an output gain signal is supplied in this frame memory (or field memory) is "α" (0 <α <
1) A recursive circuit configured by a first amplifier and an adder circuit that adds an output signal of the first amplifier and an input video signal and supplies the sum to the frame memory (or field memory); A second amplifier having a gain of "1/2" to which the output signal of the adding circuit of the circuit is supplied, and a subtraction circuit for subtracting the output signal of the second amplifier from the input video signal and outputting it as an output video signal And a video signal processing circuit including the following.

(Embodiment) The present invention does not solve the problem of the response speed of the LCD by improving the material of the LCD or supplying the driving pulse as in the related art, but tries to display on the video display device (LCD). It is intended to solve the above-mentioned problem of response speed by processing a video signal.

An embodiment of the video signal processing circuit according to the present invention will be described below.

FIG. 1 is a block diagram showing an embodiment of a video signal processing circuit according to the present invention.

In the figure, a video signal (input video signal) is supplied to the input terminal 1. This input video signal has a gain of "2"
It is supplied to one input terminal of each of the (double) amplifier 2 and the adder circuit 3. Then, the output signal of the amplifier 2 is supplied to one input terminal of the subtraction circuit 4.

On the other hand, the frame memory 5 stores the input signal only for one frame period, and substantially outputs the input signal with a delay of one frame period. The output signal of the frame memory 5 is supplied to the amplifier 6 having a gain of "α" (α times) [0 <α <1]. Further, the output signal of the amplifier 6 is supplied to the other input terminal of the adding circuit 3.

The adder circuit 3 adds the input video signal from the input terminal 1 and the output signal of the amplifier 6 and supplies the added output signal to the frame memory 5 and the other input terminal of the subtraction circuit 4.
That is, in the adder circuit 3, the input video signal and its 1
A signal (afterimage simulation signal) obtained by multiplying the input video signal before the frame by α is added.

The cyclic circuit of the frame memory 5 → amplifier 6 → adder circuit 3 constitutes an afterimage simulation circuit. The portion A in the figure (that is, the output end of the adder circuit 3)
At, a signal is obtained which is the sum of the afterimage simulation signal and the input video signal, the amount of which is determined by the value of the gain α of the amplifier 6.

Then, the subtraction circuit 4 subtracts the “signal of the sum of the afterimage simulation signal and the input video signal” obtained in the portion A from the “signal obtained by doubling the input video signal” output from the amplifier 2, The output signal of the subtraction circuit 4 is output as an output video signal via the output terminal 7.

The processing in the subtraction circuit 4 is expressed as follows.

[Input video signal] × 2-([Input video signal] + [Afterimage simulation signal]) = [Input video signal] − [Afterimage simulation signal] (= [Output video signal]) When the output video signal obtained by processing by the video signal processing circuit is input to a video display device such as an LCD whose response speed is slow and afterimage is prominent,
By appropriately selecting the value of the gain α of the amplifier 6, as is apparent from the following processing equation, the above-mentioned image display device (L
Afterimage (afterimage signal) due to a CD or the like can be reduced.

[Output video signal] + [Afterimage signal] = [Input video signal]-[Afterimage simulation signal] +
[Afterimage signal] ≈ [input video signal] Here, the operation of the video signal processing circuit of FIG.
This will be described with reference to the waveform chart of FIG.

Considering the behavior in the unprocessed state, b at present in FIG.
When a video signal such as
When the signal waveform before (field) is as shown in Fig. 2a,
Since the image display device (display) using the LCD has an afterimage, the image signal (monitor) having a fast response speed is displayed on the image display device (monitor) with a current signal and one frame (or one field) before as shown in FIG. Signal (this is the afterimage)
It is equivalent to inputting a signal obtained by combining (adding) and.

Therefore, in the present invention, a signal obtained by multiplying the signal of a (the afterimage signal of one frame before) by α in the frame memory 5 and the amplifier 6 in the circuit of FIG. 1 [the signal of d (afterimage of FIG. 2 Simulation signal)], and the adder circuit 3 creates a signal (a sum signal of the afterimage simulation signal and the input video signal) similar to c in FIG. 2 described above.

Further, by subtracting the signal c in FIG. 2 from the output signal [signal e in FIG. 2] of the amplifier 2 in the subtraction circuit 4, a signal (output video signal) such as f in FIG. 2 is obtained. can get.

When the output video signal f in FIG. 2 is input to a video display device (display) using an LCD, the missing portion of the signal arrow f in FIG. 2 is a video display device (display) using an LCD. The above-mentioned signal (a) (a signal of the afterimage of one frame before) in (2) can be canceled and the afterimage can be reduced.

FIG. 3 is a block diagram showing another embodiment of the video signal processing circuit according to the present invention.

In this embodiment, instead of the amplifier 2 in the embodiment shown in FIG. 1 above, an amplifier 8 having a gain of "1/2" (1/2 times) is provided on the other input side of the subtraction circuit 4. Provided,
An amplifier 9 having a gain of “2” (twice) is provided on the output terminal side of the subtraction circuit 4. Others are the same as the circuit of FIG.

With the above configuration, the output signal of the adder circuit 3 forming the afterimage simulation circuit (recursive circuit) is set to 1 by the amplifier 8.
It is multiplied by / 2 and then supplied to the other input terminal of the subtraction circuit 4. Then, in the subtraction circuit 4, the "signal obtained by multiplying the sum of the afterimage simulation signal and the input video signal by 1/2" is subtracted from the "input video signal" from the input terminal 1, and the output of the subtraction circuit 4 is further subtracted. The signal is doubled by the amplifier 9 and then output as an output video signal via the output terminal 7.

The above processing is expressed by the following equation.

{[Input video signal]-([input video signal] + [afterimage simulation signal]) × (1/2)} × 2 = [input video signal] − [afterimage simulation signal] (= [output video signal]) In this way, an output video signal similar to the circuit of the embodiment of FIG. 1 can be obtained. If this output video signal is input to a video display device such as an LCD whose response speed is slow and an afterimage is conspicuous as described above, the above video display device (LC
It is possible to reduce the afterimage (afterimage signal) due to (D etc.).

Here, in the embodiment of FIG. 3, the amplifier 9 doubles the output signal of the subtraction circuit 4 and then outputs it as the output video signal. However, without the amplifier 9, the output signal of the subtraction circuit 4 is not provided. Even if is output as the output video signal as it is, the effect of reducing the afterimage can be obtained similarly to the above, and therefore the amplifier 9 may be provided as necessary.

It should be noted that, instead of the frame memory 5 in each of the above-described embodiments, a field memory that stores an input signal for only one field period and substantially delays the input signal by one field period and then outputs the same is used. it can.

Also, the video signal processed by the present invention is input,
The image display device capable of reducing the afterimage is not limited to the image display device using the LCD, and it is needless to say that the image display device can be applied to other image display devices using the display element having a slow response speed.

(Effects of the Invention) As described above, the video signal processed by the video signal processing circuit of the present invention may be input to a video display device such as a liquid crystal display (LCD) monitor whose response speed is slow and an afterimage is noticeable. As a result, afterimages in the above video display device can be reduced,
It has the feature that the visual performance can be greatly improved.

[Brief description of drawings]

1 and 3 are block diagrams showing respective embodiments of the video signal processing circuit according to the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the present invention. 1 ... input terminal, 2,6,8,9 ... amplifier, 3 ... adding circuit, 4 ... subtraction circuit, 5 ... frame memory, 7 ...
… Output terminal.

Claims (2)

[Claims] 1. A first amplifier having a gain of "2" to which an input video signal is supplied, a frame memory (or field memory) for storing and outputting the input signal for one frame (or one field) period, and The gain to which the output signal of the frame memory (or field memory) is supplied is “α” (0 <α <
A cyclic circuit composed of a second amplifier of 1) and an adder circuit for adding the output signal of the second amplifier and the input video signal and supplying the sum to the frame memory (or field memory); A video signal processing circuit comprising a subtraction circuit for subtracting the output signal of the adder circuit of the cyclic circuit from the output signal of the amplifier No. 1 and outputting it as an output video signal. 2. A frame memory (or field memory) for storing and outputting an input signal for one frame (or one field) period, and a gain to which an output signal of this frame memory (or field memory) is supplied is "α".
A recursive circuit composed of a first amplifier (0 <α <1) and an adder circuit for adding an output signal of the first amplifier and an input video signal and supplying the result to the frame memory (or field memory). A second amplifier having a gain of "1/2" to which the output signal of the adder circuit of the cyclic circuit is supplied; and an output video signal obtained by subtracting the output signal of the second amplifier from the input video signal. A video signal processing circuit consisting of a subtraction circuit for outputting as.