Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPH06296068A - Method of forming circuit pattern - Google Patents
[go: Go Back, main page]

JPH06296068A - Method of forming circuit pattern - Google Patents

Method of forming circuit pattern

Info

Publication number
JPH06296068A
JPH06296068A JP8207893A JP8207893A JPH06296068A JP H06296068 A JPH06296068 A JP H06296068A JP 8207893 A JP8207893 A JP 8207893A JP 8207893 A JP8207893 A JP 8207893A JP H06296068 A JPH06296068 A JP H06296068A
Authority
JP
Japan
Prior art keywords
region
plating
resist
substrate
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP8207893A
Other languages
Japanese (ja)
Inventor
Susumu Miyabe
進 宮部
Nobuo Saito
伸郎 斎藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Chemical Industry Co Ltd
Original Assignee
Asahi Chemical Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Chemical Industry Co Ltd filed Critical Asahi Chemical Industry Co Ltd
Priority to JP8207893A priority Critical patent/JPH06296068A/en
Publication of JPH06296068A publication Critical patent/JPH06296068A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Manufacturing Of Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To protect a conductor region against a short circuit caused by a plating layer formed after etching by a method wherein a plating metal foil layer formed on a resist is removed by etching. CONSTITUTION:A first plating metal foil layer 8 unnecessarily formed on a third region or a resist 5 is removed by etching with etchant. An etching operation is carried out so far as to remove plating metal from the surface of the third region 5 or till the surface of a first region metal adjacent to the third region 5 is lower than the surface of the third region resist 5, and it is preferable that the depth of the recessed surface is smaller than the thickness of the resist film 5 located there. By this setup, the conductor region 4 can be protected against a short circuit caused by a plating layer formed after etching.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、精密印刷回路基板など
に施すパターンメッキ法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern plating method applied to a precision printed circuit board or the like.

【0002】[0002]

【従来の技術】従来から精密な印刷回路基板を作る場合
フォトリソグラフィがよく用いられてきたが、特にアデ
ィティブ法を用いることによって高密度配線回路基板が
でき、かなり有利な製造法であるとされてきた。その製
造法を図面を用いて説明すると、その工程は次のとおり
である。 (a)導電性の基板7上にフォトリソグラフィでレジス
ト層5による微細パターンを形成する(図4)。 (b)さらにこの微細パターン上にメッキを行なう。こ
のメッキを行なった後(図5)、メッキされた面を内側
にして絶縁基板の両面にはりつける。 (c)次に基板を溶解して取り除き、さらにメッキを行
なうことでレジスト層の上下にメッキ層を形成する(図
6)。
2. Description of the Related Art Conventionally, photolithography has been often used for producing a precise printed circuit board, but it is said that a high density wiring circuit board can be formed by using the additive method, which is a considerably advantageous manufacturing method. It was The manufacturing method will be described below with reference to the drawings. (A) A fine pattern of the resist layer 5 is formed on the conductive substrate 7 by photolithography (FIG. 4). (B) Further, plating is performed on this fine pattern. After this plating is performed (FIG. 5), the plated surface is placed on the inside of the insulating substrate. (C) Next, the substrate is dissolved and removed, and further plating is performed to form plating layers above and below the resist layer (FIG. 6).

【0003】[0003]

【発明が解決しようとする課題】ところが基板とレジス
トが密着していない部分が存在すると、一回目のメッキ
時にレジスト基板間にメッキが回り込み金属の析出が起
きてしまう。また一般にメッキで銅を成長させる前に銅
以外の金属を析出させる処理が行なわれるが、この処理
によってもレジストと基板間に前処理液が浸食し、レジ
スト層と基板間に金属層が形成される。このためその後
の一回目メッキによりやはり同様に金属層上に銅が析出
する。
However, if there is a portion where the substrate and the resist are not in close contact with each other, the plating wraps between the resist substrates during the first plating, and metal deposition occurs. Further, generally, a process of depositing a metal other than copper is performed before growing copper by plating, but this process also erodes the pretreatment liquid between the resist and the substrate, forming a metal layer between the resist layer and the substrate. It Therefore, copper is similarly deposited on the metal layer by the first plating thereafter.

【0004】そのいずれの場合も図3に示す析出部分8
から基板溶解後の二回目のメッキが開始してしまい、形
成すべき微細パターンがレジスト上で短絡してしまう問
題があった(図6)。
In either case, the deposited portion 8 shown in FIG.
Therefore, there was a problem that the second plating started after the substrate was melted and the fine pattern to be formed was short-circuited on the resist (FIG. 6).

【0005】[0005]

【課題を解決するための手段】上記課題を解決するため
に、導体回路パターンを形成する基板において、基板表
面に形成された金属である第一領域と、不導体部分で形
成された第二領域と金属箔層が表面に形成されその下に
第二領域と同一の不導体部分が存在する第三領域があ
り、エッチングにより少なくとも第三領域上の該金属箔
層を除去した後にメッキを行うことを特徴とする回路パ
ターン形成方法を提供するものである。
In order to solve the above problems, in a substrate on which a conductor circuit pattern is formed, a first region which is a metal formed on the surface of the substrate and a second region which is formed of a non-conductor portion And a metal foil layer is formed on the surface, and there is a third region below which the same non-conductive portion as the second region exists, and plating is performed after removing the metal foil layer on at least the third region by etching. And a circuit pattern forming method characterized by the above.

【0006】まず、レジストパターンを形成する基板
は、メッキで形成する金属とは溶解溶液に対する溶解速
度が異なっていることが好ましく、基板は両性金属であ
ることが望ましい。メッキする金属としては銅がよく用
いられる。レジストパターンが形成された基板に対し、
一般にメッキで銅を成長させる前に銅以外の金属を析出
させる処理が行なわれる。特に基板がアルミのとき基板
への銅メッキ層の密着力を強化するため、いわゆるジン
ケート処理により亜鉛層を形成するのが好ましい。その
後一回目のメッキを行い、そのメッキ面を内側にして絶
縁基板の両側に接着するかメッキ面に絶縁塗料を塗布後
接着材で張り合わせる。次に基板をメッキ金属は溶かさ
ないが基板を溶かせる液で溶解する。基板がアルミで導
体層が銅の場合には、塩酸等を用いて基板を除去すると
良い。
First, the substrate on which the resist pattern is formed preferably has a dissolution rate different from that of the metal formed by plating in a dissolution solution, and the substrate is preferably an amphoteric metal. Copper is often used as the plating metal. For the substrate on which the resist pattern is formed,
Generally, a process of depositing a metal other than copper is performed before the copper is grown by plating. Particularly when the substrate is aluminum, it is preferable to form the zinc layer by so-called zincate treatment in order to enhance the adhesion of the copper plating layer to the substrate. After that, the first plating is performed, and the plated surface is placed on the inside to adhere to both sides of the insulating substrate, or the plated surface is coated with an insulating paint and then adhered with an adhesive. Next, the substrate is dissolved with a solution that does not dissolve the plating metal but the substrate. When the substrate is aluminum and the conductor layer is copper, the substrate may be removed using hydrochloric acid or the like.

【0007】ここで本願の発明により第三領域、つまり
レジスト上に形成されてしまった一回目のメッキ金属箔
層8をその金属をエッチング可能な液でエッチング除去
する。エッチング量はその第三領域の表面にメッキ金属
がなくなるまで行えば良く(図1)更にその第一領域の
第三領域に隣接する金属表面がその第三領域のレジスト
表面により凹になるまでで、かつその部分のレジスト膜
厚より深くならない程度がより良い(図2)。
Here, according to the invention of the present application, the third region, that is, the first plating metal foil layer 8 formed on the resist is removed by etching with a liquid capable of etching the metal. The amount of etching may be performed until the plating metal is removed from the surface of the third region (FIG. 1), and until the metal surface adjacent to the third region of the first region becomes concave due to the resist surface of the third region. Moreover, it is better that the thickness is not deeper than the resist film thickness in that portion (FIG. 2).

【0008】なぜなら第一領域の二回目メッキ開始面が
第三領域のレジスト表面より凹なら二回目のメッキによ
る導体の形成はそのレジスト端面により制限されパター
ン横方向のショートが防止できる。但し凹がレジスト膜
厚より深くまでエッチングして形成されるとオーバーハ
ングしたレジスト層が崩れ、そこからメッキが成長し、
かえってパターン横方向のショートが発生しやすくな
る。
Because if the second plating start surface of the first region is concave from the resist surface of the third region, the formation of the conductor by the second plating is limited by the resist end face and the short circuit in the lateral direction of the pattern can be prevented. However, if the recess is formed by etching to a depth deeper than the resist film thickness, the overhanging resist layer collapses and plating grows from there.
On the contrary, a short circuit in the lateral direction of the pattern is likely to occur.

【0009】ここで更に第一領域の第三領域との境界か
ら離れた中央部ではその境界部の高さより高く、その第
一領域内での端部と中央部の高さの差は1μm、好まし
くは2μm以上が好ましい。第一領域の中央部が第三領
域つまりレジスト端部に接している第一領域の境界部よ
り高いと二回目のメッキ膜厚を大きくしても第一領域か
ら第三、第二領域に向かう横方向のメッキ成長が小さく
なりパターン横方向のショートをより効果的に防止でき
る。その防止効果は第一領域の中央部と端部(第三領域
との境界)の膜厚差が大きいほど強い。一方この膜厚差
は通常20μmを越えることは無い。
Here, in the central portion further away from the boundary between the first area and the third area, the height is higher than the height of the boundary portion, and the difference in height between the end portion and the central portion in the first area is 1 μm, It is preferably 2 μm or more. If the center of the first region is higher than the boundary of the third region, that is, the boundary of the first region in contact with the resist edge, even if the second plating thickness is increased, the first region moves toward the third and second regions. Lateral plating growth is reduced, and short circuit in the lateral direction of the pattern can be prevented more effectively. The prevention effect is stronger as the film thickness difference between the central portion and the end portion (boundary between the third region) of the first region is larger. On the other hand, this film thickness difference usually does not exceed 20 μm.

【0010】なおこのエッチング処理ではメッキ金属を
エッチングできる液ならばなんでもよいがメッキ金属が
銅の場合、10〜200g/1濃度の過硫酸アンモニュ
ウム(APS)を用いると、さきに述べた第一領域の中
央部が第三領域つまりレジスト端部に接している第一領
域の境界部より高い形状になりより好ましい。またジン
ケート処理によるアルミ表面から深さ方向の侵食深さは
1μm、好ましくは2μm以上が好ましい。
In this etching treatment, any liquid can be used as long as it can etch the plating metal, but when the plating metal is copper, ammonium persulfate (APS) having a concentration of 10 to 200 g / 1 is used, and the first region described above is used. It is more preferable that the central part has a higher shape than the boundary part of the third region, that is, the first region in contact with the resist end. Further, the erosion depth from the aluminum surface in the depth direction by the zincate treatment is 1 μm, preferably 2 μm or more.

【0011】本願の処理を行い2回目のメッキを終了し
た好ましい状態を図7に示す。
FIG. 7 shows a preferred state in which the processing of the present application has been performed and the second plating has been completed.

【0012】[0012]

【実施例1】本願の実施例の一例を工程を追って説明す
る。 厚みが80μmのアルミ基板のうえに東京応化工業
(株)製ネガ型フォトレジスト「OMR83」を塗布
し、プリベークした。このときレジスト膜厚は平均10
μmとなった。次にPETフィルム製のフォトマスクを
のせ回路パターンを露光した。更に現像液で現像し、リ
ンスでリンスし、最後にアフターベークしレジストの回
路パターンが形成された導電性基板を得た。 回路パターンが形成された導電性基板を酸で洗浄後、
奥野製薬工業(株)のジンケート処理液「サブスターZ
N−2」を使いジンケート処理した。この処理によりア
ルミ基板のジンケート処理深さは約2μmであった。
[Embodiment 1] An example of an embodiment of the present application will be described step by step. A negative photoresist “OMR83” manufactured by Tokyo Ohka Kogyo Co., Ltd. was applied onto an aluminum substrate having a thickness of 80 μm and prebaked. At this time, the resist film thickness is 10 on average.
became μm. Next, a photomask made of PET film was placed on the circuit pattern to expose it. Further, it was developed with a developing solution, rinsed with rinse, and finally afterbaked to obtain a conductive substrate on which a resist circuit pattern was formed. After cleaning the conductive substrate with the circuit pattern formed with acid,
Okuno Chemical Industries Co., Ltd. zincate treatment liquid "Substar Z
N-2 "was used for zincate treatment. By this treatment, the zincate treatment depth of the aluminum substrate was about 2 μm.

【0013】なお全ての処理において水洗を行った。 株式会社ムラタ製ピロリン酸銅メッキ液を用いて、基
板を陰極とし銅を1μm厚に電解メッキした。 CuSO4 ・5H2 O 110g/1、H2 SO4
80g/1、塩素イオン50ppmで光沢剤を添加した
硫酸銅メッキ液を使い60μm厚に電解メッキした。 形成されたメッキ面に日立化成製絶縁ワニス「WI−
640」でオーバーコートし、セメダイン社製「SG−
EPO EP−007」エポキシ樹脂系接着剤を用いて
メッキ面を内側にして接着した。 14%塩酸水溶液でアルミ基板を溶解除去した。 100g/1の過硫酸アンモニュウム水溶液で25
℃、30秒間エッチングした。 二回目の電解銅メッキを工程と同じ条件で行った。 以上の処理により、400mm×400mmの基板30
枚を製造したが、30枚のいずれの基板においてもパタ
ーン間のショート箇所はなかった。
Washing with water was carried out in all the treatments. Using a copper pyrophosphate plating solution manufactured by Murata Co., Ltd., copper was electrolytically plated to a thickness of 1 μm using the substrate as a cathode. CuSO 4 · 5H 2 O 110g / 1, H 2 SO 4 1
Electrolytic plating was performed to a thickness of 60 μm using a copper sulfate plating solution in which a brightening agent was added at 80 g / 1 and chlorine ion of 50 ppm. Hitachi Chemical Insulation Varnish "WI-"
640 ”is overcoated and made by Cemedine's“ SG-
EPO EP-007 "epoxy resin adhesive was used to bond with the plated surface inside. The aluminum substrate was dissolved and removed with a 14% hydrochloric acid aqueous solution. 25 with 100 g / 1 ammonium persulfate aqueous solution
Etched at 30 ° C. for 30 seconds. The second electrolytic copper plating was performed under the same conditions as the process. By the above processing, the substrate 30 of 400 mm × 400 mm
Although 30 substrates were manufactured, there was no short-circuited portion between the patterns on any of the 30 substrates.

【0014】なお工程の過硫酸アンモニュウム水溶液
でエッチング後一枚の基板の一部から10×10mmの
サンプルを切り出し樹脂に包埋し断面をとって観察した
ところ、導体パターンの境界部のレジストの表面からの
高さは10箇所の平均で1.5μmであり導体パターン
の中央と境界部の高さの差は0.5μmであった。二回
目のメッキが厚みで60μmに成長する間にパターン横
方向の成長は43μmであった。
After etching with an aqueous solution of ammonium persulfate in the step, a 10 × 10 mm sample was cut out from a part of one substrate, embedded in resin, and observed by observing a cross section. The average height from 10 points was 1.5 μm, and the difference in height between the center and the boundary of the conductor pattern was 0.5 μm. The lateral pattern growth was 43 μm while the second plating was grown to a thickness of 60 μm.

【0015】[0015]

【実施例2】工程のジンケート処理時間を増やし工程
の過硫酸アンモニュウムによるエッチング時間を延長
した以外は実施例1と同じ処理を行った。結果は表1に
示すようにショートも無く、かつメッキのパターン横方
向の成長も35μmであった。
Example 2 The same process as in Example 1 was performed except that the zincate treatment time in the step was increased and the etching time with ammonium persulfate in the step was extended. As a result, as shown in Table 1, there was no short circuit, and the lateral growth of the plating pattern was 35 μm.

【0016】[0016]

【実施例3】工程のジンケート処理時間を増やし工程
の過硫酸アンモニュウムによるエッチング時間を延長
した以外は実施例1と同じ処理を行った。結果は表1に
示すようにショートも無く、かつメッキのパターン横方
向の成長も30μmであった。
Example 3 The same process as in Example 1 was carried out except that the zincate treatment time in the step was increased and the etching time with ammonium persulfate in the step was extended. As a result, as shown in Table 1, there was no short circuit, and the lateral growth of the plating pattern was 30 μm.

【0017】[0017]

【比較例】実施例の工程から工程まで行った後、工
程をせずに工程を行い400mm×400mmの基
板30枚を製造したが、そのうち20枚の基板にパター
ン間のショート箇所が発見された。しかも内5枚は基板
のほぼ全面にショート箇所が発見された。
[Comparative Example] 30 steps of 400 mm × 400 mm substrates were manufactured by performing the steps from the step to the step of the example without performing steps, and a short-circuited portion between patterns was found on 20 of the boards. . Moreover, in 5 of them, short circuits were found on almost the entire surface of the substrate.

【0018】なおの工程の前に一枚の基板の一部から
10×10mmのサンプルを切り出し樹脂に包埋し断面
をとって観察したところ、レジストパターンの上に導体
が析出しており導体パターンの中央部も境界部もレジス
ト面から平均3μm高くなっていた。
Before the above step, a 10 × 10 mm sample was cut out from a part of one substrate, embedded in resin, and a cross section was observed. As a result, a conductor was found to have been deposited on the resist pattern. Both the central portion and the boundary portion of the above were higher than the resist surface by 3 μm on average.

【0019】[0019]

【表1】 [Table 1]

【0020】[0020]

【発明の効果】本発明は導体回路パターンを形成する基
板において基板表面に形成された金属である第一領域
と、不導体部分で形成された第二領域により形成されて
おり、基板の表面をエッチングした後にメッキを行うこ
とを特徴とする回路パターン形成方法により、エッチン
グ後形成されるメッキによる導体領域の短絡を防止でき
ショートのない微細回路パターンの形成が可能となっ
た。
EFFECT OF THE INVENTION The present invention comprises a first region, which is a metal formed on the surface of a substrate on which a conductor circuit pattern is formed, and a second region, which is formed of a non-conductor portion, and By the circuit pattern forming method characterized by performing plating after etching, it is possible to prevent a short circuit of a conductor region due to plating formed after etching and to form a fine circuit pattern without a short circuit.

【図面の簡単な説明】[Brief description of drawings]

【図1】本願を実施した途中状態の一例である。FIG. 1 is an example of a state in the middle of carrying out the present application.

【図2】更に本願を実施した途中の更に好ましい形態の
一例である。
FIG. 2 is an example of a more preferable mode in the middle of carrying out the present application.

【図3】基板を除去した直後の状態であり、第3領域3
においては表面に第1領域1と同一の金属箔層8が残留
している。
FIG. 3 is a state immediately after removing the substrate, and shows a third region 3
In, the same metal foil layer 8 as the first region 1 remains on the surface.

【図4】基板上にレジストパターンが形成された状態。FIG. 4 shows a state where a resist pattern is formed on a substrate.

【図5】一回目のメッキをした直後でありレジスト(第
2領域)の下に金属箔層8が形成されている。
[FIG. 5] Immediately after the first plating, the metal foil layer 8 is formed under the resist (second region).

【図6】従来の技術により二回目のメッキをした直後で
あり、金属箔層8のため二回目のメッキでパターン間で
ショートが発生している。
[FIG. 6] Immediately after the second plating is performed by the conventional technique, a short circuit occurs between the patterns in the second plating due to the metal foil layer 8.

【図7】本願を実施した一例でありパターン間のショー
トが発生しない。
FIG. 7 is an example of implementing the present application, in which a short circuit between patterns does not occur.

【符号の説明】[Explanation of symbols]

1 第一領域 金属部分 2 第二領域 不導体部分 3 第三領域 表面に1と同一の金属箔層が残留してい
る部分 4 1回目のメッキにより形成された金属部分 4′2回目のメッキにより形成された金属部分 5 レジスト 6 導体回路パターンを張り付けている絶縁体 7 基板 8 第三領域上の金属箔層部分
1 first area metal part 2 second area non-conductor part 3 third area part where the same metal foil layer as 1 remains on the surface 4 metal part formed by the first plating 4'by the second plating Formed metal part 5 Resist 6 Insulator to which conductor circuit pattern is attached 7 Substrate 8 Metal foil layer part on the third region

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 導体回路パターンを形成する基板におい
て、基板表面に形成された金属である第一領域と、不導
体部分で形成された第二領域と、金属箔層が表面に形成
され、その下に第二領域と同一の不導体部分が存在する
第三領域があり、エッチングにより少なくとも第三領域
上の該金属箔層を除去した後にメッキを行うことを特徴
とする回路パターン形成方法。
1. A substrate on which a conductor circuit pattern is formed, wherein a metal first region formed on the substrate surface, a second region formed of a non-conductor portion, and a metal foil layer are formed on the surface. A circuit pattern forming method, characterized in that there is a third region below which the same non-conductor portion as the second region exists, and plating is performed after removing at least the metal foil layer on the third region by etching.
JP8207893A 1993-04-08 1993-04-08 Method of forming circuit pattern Withdrawn JPH06296068A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8207893A JPH06296068A (en) 1993-04-08 1993-04-08 Method of forming circuit pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8207893A JPH06296068A (en) 1993-04-08 1993-04-08 Method of forming circuit pattern

Publications (1)

Publication Number Publication Date
JPH06296068A true JPH06296068A (en) 1994-10-21

Family

ID=13764434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8207893A Withdrawn JPH06296068A (en) 1993-04-08 1993-04-08 Method of forming circuit pattern

Country Status (1)

Country Link
JP (1) JPH06296068A (en)

Similar Documents

Publication Publication Date Title
JP3594894B2 (en) Via filling plating method
US4943346A (en) Method for manufacturing printed circuit boards
US4705592A (en) Process for producing printed circuits
JP2009260216A (en) Method for manufacturing wiring board
JP4195706B2 (en) Printed wiring board and manufacturing method thereof
KR20140091689A (en) Aqueous composition for etching of copper and copper alloys
US4540464A (en) Method of renewing defective copper conductors on the external planes of multilayer circuit boards
JPH06196846A (en) Forming of copper circuit pattern on ceramic substrate
JPH06296068A (en) Method of forming circuit pattern
JPH05251852A (en) Printed-circuit board and its manufacture
US6003225A (en) Fabrication of aluminum-backed printed wiring boards with plated holes therein
US5207867A (en) Composition and method for improving the surface insulation resistance of a printed circuit
JP2624068B2 (en) Manufacturing method of printed wiring board
JP2011181640A (en) Method of forming wiring conductor
JPH08148810A (en) Manufacture of printed wiring board
JPH06334311A (en) Circuit body manufacturing method
JP2004140085A (en) Circuit board and method of manufacturing the same
JPH01188700A (en) Formation of high-density pattern
JP4720521B2 (en) Flexible wiring board and manufacturing method thereof
JPH0779060A (en) Wiring pattern forming method and resist removing apparatus
KR100677938B1 (en) Manufacturing method of double sided wiring board and double sided wiring board
JPH05347468A (en) Manufacture of printed circuit board
JPH11284316A (en) Method of forming conductor pattern on wiring board
JPH1022612A (en) Manufacture of printed wiring board
JPS6014453A (en) Forming method of metallic layer pattern

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20000704