JPH0630084B2 - Memory circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a memory circuit, and more particularly to a memory circuit such as a main memory or an external memory of a computer and a high speed processor.

(Prior Art) Memory access to a memory circuit includes read access (FIG. 1 (a)) and write access (FIG. 1 (b)). As shown in these figures, assuming that one cycle of the clock 1 is one cycle, in the read access shown in FIG. 1 (a), the address 2 is sent to the memory at the first cycle and the read request 3 is made, and at the second cycle. The read read data is used as the data bus output 4. In the write access shown in FIG. 1 (b), the write data 4'according to the write request 3'is written in the memory in the first cycle. Memory access is performed by one address bus and one bidirectional data bus. A block diagram of this conventional memory circuit is shown in FIG. In the figure, this memory circuit is a random access memory circuit 11
And a timing control circuit 12, a read data output driver 13 and a write data input driver 14. First, as shown in FIG. 3, when the read request c is input together with the address data f in the first cycle, the timing control circuit 12 causes the write enable signal k
Turn off. As a result, the data is read from the memory 11 and the read data j is output within the same cycle.
At the rising edge of the clock signal e in the second cycle, the output control signal h also becomes high level, the read data j is output to the data bus a, and the read access is completed. During this time, write access is prohibited. Write request becomes possible in the third cycle, and write request d is turned on.
Then, in the timing control circuit, the write enable signal k is turned on, the output control signal h is set to low level, and the output of the read data output driver 13 is set to high impedance. At the same time, by setting the input control signal g to the high level, the write data i is written at the address designated by the address data f. In such a conventional circuit, when a read request is made in the first cycle and a write request is made in the next cycle, two read access requests are made.
Since cycles are required, write data and read data collide with each other on the data bus. For this reason, as shown in FIG. 3, the memory access must be prohibited during the two read access cycles, and the memory access efficiency cannot be improved.

(Object of the Invention) An object of the present invention is to solve the above-mentioned drawbacks, avoid collision of read data and write data on the data bus when performing read access and write access in continuous cycles, and to prevent memory access. It is to provide a memory circuit that can achieve higher efficiency and higher speed.

(Structure of the Invention) A memory circuit according to the present invention has a memory circuit, a data bus, a first driver that receives the data bus as an input and outputs the data circuit to the memory circuit, and receives read data of the memory circuit as an input. A second driver that outputs to the data bus,
A timing control circuit for controlling the first and second drivers and the memory circuit and a latch circuit for temporarily storing the read data are provided between the second driver and the memory circuit. Is characterized by.

(Example) Next, the Example of this invention is described in detail with reference to drawings.

FIG. 4 is a circuit block diagram showing a memory circuit of an embodiment of the present invention, and FIG. 5 is a timing diagram of the memory circuit of FIG. In these drawings, the present memory circuit includes a random access memory circuit 11, a timing control circuit 12, a latch circuit 15, a read data output driver 13, and a write data input driver 14. First, in the first cycle, when the read request d is input together with the address data f, the timing control circuit 12 turns off the write enable signal k. As a result, the memory circuit 11
From the memory circuit 1 in the same cycle
The read data j from 1 is recorded in the latch circuit 15.
The latch timing of the latch circuit 15 is set at the falling edge of the latch signal l synchronized with the sub clock signal obtained by delaying the clock signal e by about 1/4 cycle. When the write request d is OFF in the second cycle, the output control signal h also becomes high level at the rising edge of the clock signal e in the second cycle, and the latch data m is output to the data bus a and read. Terminate access. Second
When the write request d is turned on at the cycle, the timing control circuit 12 turns on the write enable signal k, turns the output control signal h to low level, and outputs the latch data m to the data bus a. Ban. As a result, collision of read data and write data is avoided, and read data is latched by the latch circuit 15.
Held by Further, by setting the input control signal g to the high level, the write data i is written at the address designated by the address data f.
When the write access ends, the write request signal d becomes OF.
F, the read request signal is turned on, and the output control signal h becomes high level. The read data, that is, the latch data m held by this is output to the data bus. In FIG. 5, in a continuous cycle, R1 data read request, R2 data read request,
It also shows the memory cycle timing and the like when a W1 data write request is issued.

(Effects of the Invention) As described above, according to the present invention, three types of memory access are performed: read data is read from the memory, data read from the memory is output to the data bus, and write data is written to the memory. By dividing the process into steps and performing parallel processing in a pipeline manner, it is possible to obtain an effect such that memory access in a continuous cycle can be processed at high speed.

[Brief description of drawings]

FIG. 1 (a) is a timing diagram showing a read access among memory accesses, FIG. 1 (b) is a timing diagram showing a write access among memory accesses, and FIG. 2 is a circuit block diagram showing a conventional memory circuit, FIG. 3 is a timing diagram showing a case where a read request and a write request are made in a continuous cycle in the memory circuit of FIG. 2, FIG. 4 is a circuit block diagram showing a memory circuit of an embodiment of the present invention, and FIG. FIG. 6 is a timing diagram showing a case where a read request and a write request are made in consecutive cycles in the memory circuit of FIG. In the figure, 1 ... Clock, 2, 2 '... Address, 3 ... Read request, 3' ... Write request, 4, 4 '... Data output,
11 ... Random access memory circuit, 12 ... Timing control circuit, 13 ... Output driver circuit, 14 ... Input driver circuit, 15 ... Latch circuit, a ... Data bus, b ... Output enable signal, c ... Read request signal, d ... Write request signal, e ... Clock signal, f ... Address data, g ... Input control signal, h ... Output control signal, i ...
... write data, j ... read data, k ... write enable signal, l ... latch signal, m ... latch data, R1, R2 ... read data from memory, W1 ...
… Data written to memory.

Claims (1)

[Claims] 1. A memory circuit, an address bus connected to the memory circuit, a data bus that handles read data and write data in common, and write data inserted between the data bus and the memory circuit. A first driver for outputting to the memory circuit, a second driver inserted between the data bus and the memory circuit for outputting read data from the memory circuit to the data bus, and the second driver A timing circuit that controls the memory circuit, the first and second drivers and the latch circuit, and a timing control circuit that is provided between the memory circuit and the memory circuit. The control circuit gives a write address and write data to the memory circuit in one cycle to complete the write operation,
The operation of applying the read address to the memory circuit during one cycle to complete the operation of latching the read data read in the latch circuit, and if the write cycle does not come after the read cycle, the read of the latch circuit is performed in the next cycle. The second driver is controlled so as to send out data to the data bus, and if the write cycle comes once after the read cycle, the write cycle ends and the write cycle continues after the read cycle. When it comes, the storage circuit is characterized in that the second driver is controlled so as to send the read data of the latch circuit to the data bus in a cycle after all the continuous write cycles are completed.