JPH0630415B2 - Differential circuit - Google Patents

Description

The present invention relates to a differential circuit, and more particularly to a differential circuit including a differential pair formed of FETs, a current mirror circuit and a constant current source.

[Conventional technology]

Conventionally, as shown in FIG. 4, a differential circuit of this type conventionally has a first transistor Q ₁ having a drain connected to a power supply voltage V _cc terminal and a source connected to a gate, and a drain connected to a power supply voltage V _cc terminal. And a second transistor Q ₂ having a gate connected to the gate of the transistor Q ₁ and a source connected to the output terminal T ₃ , the source of the transistor Q _{1 being} an input end and the source of the transistor Q _{2 being} an output end. And a drain connected to the source of the transistor Q ₁ and a gate connected to the signal input terminal T _{1 of} the first input signal V _I1 via the capacitor C _{1 and} having a transconductance g _m. The transistor Q ₃ and the drain are connected to the source of the transistor Q ₂ and the gate is connected to the signal input terminal T _{2 of} the second input signal V _I2 via the capacitor C _2. The source is connected to the source of the transistor Q ₃ , and a fourth transistor Q ₄ having a transconductance g _m forming a differential pair together with the transistor Q ₃ is connected to the sources of the transistors Q ₃ and Q ₄ at one end and the other end is connected to the other end. Constant current source circuit 2 having an equivalent resistance R _SS with a resistance value r _SS connected to the ground terminal
A first resistor R ₄₁ having one end connected to the gate of the transistor Q ₃ and the other end connected to the ground terminal, and a second resistor R ₄₁ having one end connected to the gate of the transistor Q ₄ and the other end connected to the ground terminal.
Comprising a resistor R _42, the resistance value r _41, r ₄₂ of the first and second resistors R _41, R ₄₂ has a normally equal.

[Problems to be Solved by the Invention]

In the conventional differential circuit described above, the drains are respectively connected to the input / output terminals of the current mirror circuit 1 and the transistors Q ₃ and Q ₄ both having the mutual conductance g _m , and the sources and ground terminals of these transistors Q ₃ and Q _4. A constant current source circuit 2 having an equivalent resistance value r _SS connected between and the resistors R ₄₁ and R ₄₂ connected between the gates of the transistors Q ₃ and Q ₄ and the ground terminal. Since the resistance values r ₄₁ and r ₄₂ of the resistors R ₄₁ and R ₄₂ are usually equal to each other, the goodness of the differential circuit is shown, and the common mode rejection ratio CMRR of the ratio of the common mode gain and the differential gain is CMRR = 1 + 2g _m r _SS (1) Since r _SS is finite, the CM ratio CM
It has the drawback that RR cannot be increased.

For example, if g _m = 7.58 mS and r _SS = 867Ω, the common mode rejection ratio CMRR can be only 23 dB.

On the other hand, small signal 3-port S-parameters | S31 |, | S32 |
From the perspective, Since there is a relationship of, from equations (1) and (2) Therefore, there is a drawback that the level difference between | S31 | and | S32 | becomes large as a result. In the case of the above example, as shown in FIG. 5, the level difference between | S31 | and | S32 | is 1.4 dB.

The object of the present invention is to increase the common mode rejection ratio,
Another object of the present invention is to provide a differential circuit capable of reducing the level difference between the small signal 3-port S-parameters | S31 | and | S32 |.

[Means for Solving the Problems]

In the differential circuit of the present invention, a drain (or source) is connected to a first power supply voltage terminal and a source (or drain) is connected to a gate, and a drain (or source) is connected to the first transistor. A second transistor having a gate connected to the gate of the first transistor and a source (or drain) connected to an output terminal, the source (or drain) of the first transistor
Is connected to the source (or the drain) of the first transistor and the gate is connected to the output impedance r. _A third transistor having a transconductance g _m connected to a first signal input terminal for inputting a signal from a first signal source having ₀ , and a drain (or a source) as a source (or a drain) of the second transistor. ) And a source (or drain) connected to the source (or drain) of the third transistor and a gate connected to the second signal input terminal for inputting a signal from a second signal source having an output impedance r ₀ ; A fourth transistor having a transconductance g _m connected to form a differential pair with the third transistor; A constant current source circuit connected to the sources (or drains) of the third and fourth transistors and the other end thereof connected to the second power supply voltage terminal and having an equivalent resistance of the resistance value r _SS ;
A _first resistor having a resistance value r _{1 having one} end connected to the gate of the third transistor and the other end connected to the second power supply voltage terminal; and one end connected to the gate of the fourth transistor and the other end Connected to the second power supply voltage terminal with a resistance value r ₂
In the differential circuit having the second resistance of, the resistance values r ₁ and r ₂ of the first and second resistances are It is configured as a resistance value that satisfies the following relational expression.

[Action]

Small signal 3-port S-parameter | S31 |, | S32 | level differences in order to correct the first and second resistor connected between the gate of the transistor Q _3, Q ₄ and the ground terminal of the signal _First and _second terminals connected to the input terminals T ₁ and T 2
Let r _{0 be} the output impedance of the signal source, and r ₁ and r ₂ be the resistance values of the first and second resistors, The following relationship should be satisfied.

Substituting equation (4) into equation (3) To obtain the relational expression.

Reducing the level difference between the small-signal three-port S-parameters | S31 | and | S32 | leads to increasing the common-mode rejection ratio CMRR as can be seen from equation (2).

Therefore, in the present invention, the resistance values r ₁ and r ₂ of the first and second resistors are selected so as to satisfy the relationship of the expression (5).

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

This embodiment differs from the conventional differential circuit shown in FIG. 4 in that the resistance values r ₁ and r ₂ of the first and second resistors R ₁ and R ₂ are The resistance value satisfies the relationship

Here, for example, the characteristic impedance of the signal source or the like is set to 50
Ω, that is, r ₀ = 50Ω, r ₂ = ₂ kΩ, g _m = 7.58
If m ₁ and r _SS = 867Ω and r ₁ is 280Ω which almost satisfies the equation (5), the common mode rejection ratio CMRR is 39 dB, and the small signal 3
The level difference between the port S parameters | S31 | and | S32 | is 0.
It is 2 dB, which is much improved as compared with the conventional examples of 23 dB and 1.4 dB.

It is to be noted that FIG. 1 also shows a source follower type output circuit 3 for taking out the output signal V ₀ of the differential circuit by lowering the output impedance.

FIG. 3 is a circuit diagram of a frequency conversion circuit using this embodiment as an image cancellation circuit. RF signal V _RFI
Is split by a 3 dB hybrid coupler 4 into two signals having the same power and a phase difference of 90 °, and input to the single balance mixers 5 _A and 5 _B.

On the other hand, the LO signal V _LOI is set to 2 by the in-phase power divider 6.
Single balance mixer 5 _A , 5 _B divided into two signals
Entered in. The IF output of the single balance mixer 5 _A is delayed by 90 ° by the 90 ° phase shifter 7, and the phase difference from the IF output of the single balance mixer 5 _B is opposite in phase to the signal and to the image component. Be in phase.

These IF outputs are input to the differential circuit 10 of the present invention,
The signal is synthesized is canceled by the image component common mode rejection function, only the signal is output to the output terminal T _3.

That is, in this application example, the differential circuit 10 of the present invention is used as an image cancellation circuit of a frequency conversion circuit,
By setting the resistance values of the resistors R ₁ and R ₂ so as to satisfy the relationship of the equation (5), there is an advantage that a much higher image suppression degree can be obtained than in the past.

〔The invention's effect〕

As described above, according to the present invention, the common mode rejection ratio limited by the equivalent resistance of the constant current source circuit is increased by setting the resistance values of the first and second resistors to values that satisfy the expression (5). And small signal 3-port S-parameter | S
The effect is that the level difference between 31 | and | S32 | can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a frequency characteristic diagram of a small signal 3-port S parameter of the embodiment shown in FIG. 3, FIG. 3 is a circuit diagram of a frequency conversion circuit using the embodiment shown in FIG. 1, and FIG. FIG. 5 is a circuit diagram showing an example of a circuit, and FIG. 5 is a frequency characteristic diagram of a small signal 3-port S parameter of the differential circuit shown in FIG. 1 ... Current mirror circuit, 2 ... Constant current source circuit, 3 ...
... Output circuit, 4 ... 3 dB hybrid coupler, 5 _A ,
5 _B ... Single balance mixer, 6 ... In-phase power distributor, 7 ... 90 ° phase shifter, 8 ... Terminator, 10 ... Differential circuit, 21 ... Constant current source, C _{1 to} C ₅ ...... _capacitor, Q 1 to Q ₇ ...... _{transistor, R 1 ~R 3, R 41} ,
R ₄₂ ... resistance, R _SS ... equivalent resistance.

Claims (1)

[Claims] 1. A first transistor having a drain (or source) connected to a first power supply voltage terminal and a source (or drain) connected to a gate, and a drain (or source) connected to the first power supply voltage terminal. A second transistor having a gate connected to the gate of the first transistor and a source (or drain) connected to an output terminal, the source (or drain) of the first transistor being an input terminal A current mirror circuit having a source (or drain) of the second transistor as an output terminal, a first (current source) having a drain (or source) connected to the source (or drain) of the first transistor, and a gate having an output impedance r ₀ a third transistor of the transconductance g _m for connecting the first signal input terminal for inputting a signal from the signal source, the drain ( A second signal having an output impedance r ₀ a gate connected to the source (or drain) and the third transistor source of the (or drain) connected to a source (or drain) of the second transistor source) A fourth transistor having a mutual conductance g _m connected to a second signal input terminal for inputting a signal from a source and forming a differential pair with the third transistor, and one end of the third and fourth transistors. A constant current source circuit connected to the source (or drain) and the other end connected to the second power supply voltage terminal and having an equivalent resistance of the resistance value r _SS ; and one end connected to the gate of the third transistor and the other end connected. A _first resistor having a resistance value r ₁ connected to the second power supply voltage terminal, and a resistor having one end connected to the gate of the fourth transistor and the other end connected to the second power supply voltage terminal. In the differential circuit having the second resistor having the value r ₂ , the resistance values r ₁ and r ₂ of the first and second resistors are A differential circuit having a resistance value that satisfies the following relational expression.